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net/mlx5: DR, Move STEv0 look up types from mlx5_ifc_dr header

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The lookup types are device specific and should not be
exposed to DR upper layers, matchers/tables.
Each HW STE version should keep them internal.
The lu_type size is updated to support larger lu_types as
required for STEv1.

Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik 2020-09-22 04:22:12 +03:00 committed by Saeed Mahameed
parent 467790985d
commit dd2d3c8d20
4 changed files with 64 additions and 60 deletions
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6
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
View File

@ -171,7 +171,7 @@ void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi)
MLX5_SET(ste_general, hw_ste_p, next_table_base_63_48, gvmi);
}
void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type,
void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type,
u16 gvmi)
{
MLX5_SET(ste_general, hw_ste_p, entry_type, entry_type);
@ -523,7 +523,7 @@ int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher,
struct mlx5dr_ste_htbl *next_htbl;
if (!mlx5dr_ste_is_last_in_rule(nic_matcher, ste->ste_chain_location)) {
u8 next_lu_type;
u16 next_lu_type;
u16 byte_mask;
next_lu_type = MLX5_GET(ste_general, hw_ste, next_lu_type);
@ -576,7 +576,7 @@ static void dr_ste_set_ctrl(struct mlx5dr_ste_htbl *htbl)
struct mlx5dr_ste_htbl *mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
enum mlx5dr_icm_chunk_size chunk_size,
u8 lu_type, u16 byte_mask)
u16 lu_type, u16 byte_mask)
{
struct mlx5dr_icm_chunk *chunk;
struct mlx5dr_ste_htbl *htbl;

70
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
View File

@ -6,9 +6,53 @@
#include "dr_ste.h"
#define DR_STE_CALC_LU_TYPE(lookup_type, rx, inner) \
((inner) ? MLX5DR_STE_LU_TYPE_##lookup_type##_I : \
(rx) ? MLX5DR_STE_LU_TYPE_##lookup_type##_D : \
MLX5DR_STE_LU_TYPE_##lookup_type##_O)
((inner) ? DR_STE_V0_LU_TYPE_##lookup_type##_I : \
(rx) ? DR_STE_V0_LU_TYPE_##lookup_type##_D : \
DR_STE_V0_LU_TYPE_##lookup_type##_O)
enum {
DR_STE_V0_LU_TYPE_NOP = 0x00,
DR_STE_V0_LU_TYPE_SRC_GVMI_AND_QP = 0x05,
DR_STE_V0_LU_TYPE_ETHL2_TUNNELING_I = 0x0a,
DR_STE_V0_LU_TYPE_ETHL2_DST_O = 0x06,
DR_STE_V0_LU_TYPE_ETHL2_DST_I = 0x07,
DR_STE_V0_LU_TYPE_ETHL2_DST_D = 0x1b,
DR_STE_V0_LU_TYPE_ETHL2_SRC_O = 0x08,
DR_STE_V0_LU_TYPE_ETHL2_SRC_I = 0x09,
DR_STE_V0_LU_TYPE_ETHL2_SRC_D = 0x1c,
DR_STE_V0_LU_TYPE_ETHL2_SRC_DST_O = 0x36,
DR_STE_V0_LU_TYPE_ETHL2_SRC_DST_I = 0x37,
DR_STE_V0_LU_TYPE_ETHL2_SRC_DST_D = 0x38,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_DST_O = 0x0d,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_DST_I = 0x0e,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_DST_D = 0x1e,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_SRC_O = 0x0f,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_SRC_I = 0x10,
DR_STE_V0_LU_TYPE_ETHL3_IPV6_SRC_D = 0x1f,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x11,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x12,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_5_TUPLE_D = 0x20,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_MISC_O = 0x29,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_MISC_I = 0x2a,
DR_STE_V0_LU_TYPE_ETHL3_IPV4_MISC_D = 0x2b,
DR_STE_V0_LU_TYPE_ETHL4_O = 0x13,
DR_STE_V0_LU_TYPE_ETHL4_I = 0x14,
DR_STE_V0_LU_TYPE_ETHL4_D = 0x21,
DR_STE_V0_LU_TYPE_ETHL4_MISC_O = 0x2c,
DR_STE_V0_LU_TYPE_ETHL4_MISC_I = 0x2d,
DR_STE_V0_LU_TYPE_ETHL4_MISC_D = 0x2e,
DR_STE_V0_LU_TYPE_MPLS_FIRST_O = 0x15,
DR_STE_V0_LU_TYPE_MPLS_FIRST_I = 0x24,
DR_STE_V0_LU_TYPE_MPLS_FIRST_D = 0x25,
DR_STE_V0_LU_TYPE_GRE = 0x16,
DR_STE_V0_LU_TYPE_FLEX_PARSER_0 = 0x22,
DR_STE_V0_LU_TYPE_FLEX_PARSER_1 = 0x23,
DR_STE_V0_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x19,
DR_STE_V0_LU_TYPE_GENERAL_PURPOSE = 0x18,
DR_STE_V0_LU_TYPE_STEERING_REGISTERS_0 = 0x2f,
DR_STE_V0_LU_TYPE_STEERING_REGISTERS_1 = 0x30,
DR_STE_V0_LU_TYPE_DONT_CARE = MLX5DR_STE_LU_TYPE_DONT_CARE,
};
static void
dr_ste_v0_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value,
@ -451,7 +495,7 @@ dr_ste_v0_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_ETHL2_TUNNELING_I;
sb->lu_type = DR_STE_V0_LU_TYPE_ETHL2_TUNNELING_I;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_tnl_tag;
}
@ -567,7 +611,7 @@ dr_ste_v0_build_tnl_gre_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_tnl_gre_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_GRE;
sb->lu_type = DR_STE_V0_LU_TYPE_GRE;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_tnl_gre_tag;
}
@ -613,7 +657,7 @@ dr_ste_v0_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_tnl_mpls_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_FLEX_PARSER_0;
sb->lu_type = DR_STE_V0_LU_TYPE_FLEX_PARSER_0;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_tnl_mpls_tag;
}
@ -704,7 +748,7 @@ dr_ste_v0_build_icmp_init(struct mlx5dr_ste_build *sb,
if (ret)
return ret;
sb->lu_type = MLX5DR_STE_LU_TYPE_FLEX_PARSER_1;
sb->lu_type = DR_STE_V0_LU_TYPE_FLEX_PARSER_1;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_icmp_tag;
@ -730,7 +774,7 @@ dr_ste_v0_build_general_purpose_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_general_purpose_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_GENERAL_PURPOSE;
sb->lu_type = DR_STE_V0_LU_TYPE_GENERAL_PURPOSE;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_general_purpose_tag;
}
@ -789,7 +833,7 @@ dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb,
struct mlx5dr_match_param *mask)
{
dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER;
sb->lu_type = DR_STE_V0_LU_TYPE_FLEX_PARSER_TNL_HEADER;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag;
}
@ -818,7 +862,7 @@ dr_ste_v0_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,
struct mlx5dr_match_param *mask)
{
dr_ste_v0_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER;
sb->lu_type = DR_STE_V0_LU_TYPE_FLEX_PARSER_TNL_HEADER;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_geneve_tag;
}
@ -844,7 +888,7 @@ dr_ste_v0_build_register_0_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_register_0_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_0;
sb->lu_type = DR_STE_V0_LU_TYPE_STEERING_REGISTERS_0;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_register_0_tag;
}
@ -870,7 +914,7 @@ dr_ste_v0_build_register_1_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_register_1_tag(mask, sb, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_1;
sb->lu_type = DR_STE_V0_LU_TYPE_STEERING_REGISTERS_1;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_register_1_tag;
}
@ -939,7 +983,7 @@ dr_ste_v0_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb,
{
dr_ste_v0_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);
sb->lu_type = MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP;
sb->lu_type = DR_STE_V0_LU_TYPE_SRC_GVMI_AND_QP;
sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
sb->ste_build_tag_func = &dr_ste_v0_build_src_gvmi_qpn_tag;
}

8
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h
View File

@ -155,7 +155,7 @@ struct mlx5dr_ste_htbl_ctrl {
};
struct mlx5dr_ste_htbl {
u8 lu_type;
u16 lu_type;
u16 byte_mask;
u32 refcount;
struct mlx5dr_icm_chunk *chunk;
@ -191,7 +191,7 @@ struct mlx5dr_ste_build {
u8 vhca_id_valid:1;
struct mlx5dr_domain *dmn;
struct mlx5dr_cmd_caps *caps;
u8 lu_type;
u16 lu_type;
u16 byte_mask;
u8 bit_mask[DR_STE_SIZE_MASK];
int (*ste_build_tag_func)(struct mlx5dr_match_param *spec,
@ -202,7 +202,7 @@ struct mlx5dr_ste_build {
struct mlx5dr_ste_htbl *
mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
enum mlx5dr_icm_chunk_size chunk_size,
u8 lu_type, u16 byte_mask);
u16 lu_type, u16 byte_mask);
int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl);
@ -220,7 +220,7 @@ static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl)
/* STE utils */
u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, u16 gvmi);
void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, u16 gvmi);
void mlx5dr_ste_always_hit_htbl(struct mlx5dr_ste *ste,
struct mlx5dr_ste_htbl *next_htbl);
void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr);

40
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h
View File

@ -50,46 +50,6 @@ enum {
};
enum {
MLX5DR_STE_LU_TYPE_NOP = 0x00,
MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP = 0x05,
MLX5DR_STE_LU_TYPE_ETHL2_TUNNELING_I = 0x0a,
MLX5DR_STE_LU_TYPE_ETHL2_DST_O = 0x06,
MLX5DR_STE_LU_TYPE_ETHL2_DST_I = 0x07,
MLX5DR_STE_LU_TYPE_ETHL2_DST_D = 0x1b,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_O = 0x08,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_I = 0x09,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_D = 0x1c,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_O = 0x36,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_I = 0x37,
MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_D = 0x38,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_O = 0x0d,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_I = 0x0e,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_D = 0x1e,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_O = 0x0f,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_I = 0x10,
MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_D = 0x1f,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x11,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x12,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_D = 0x20,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_O = 0x29,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_I = 0x2a,
MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_D = 0x2b,
MLX5DR_STE_LU_TYPE_ETHL4_O = 0x13,
MLX5DR_STE_LU_TYPE_ETHL4_I = 0x14,
MLX5DR_STE_LU_TYPE_ETHL4_D = 0x21,
MLX5DR_STE_LU_TYPE_ETHL4_MISC_O = 0x2c,
MLX5DR_STE_LU_TYPE_ETHL4_MISC_I = 0x2d,
MLX5DR_STE_LU_TYPE_ETHL4_MISC_D = 0x2e,
MLX5DR_STE_LU_TYPE_MPLS_FIRST_O = 0x15,
MLX5DR_STE_LU_TYPE_MPLS_FIRST_I = 0x24,
MLX5DR_STE_LU_TYPE_MPLS_FIRST_D = 0x25,
MLX5DR_STE_LU_TYPE_GRE = 0x16,
MLX5DR_STE_LU_TYPE_FLEX_PARSER_0 = 0x22,
MLX5DR_STE_LU_TYPE_FLEX_PARSER_1 = 0x23,
MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x19,
MLX5DR_STE_LU_TYPE_GENERAL_PURPOSE = 0x18,
MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_0 = 0x2f,
MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_1 = 0x30,
MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f,
};