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This pull request contains Broadcom ARM-based SoCs Device Tree changes

Browse Source 
for 5.18, please pull the following:
 
 - Arinc defines the switch ports of the RTL8365MB switch on the Asus
   RT-AC88U
 
 - Richard provides cache information for the BCM2835/36/37 and BCM2711
   SoCs such that tools like "lscpu -C" can report it when supported
 
 - Stefan adds support for the Raspberry Pi Zero 2 W (wireless)
 
 - Matthew defines the MAC address NVMEM cells for the Cisco Meraki
   MX64/MX65 devices, he also fixes the LED for these platforms.
 
 - Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150
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Merge tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.18, please pull the following:

- Arinc defines the switch ports of the RTL8365MB switch on the Asus
  RT-AC88U

- Richard provides cache information for the BCM2835/36/37 and BCM2711
  SoCs such that tools like "lscpu -C" can report it when supported

- Stefan adds support for the Raspberry Pi Zero 2 W (wireless)

- Matthew defines the MAC address NVMEM cells for the Cisco Meraki
  MX64/MX65 devices, he also fixes the LED for these platforms.

- Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150

* tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux:
  ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul XWR-3150
  ARM: dts: NSP: MX6X: correct LED function types
  ARM: dts: NSP: MX6X: get mac-address from eeprom
  arm64: dts: broadcom: Add reference to RPi Zero 2 W
  ARM: dts: Add Raspberry Pi Zero 2 W
  dt-bindings: arm: bcm2835: Add Raspberry Pi Zero 2 W
  ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
  ARM: dts: bcm2711: Add the missing L1/L2 cache information
  ARM: dts: bcm2837: Add the missing L1/L2 cache information
  ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U

Link: https://lore.kernel.org/r/20220307194817.3754107-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-03-08 16:25:36 +01:00
commit dd5d787f48
14 changed files with 403 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
View File

@ -51,6 +51,7 @@ properties:
- raspberrypi,3-model-b-plus
- raspberrypi,3-compute-module
- raspberrypi,3-compute-module-lite
- raspberrypi,model-zero-2-w
- const: brcm,bcm2837
additionalProperties: true

1
arch/arm/boot/dts/Makefile
View File

@ -93,6 +93,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2837-rpi-zero-2-w.dtb \
bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \

50
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -458,12 +458,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
/* Source for d/i-cache-line-size and d/i-cache-sets
* https://developer.arm.com/documentation/100095/0003
* /Level-1-Memory-System/About-the-L1-memory-system?lang=en
* Source for d/i-cache-size
* https://www.raspberrypi.com/documentation/computers
* /processors.html#bcm2711
*/
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@ -472,6 +486,13 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@ -480,6 +501,13 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@ -488,6 +516,28 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
next-level-cache = <&l2>;
};
/* Source for d/i-cache-line-size and d/i-cache-sets
* https://developer.arm.com/documentation/100095/0003
* /Level-2-Memory-System/About-the-L2-memory-system?lang=en
* Source for d/i-cache-size
* https://www.raspberrypi.com/documentation/computers
* /processors.html#bcm2711
*/
l2: l2-cache0 {
compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
cache-level = <2>;
};
};

17
arch/arm/boot/dts/bcm2835.dtsi
View File

@ -14,6 +14,23 @@
device_type = "cpu";
compatible = "arm,arm1176jzf-s";
reg = <0x0>;
/* Source for d/i-cache-line-size and d/i-cache-sets
* https://developer.arm.com/documentation/ddi0301
* /h/level-one-memory-system/cache-organization?lang=en
*
* Source for d/i-cache-size
* https://forums.raspberrypi.com/viewtopic.php?t=98428
*
* NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU
* It can be shared with the CPU through fw settings,
* but this is not recommended.
*/
d-cache-size = <0x4000>;
d-cache-line-size = <16>;
d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
i-cache-size = <0x4000>;
i-cache-line-size = <16>;
i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
};
};

50
arch/arm/boot/dts/bcm2836.dtsi
View File

@ -41,11 +41,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp";
/* Source for d/i-cache-line-size and d/i-cache-sets
* https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
* /About-the-L1-memory-system?lang=en
*
* Source for d/i-cache-size
* https://forums.raspberrypi.com/viewtopic.php?t=98428
*/
v7_cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
clock-frequency = <800000000>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
next-level-cache = <&l2>;
};
v7_cpu1: cpu@1 {
@ -53,6 +68,13 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
clock-frequency = <800000000>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
next-level-cache = <&l2>;
};
v7_cpu2: cpu@2 {
@ -60,6 +82,13 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
clock-frequency = <800000000>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
next-level-cache = <&l2>;
};
v7_cpu3: cpu@3 {
@ -67,6 +96,27 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
clock-frequency = <800000000>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <32>;
i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
next-level-cache = <&l2>;
};
/* Source for cache-line-size + cache-sets
* https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
* /About-the-L2-Memory-system?lang=en
* Source for cache-size
* https://forums.raspberrypi.com/viewtopic.php?t=98428
*/
l2: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
cache-level = <2>;
};
};
};

136
arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts Normal file
View File

@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Stefan Wahren <stefan.wahren@i2se.com>
*/
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837";
model = "Raspberry Pi Zero 2 W";
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
leds {
led-act {
gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
};
};
};
&bt {
shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
&gpio {
/*
* This is based on the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD0",
"RXD0",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"HDMI_HPD_N",
"STATUS_LED_N",
"NC", /* GPIO30 */
"NC", /* GPIO31 */
"NC", /* GPIO32 */
"NC", /* GPIO33 */
"NC", /* GPIO34 */
"NC", /* GPIO35 */
"NC", /* GPIO36 */
"NC", /* GPIO37 */
"NC", /* GPIO38 */
"NC", /* GPIO39 */
"CAM_GPIO0", /* GPIO40 */
"WL_ON", /* GPIO41 */
"BT_ON", /* GPIO42 */
"WIFI_CLK", /* GPIO43 */
"SDA0", /* GPIO44 */
"SCL0", /* GPIO45 */
"SMPS_SCL",
"SMPS_SDA",
/* Used by SD Card */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&sdhci {
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};

49
arch/arm/boot/dts/bcm2837.dtsi
View File

@ -40,12 +40,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
/* Source for d/i-cache-line-size and d/i-cache-sets
* https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
* /about-the-l1-memory-system?lang=en
*
* Source for d/i-cache-size
* https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
*/
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@ -54,6 +68,13 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@ -62,6 +83,13 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@ -70,6 +98,27 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
next-level-cache = <&l2>;
};
/* Source for cache-line-size + cache-sets
* https://developer.arm.com/documentation/ddi0500
* /e/level-2-memory-system/about-the-l2-memory-system?lang=en
* Source for cache-size
* https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
*/
l2: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
cache-level = <2>;
};
};
};

76
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
View File

@ -93,6 +93,82 @@
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
};
switch {
compatible = "realtek,rtl8365mb";
/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
realtek,disable-leds;
dsa,member = <1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan5";
phy-handle = <&ethphy0>;
};
port@1 {
reg = <1>;
label = "lan6";
phy-handle = <&ethphy1>;
};
port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&ethphy2>;
};
port@3 {
reg = <3>;
label = "lan8";
phy-handle = <&ethphy3>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&sw0_p5>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <2100>;
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
mdio {
compatible = "realtek,smi-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
};
};
};
};
&srab {

8
arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
View File

@ -25,6 +25,9 @@
nvram@1eff0000 {
compatible = "brcm,nvram";
reg = <0x1eff0000 0x10000>;
et0macaddr: et0macaddr {
};
};
leds {
@ -72,6 +75,11 @@
};
};
&gmac0 {
nvmem-cells = <&et0macaddr>;
nvmem-cell-names = "mac-address";
};
&usb3 {
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};

3
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
View File

@ -57,10 +57,9 @@
led-4 {
/* amber:power */
function = LED_FUNCTION_POWER;
function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led-5 {

3
arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
View File

@ -106,10 +106,9 @@
led-a {
/* amber:power */
function = LED_FUNCTION_POWER;
function = LED_FUNCTION_FAULT;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-b {

10
arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
View File

@ -22,7 +22,7 @@
};
led-2 {
function = LED_FUNCTION_INDICATOR;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
pwms = <&pwm 2 50000>;
max-brightness = <255>;
@ -39,6 +39,8 @@
&amac2 {
status = "okay";
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
};
&ehci0 {
@ -53,6 +55,12 @@
reg = <0x50>;
pagesize = <32>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
mac_address: mac-address@66 {
reg = <0x66 0x6>;
};
};
};

3
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -5,7 +5,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb
bcm2837-rpi-cm3-io3.dtb \
bcm2837-rpi-zero-2-w.dtb
subdir-y += bcm4908
subdir-y += northstar2

2
arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts Normal file
View File

@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-zero-2-w.dts"