net: stmmac: rearrange RX and TX desc init into per-queue basis
Below functions are made to be per-queue in preparation of XDP ZC: __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) The original functions below are stay maintained for all queue usage: init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) init_dma_tx_desc_rings(struct net_device *dev) Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ong Boon Leong
David S. Miller
parent
da5ec7f22a
commit
de0b90e52a
@ -1575,60 +1575,70 @@ err_reinit_rx_buffers:
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}
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/**
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* init_dma_rx_desc_rings - init the RX descriptor rings
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* @dev: net device structure
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* __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
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* @priv: driver private structure
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* @queue: RX queue index
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* @flags: gfp flag.
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* Description: this function initializes the DMA RX descriptors
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* and allocates the socket buffers. It supports the chained and ring
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* modes.
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*/
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static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
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{
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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int ret;
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netif_dbg(priv, probe, priv->dev,
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"(%s) dma_rx_phy=0x%08x\n", __func__,
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(u32)rx_q->dma_rx_phy);
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stmmac_clear_rx_descriptors(priv, queue);
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WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
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MEM_TYPE_PAGE_POOL,
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rx_q->page_pool));
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netdev_info(priv->dev,
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"Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
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rx_q->queue_index);
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ret = stmmac_alloc_rx_buffers(priv, queue, flags);
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if (ret < 0)
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return -ENOMEM;
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rx_q->cur_rx = 0;
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rx_q->dirty_rx = 0;
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/* Setup the chained descriptor addresses */
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if (priv->mode == STMMAC_CHAIN_MODE) {
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if (priv->extend_desc)
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stmmac_mode_init(priv, rx_q->dma_erx,
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rx_q->dma_rx_phy,
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priv->dma_rx_size, 1);
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else
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stmmac_mode_init(priv, rx_q->dma_rx,
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rx_q->dma_rx_phy,
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priv->dma_rx_size, 0);
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}
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return 0;
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}
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static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
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{
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struct stmmac_priv *priv = netdev_priv(dev);
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u32 rx_count = priv->plat->rx_queues_to_use;
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int ret = -ENOMEM;
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int queue;
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u32 queue;
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int ret;
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/* RX INITIALIZATION */
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netif_dbg(priv, probe, priv->dev,
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"SKB addresses:\nskb\t\tskb data\tdma data\n");
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for (queue = 0; queue < rx_count; queue++) {
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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netif_dbg(priv, probe, priv->dev,
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"(%s) dma_rx_phy=0x%08x\n", __func__,
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(u32)rx_q->dma_rx_phy);
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stmmac_clear_rx_descriptors(priv, queue);
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WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
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MEM_TYPE_PAGE_POOL,
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rx_q->page_pool));
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netdev_info(priv->dev,
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"Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
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rx_q->queue_index);
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ret = stmmac_alloc_rx_buffers(priv, queue, flags);
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if (ret < 0)
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ret = __init_dma_rx_desc_rings(priv, queue, flags);
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if (ret)
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goto err_init_rx_buffers;
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rx_q->cur_rx = 0;
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rx_q->dirty_rx = 0;
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/* Setup the chained descriptor addresses */
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if (priv->mode == STMMAC_CHAIN_MODE) {
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if (priv->extend_desc)
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stmmac_mode_init(priv, rx_q->dma_erx,
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rx_q->dma_rx_phy,
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priv->dma_rx_size, 1);
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else
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stmmac_mode_init(priv, rx_q->dma_rx,
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rx_q->dma_rx_phy,
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priv->dma_rx_size, 0);
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}
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}
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return 0;
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@ -1647,62 +1657,72 @@ err_init_rx_buffers:
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}
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/**
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* init_dma_tx_desc_rings - init the TX descriptor rings
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* @dev: net device structure.
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* __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
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* @priv: driver private structure
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* @queue : TX queue index
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* Description: this function initializes the DMA TX descriptors
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* and allocates the socket buffers. It supports the chained and ring
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* modes.
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*/
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static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
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{
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
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int i;
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netif_dbg(priv, probe, priv->dev,
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"(%s) dma_tx_phy=0x%08x\n", __func__,
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(u32)tx_q->dma_tx_phy);
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/* Setup the chained descriptor addresses */
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if (priv->mode == STMMAC_CHAIN_MODE) {
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if (priv->extend_desc)
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stmmac_mode_init(priv, tx_q->dma_etx,
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tx_q->dma_tx_phy,
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priv->dma_tx_size, 1);
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else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
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stmmac_mode_init(priv, tx_q->dma_tx,
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tx_q->dma_tx_phy,
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priv->dma_tx_size, 0);
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}
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for (i = 0; i < priv->dma_tx_size; i++) {
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struct dma_desc *p;
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if (priv->extend_desc)
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p = &((tx_q->dma_etx + i)->basic);
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &((tx_q->dma_entx + i)->basic);
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else
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p = tx_q->dma_tx + i;
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stmmac_clear_desc(priv, p);
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tx_q->tx_skbuff_dma[i].buf = 0;
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tx_q->tx_skbuff_dma[i].map_as_page = false;
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tx_q->tx_skbuff_dma[i].len = 0;
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tx_q->tx_skbuff_dma[i].last_segment = false;
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tx_q->tx_skbuff[i] = NULL;
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}
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tx_q->dirty_tx = 0;
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tx_q->cur_tx = 0;
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tx_q->mss = 0;
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netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
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return 0;
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}
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static int init_dma_tx_desc_rings(struct net_device *dev)
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{
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struct stmmac_priv *priv = netdev_priv(dev);
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u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
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u32 tx_queue_cnt;
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u32 queue;
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int i;
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for (queue = 0; queue < tx_queue_cnt; queue++) {
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struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
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tx_queue_cnt = priv->plat->tx_queues_to_use;
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netif_dbg(priv, probe, priv->dev,
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"(%s) dma_tx_phy=0x%08x\n", __func__,
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(u32)tx_q->dma_tx_phy);
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/* Setup the chained descriptor addresses */
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if (priv->mode == STMMAC_CHAIN_MODE) {
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if (priv->extend_desc)
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stmmac_mode_init(priv, tx_q->dma_etx,
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tx_q->dma_tx_phy,
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priv->dma_tx_size, 1);
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else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
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stmmac_mode_init(priv, tx_q->dma_tx,
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tx_q->dma_tx_phy,
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priv->dma_tx_size, 0);
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}
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for (i = 0; i < priv->dma_tx_size; i++) {
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struct dma_desc *p;
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if (priv->extend_desc)
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p = &((tx_q->dma_etx + i)->basic);
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else if (tx_q->tbs & STMMAC_TBS_AVAIL)
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p = &((tx_q->dma_entx + i)->basic);
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else
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p = tx_q->dma_tx + i;
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stmmac_clear_desc(priv, p);
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tx_q->tx_skbuff_dma[i].buf = 0;
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tx_q->tx_skbuff_dma[i].map_as_page = false;
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tx_q->tx_skbuff_dma[i].len = 0;
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tx_q->tx_skbuff_dma[i].last_segment = false;
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tx_q->tx_skbuff[i] = NULL;
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}
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tx_q->dirty_tx = 0;
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tx_q->cur_tx = 0;
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tx_q->mss = 0;
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netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
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}
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for (queue = 0; queue < tx_queue_cnt; queue++)
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__init_dma_tx_desc_rings(priv, queue);
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return 0;
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}
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