wifi: iwlwifi: mvm: limit EHT 320 MHz MCS for STEP URM
If the STEP (the interface between MAC and PHY) is in URM (a lower speed mode) then we cannot use 320 MHz MCS > 9. Therefore, limit the MCS in our capabilities in this case. Note that this also limits the TX/rate scaling since that takes both TX and RX capabilities into account. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Reviewed-by: Gregory Greenman <gregory.greenman@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://msgid.link/20240123200528.02bae683b7fc.Id5efbb71d45da02c8c4e211d20396637ddd44da8@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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@ -1061,6 +1061,11 @@ iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
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~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
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}
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if (trans->step_urm) {
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iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0;
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iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0;
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}
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if (trans->no_160)
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iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &=
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~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
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@ -374,6 +374,9 @@ enum {
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#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938
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#define CNVI_SCU_SEQ_DATA_DW9 0xA27488
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#define CNVI_PMU_STEP_FLOW 0xA2D588
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#define CNVI_PMU_STEP_FLOW_FORCE_URM BIT(2)
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#define PREG_AUX_BUS_WPROT_0 0xA04CC0
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/* device family 9000 WPROT register */
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@ -1070,6 +1070,7 @@ struct iwl_trans_txqs {
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* @invalid_tx_cmd: invalid TX command buffer
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* @reduced_cap_sku: reduced capability supported SKU
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* @no_160: device not supporting 160 MHz
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* @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz
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*/
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struct iwl_trans {
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bool csme_own;
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@ -1093,7 +1094,8 @@ struct iwl_trans {
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char hw_id_str[52];
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u32 sku_id[3];
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bool reduced_cap_sku;
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u8 no_160;
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u8 no_160:1, step_urm:1;
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u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
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bool pm_support;
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@ -677,6 +677,11 @@ static int iwl_run_unified_mvm_ucode(struct iwl_mvm *mvm)
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iwl_dbg_tlv_time_point(&mvm->fwrt, IWL_FW_INI_TIME_POINT_AFTER_ALIVE,
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NULL);
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if (mvm->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_BZ)
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mvm->trans->step_urm = !!(iwl_read_umac_prph(mvm->trans,
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CNVI_PMU_STEP_FLOW) &
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CNVI_PMU_STEP_FLOW_FORCE_URM);
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/* Send init config command to mark that we are sending NVM access
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* commands
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*/
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