clk: renesas: Add minimal boot support for RZ/G3S SoC
Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea
Geert Uytterhoeven
parent
a96aed0636
commit
de60a3ebe4
@ -37,6 +37,7 @@ config CLK_RENESAS
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select CLK_R9A07G043 if ARCH_R9A07G043
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_R9A08G045 if ARCH_R9A08G045
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_SH73A0 if ARCH_SH73A0
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@ -179,6 +180,10 @@ config CLK_R9A07G054
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bool "RZ/V2L clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A08G045
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bool "RZ/G3S clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A09G011
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bool "RZ/V2M clock support" if COMPILE_TEST
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select CLK_RZG2L
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@ -215,7 +220,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
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This is a driver for R-Car USB2 clock selector
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config CLK_RZG2L
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bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
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bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
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@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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214
drivers/clk/renesas/r9a08g045-cpg.c
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214
drivers/clk/renesas/r9a08g045-cpg.c
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@ -0,0 +1,214 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3S CPG driver
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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#include "rzg2l-cpg.h"
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/* RZ/G3S Specific registers. */
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#define G3S_CPG_PL2_DDIV (0x204)
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#define G3S_CPG_SDHI_DDIV (0x218)
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#define G3S_CPG_PLL_DSEL (0x240)
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#define G3S_CPG_SDHI_DSEL (0x244)
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#define G3S_CLKDIVSTATUS (0x280)
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#define G3S_CLKSELSTATUS (0x284)
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/* RZ/G3S Specific division configuration. */
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#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3)
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#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
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/* RZ/G3S Clock status configuration. */
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#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
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#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1)
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#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1)
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#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1)
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#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1)
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#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1)
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#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1)
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#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1)
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/* RZ/G3S Specific clocks select. */
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#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1)
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#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
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/* PLL 1/4/6 configuration registers macro. */
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#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
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#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
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DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
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.parent_names = (_parent_names), \
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.num_parents = ARRAY_SIZE((_parent_names)), \
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.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
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.flag = (_clk_flags))
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A08G045_SWD,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV2_8,
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CLK_PLL2_DIV6,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_8,
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CLK_PLL3_DIV6,
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CLK_PLL4,
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CLK_PLL6,
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CLK_PLL6_DIV2,
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CLK_SEL_SDHI0,
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CLK_SEL_PLL4,
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CLK_P1_DIV2,
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CLK_P3_DIV2,
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CLK_SD0_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_1_2[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_1_8[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_1_32[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 4, 32 },
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{ 0, 0 },
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};
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/* Mux clock names tables. */
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static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" };
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static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" };
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/* Mux clock indices tables. */
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static const u32 mtable_sd[] = { 0, 2, 3 };
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static const u32 mtable_pll4[] = { 0, 1 };
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static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
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DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
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DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8),
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DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6),
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DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2),
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DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi,
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mtable_sd, 0, NULL),
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DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4,
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mtable_pll4, CLK_SET_PARENT_GATE, NULL),
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/* Core output clk */
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DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
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0, 0, 0, NULL),
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DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS,
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dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
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rzg3s_cpg_div_clk_notifier),
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DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4),
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DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
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DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2),
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DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
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DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
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DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
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};
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static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
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DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
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DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
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DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
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DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
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DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
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DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
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DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
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DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
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DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
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};
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static const struct rzg2l_reset r9a08g045_resets[] = {
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DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
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DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
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DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
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DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
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DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
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DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
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};
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static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
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MOD_CLK_BASE + R9A08G045_IA55_CLK,
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MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
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};
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const struct rzg2l_cpg_info r9a08g045_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a08g045_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a08g045_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a08g045_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a08g045_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
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.num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
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/* Resets */
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.resets = r9a08g045_resets,
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.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
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.has_clk_mon_regs = true,
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};
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@ -1706,6 +1706,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
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.data = &r9a07g054_cpg_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A08G045
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{
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.compatible = "renesas,r9a08g045-cpg",
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.data = &r9a08g045_cpg_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A09G011
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{
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.compatible = "renesas,r9a09g011-cpg",
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@ -284,6 +284,7 @@ struct rzg2l_cpg_info {
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extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
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extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
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extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
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extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
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extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
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int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);
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