ARM: DRA7: hwmod: Add OCP2SCP3 module
This module is needed for the SATA and PCIe PHYs. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
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},
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};
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/* ocp2scp3 */
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static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
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.name = "ocp2scp3",
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.class = &dra7xx_ocp2scp_hwmod_class,
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.clkdm_name = "l3init_clkdm",
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'qspi' class
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*
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@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> ocp2scp3 */
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static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
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.master = &dra7xx_l4_cfg_hwmod,
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.slave = &dra7xx_ocp2scp3_hwmod,
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.clk = "l4_root_clk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
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{
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.pa_start = 0x4b300000,
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@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
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&dra7xx_l4_per1__mmc4,
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&dra7xx_l4_cfg__mpu,
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&dra7xx_l4_cfg__ocp2scp1,
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&dra7xx_l4_cfg__ocp2scp3,
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&dra7xx_l3_main_1__qspi,
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&dra7xx_l4_cfg__sata,
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&dra7xx_l4_cfg__smartreflex_core,
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