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iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better

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Assuming that any SMMU can enforce coherency for any device is clearly
nonsense. Although technically even a single SMMU instance can be wired
up to only be capable of emitting coherent traffic for some of the
devices it translates, it's a fairly realistic approximation that if the
SMMU's pagetable walker is wired up to a coherent interconnect then all
its translation units probably are too, and conversely that lack of
coherent table walks implies a non-coherent system in general. Either
way it's still less inaccurate than what we've been claiming so far.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/106c9741415f0b6358c72d53ae9c78c553a2b45c.1660574547.git.robin.murphy@arm.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Robin Murphy 2022-08-15 16:26:50 +01:00 committed by Joerg Roedel
parent 359ad15763
commit df198b37e7
2 changed files with 8 additions and 6 deletions
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5
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
View File

@ -1994,9 +1994,12 @@ static const struct iommu_flush_ops arm_smmu_flush_ops = {
/* IOMMU API */ /* IOMMU API */
static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap)
{ {
struct arm_smmu_master *master = dev_iommu_priv_get(dev);
switch (cap) { switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY: case IOMMU_CAP_CACHE_COHERENCY:
return true; /* Assume that a coherent TCU implies coherent TBUs */
return master->smmu->features & ARM_SMMU_FEAT_COHERENCY;
case IOMMU_CAP_NOEXEC: case IOMMU_CAP_NOEXEC:
return true; return true;
default: default:

9
drivers/iommu/arm/arm-smmu/arm-smmu.c
View File

@ -1332,13 +1332,12 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap)
{ {
struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
switch (cap) { switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY: case IOMMU_CAP_CACHE_COHERENCY:
/* /* Assume that a coherent TCU implies coherent TBUs */
* Return true here as the SMMU can always send out coherent return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;
* requests.
*/
return true;
case IOMMU_CAP_NOEXEC: case IOMMU_CAP_NOEXEC:
return true; return true;
default: default: