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sparc32: fix build of pcic

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Left-overs for an earlier iteration of the generic clock events patch removed.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Kirill Tkhai <tkhai@yandex.ru>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sam Ravnborg 2012-04-16 21:50:49 +02:00 committed by David S. Miller
parent 62f082830d
commit df2e7f525d
1 changed files with 3 additions and 3 deletions
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6
arch/sparc/kernel/pcic.c
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@ -722,7 +722,7 @@ static unsigned int pcic_cycles_offset(void)
*/
count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
/* Coordinate with the fact that timer_cs rate is 2MHz */
/* Coordinate with the sparc_config.clock_rate setting */
return count * 2;
}
@ -735,10 +735,10 @@ void __init pci_time_init(void)
#ifndef CONFIG_SMP
/*
* It's in SBUS dimension, because timer_cs is in this dimension.
* The clock_rate is in SBUS dimension.
* We take into account this in pcic_cycles_offset()
*/
timer_cs_period = SBUS_CLOCK_RATE / HZ;
sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
sparc_config.features |= FEAT_L10_CLOCKEVENT;
#endif
sparc_config.features |= FEAT_L10_CLOCKSOURCE;