From 1fb7a9fb6295220eb96c490581316b35fce180fe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 10 May 2022 12:06:52 +0100 Subject: [PATCH 01/93] clk: renesas: r9a07g044: Add GPT clock and reset entry Add GPT clock and reset entry to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220510110653.7326-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index b288897852c7..cd2777abd957 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[71]; + struct rzg2l_mod_clk common[72]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -204,6 +204,8 @@ static const struct { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), + DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, + 0x540, 0), DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, @@ -346,6 +348,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), From b6ee0bbf388ab38384f92339aa9a1df15e716cfe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 10 May 2022 12:06:53 +0100 Subject: [PATCH 02/93] clk: renesas: r9a07g044: Add POEG clock and reset entries Add POEG clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index cd2777abd957..fd7c4eecd398 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[72]; + struct rzg2l_mod_clk common[76]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -206,6 +206,14 @@ static const struct { 0x534, 2), DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 0x540, 0), + DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, + 0x544, 0), + DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, + 0x544, 1), + DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, + 0x544, 2), + DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, + 0x544, 3), DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, @@ -349,6 +357,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), + DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), + DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), + DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), + DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2), From e55c4481e71de79d0ef566a238332bd346cef6de Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 18 May 2022 14:52:08 +0100 Subject: [PATCH 03/93] clk: renesas: r9a09g011: Add PFC clock and reset entries Add PFC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 40693bb85b80..b01d79a73dd8 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -126,6 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { }; static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { + DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), @@ -137,6 +138,7 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { }; static const struct rzg2l_reset r9a09g011_resets[] = { + DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), }; From efded37b426f4e1b7b004b1e9924ff4bf16ec0fd Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 18 May 2022 16:01:05 +0100 Subject: [PATCH 04/93] clk: renesas: r9a09g011: Add WDT clock and reset entries Add WDT0 clock and reset entries to CPG driver. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index b01d79a73dd8..b21915cf6648 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -132,6 +132,8 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), + DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), @@ -141,6 +143,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), + DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), }; static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { From f46efcc4746f5c1a539df9db625c04321f75e494 Mon Sep 17 00:00:00 2001 From: Ralph Siemsen Date: Wed, 18 May 2022 13:27:16 -0400 Subject: [PATCH 05/93] clk: renesas: r9a06g032: Drop some unused fields Remove unused fields from struct r9a06g032_clkdesc. As the D_UGATE macro no longer uses _gi, drop it from all declarations. Signed-off-by: Ralph Siemsen Reviewed-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518172808.1691450-2-ralph.siemsen@linaro.org Link: https://lore.kernel.org/r/20220518172808.1691450-3-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 35ffc462af1a..88865bb8bf94 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -51,11 +51,9 @@ struct r9a06g032_clkdesc { struct { u16 div, mul; }; - unsigned int factor; - unsigned int frequency; /* for dual gate */ struct { - uint16_t group : 1, index: 3; + uint16_t group : 1; u16 sel, g1, r1, g2, r2; } dual; }; @@ -85,10 +83,10 @@ struct r9a06g032_clkdesc { .source = 1 + R9A06G032_##_src, .name = _n, \ .reg = _reg, .div_min = _min, .div_max = _max, \ .div_table = { __VA_ARGS__ } } -#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \ +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ .source = 1 + R9A06G032_##_src, .name = _n, \ - .dual = { .group = _g, .index = _gi, \ + .dual = { .group = _g, \ .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, } enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE }; @@ -303,14 +301,14 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .dual.sel = ((0x34 / 4) << 5) | 30, .dual.group = 1, }, - D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), - D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9), - D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd), - D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763), - D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767), - D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b), - D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f), - D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773), + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9), + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd), + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763), + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767), + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b), + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f), + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773), }; struct r9a06g032_priv { From 2dee50ab9e72a3cae75b65e5934c8dd3e9bf01bc Mon Sep 17 00:00:00 2001 From: Ralph Siemsen Date: Wed, 18 May 2022 14:25:27 -0400 Subject: [PATCH 06/93] clk: renesas: r9a06g032: Fix UART clkgrp bitsel There are two UART clock groups, each having a mux to select its upstream clock source. The register/bit definitions for accessing these two muxes appear to have been reversed since introduction. Correct them so as to match the hardware manual. Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Ralph Siemsen Reviewed-by: Phil Edworthy Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 88865bb8bf94..1488c9d6e639 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -288,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .name = "uart_group_012", .type = K_BITSEL, .source = 1 + R9A06G032_DIV_UART, - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ - .dual.sel = ((0xec / 4) << 5) | 24, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ + .dual.sel = ((0x34 / 4) << 5) | 30, .dual.group = 0, }, { @@ -297,8 +297,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .name = "uart_group_34567", .type = K_BITSEL, .source = 1 + R9A06G032_DIV_P2_PG, - /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ - .dual.sel = ((0x34 / 4) << 5) | 30, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ + .dual.sel = ((0xec / 4) << 5) | 24, .dual.group = 1, }, D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), From 02c96ed9e4cd1f47bfcd10296fec6b0b69d6b3c6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 31 May 2022 08:16:57 +0100 Subject: [PATCH 07/93] clk: renesas: rzg2l: Fix reset status function As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means reset signal is not applied (deassert state) and 1 means reset signal is applied (assert state). reset_control_status() expects a positive value if the reset line is asserted. But rzg2l_cpg_status function returns zero for asserted state. This patch fixes the issue by adding double inverted logic, so that reset_control_status returns a positive value if the reset line is asserted. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index e2999ab2b53c..3ff6ecd61756 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, s8 monbit = info->resets[id].monbit; if (info->has_clk_mon_regs) { - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); } else if (monbit >= 0) { u32 monbitmask = BIT(monbit); From 61a6737fcad8810258bdf1329f063b58ac27b230 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 25 May 2022 17:11:30 +0200 Subject: [PATCH 08/93] clk: renesas: r8a779f0: Add thermal clock Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220525151130.24103-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index c17ebe6b5992..0aec5e8ffd96 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), + DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), }; From 75fe45a000a70ea35e2071eb7f8b873648590982 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sat, 4 Jun 2022 01:34:37 +0200 Subject: [PATCH 09/93] clk: renesas: r8a779f0: Add SDHI0 clock Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 0aec5e8ffd96..e6f41b9f765a 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), + DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), From 65d012e415bb3592cd1c492195ff19088166198b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:10 +0200 Subject: [PATCH 10/93] clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg The register block base pointer as stored in the reg member of the r8a73a4_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a73a4_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f835f3dfcf3bf754065e5002663952cc6341caac.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a73a4.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c index cfed11c659d9..f45c2c45808b 100644 --- a/drivers/clk/renesas/clk-r8a73a4.c +++ b/drivers/clk/renesas/clk-r8a73a4.c @@ -18,7 +18,6 @@ struct r8a73a4_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_CKSCR 0xc0 @@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = { static struct clk * __init r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; const char *parent_name; @@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, if (!strcmp(name, "main")) { - u32 ckscr = readl(cpg->reg + CPG_CKSCR); + u32 ckscr = readl(base + CPG_CKSCR); switch ((ckscr >> 28) & 3) { case 0: /* extal1 */ @@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, * clock implementation and we currently have no need to change * the multiplier value. */ - u32 value = readl(cpg->reg + CPG_PLL0CR); + u32 value = readl(base + CPG_PLL0CR); parent_name = "main"; mult = ((value >> 24) & 0x7f) + 1; if (value & BIT(20)) div = 2; } else if (!strcmp(name, "pll1")) { - u32 value = readl(cpg->reg + CPG_PLL1CR); + u32 value = readl(base + CPG_PLL1CR); parent_name = "main"; /* XXX: enable bit? */ @@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, default: return ERR_PTR(-EINVAL); } - value = readl(cpg->reg + cr); + value = readl(base + cr); switch ((value >> 5) & 7) { case 0: parent_name = "main"; @@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, shift = 0; } div *= 32; - mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); + mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f); } else { struct div4_clk *c; @@ -181,7 +180,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, 4, 0, + base + reg, shift, 4, 0, table, &cpg->lock); } } @@ -189,6 +188,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, static void __init r8a73a4_cpg_clocks_init(struct device_node *np) { struct r8a73a4_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; for (i = 0; i < num_clks; ++i) { @@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a73a4_cpg_register_clock(np, cpg, name); + clk = r8a73a4_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From a00d077aaa17c873ae1f465c5564d5d88e14d8f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:11 +0200 Subject: [PATCH 11/93] clk: renesas: r8a7740: Remove r8a7740_cpg.reg The register block base pointer as stored in the reg member of the r8a7740_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to r8a7740_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/7ec676bcc36ef1eda02c2db328c527fc5fd44e99.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7740.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c index d8190f007a81..3ee3f57e4e9a 100644 --- a/drivers/clk/renesas/clk-r8a7740.c +++ b/drivers/clk/renesas/clk-r8a7740.c @@ -18,7 +18,6 @@ struct r8a7740_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_FRQCRA 0x00 @@ -61,7 +60,7 @@ static u32 cpg_mode __initdata; static struct clk * __init r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; const char *parent_name; @@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, * clock implementation and we currently have no need to change * the multiplier value. */ - u32 value = readl(cpg->reg + CPG_FRQCRC); + u32 value = readl(base + CPG_FRQCRC); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; } else if (!strcmp(name, "pllc1")) { - u32 value = readl(cpg->reg + CPG_FRQCRA); + u32 value = readl(base + CPG_FRQCRA); parent_name = "system"; mult = ((value >> 24) & 0x7f) + 1; div = 2; } else if (!strcmp(name, "pllc2")) { - u32 value = readl(cpg->reg + CPG_PLLC2CR); + u32 value = readl(base + CPG_PLLC2CR); parent_name = "system"; mult = ((value >> 24) & 0x3f) + 1; } else if (!strcmp(name, "usb24s")) { - u32 value = readl(cpg->reg + CPG_USBCKCR); + u32 value = readl(base + CPG_USBCKCR); if (value & BIT(7)) /* extal2 */ parent_name = of_clk_get_parent_name(np, 1); @@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, 4, 0, + base + reg, shift, 4, 0, table, &cpg->lock); } } @@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, static void __init r8a7740_cpg_clocks_init(struct device_node *np) { struct r8a7740_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; for (i = 0; i < num_clks; ++i) { @@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7740_cpg_register_clock(np, cpg, name); + clk = r8a7740_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From 3849716ad32ed80dc27de06a5c377ee4b7378ac2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:12 +0200 Subject: [PATCH 12/93] clk: renesas: sh73a0: Remove sh73a0_cpg.reg The register block base pointer as stored in the reg member of the sh73a0_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to sh73a0_cpg_register_clock(). Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/5423e43d0cf518691965412fb510097d23ac5955.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-sh73a0.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c index 4146c1d717b9..8c51090f13e1 100644 --- a/drivers/clk/renesas/clk-sh73a0.c +++ b/drivers/clk/renesas/clk-sh73a0.c @@ -18,7 +18,6 @@ struct sh73a0_cpg { struct clk_onecell_data data; spinlock_t lock; - void __iomem *reg; }; #define CPG_FRQCRA 0x00 @@ -73,7 +72,7 @@ static const struct clk_div_table z_div_table[] = { static struct clk * __init sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, - const char *name) + void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; unsigned int shift, reg, width; @@ -83,12 +82,12 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, if (!strcmp(name, "main")) { /* extal1, extal1_div2, extal2, extal2_div2 */ - u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; + u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3; parent_name = of_clk_get_parent_name(np, parent_idx >> 1); div = (parent_idx & 1) + 1; } else if (!strncmp(name, "pll", 3)) { - void __iomem *enable_reg = cpg->reg; + void __iomem *enable_reg = base; u32 enable_bit = name[3] - '0'; parent_name = "main"; @@ -108,7 +107,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, default: return ERR_PTR(-EINVAL); } - if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { + if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; /* handle CFG bit for PLL1 and PLL2 */ if (enable_bit == 1 || enable_bit == 2) @@ -117,7 +116,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, } } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { u32 phy_no = name[3] - '0'; - void __iomem *dsi_reg = cpg->reg + + void __iomem *dsi_reg = base + (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); parent_name = phy_no ? "dsi1pck" : "dsi0pck"; @@ -154,7 +153,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, - cpg->reg + reg, shift, width, 0, + base + reg, shift, width, 0, table, &cpg->lock); } } @@ -162,6 +161,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, static void __init sh73a0_cpg_clocks_init(struct device_node *np) { struct sh73a0_cpg *cpg; + void __iomem *base; struct clk **clks; unsigned int i; int num_clks; @@ -186,14 +186,14 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) + base = of_iomap(np, 0); + if (WARN_ON(base == NULL)) return; /* Set SDHI clocks to a known state */ - writel(0x108, cpg->reg + CPG_SD0CKCR); - writel(0x108, cpg->reg + CPG_SD1CKCR); - writel(0x108, cpg->reg + CPG_SD2CKCR); + writel(0x108, base + CPG_SD0CKCR); + writel(0x108, base + CPG_SD1CKCR); + writel(0x108, base + CPG_SD2CKCR); for (i = 0; i < num_clks; ++i) { const char *name; @@ -202,7 +202,7 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = sh73a0_cpg_register_clock(np, cpg, name); + clk = sh73a0_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); From 1cfeec24273874ffdc5459ef2f138ab61b7207a7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:13 +0200 Subject: [PATCH 13/93] clk: renesas: r8a7778: Remove struct r8a7778_cpg All but the data member of the r8a7778_cpg structure are unused, so the whole structure can be replaced by the single member used. Remove the mapping of the CPG registers, as no code uses the mapped registers. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/4123c1c40a901195f00a825d434553d2052829aa.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7778.c | 31 +++++++++---------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7778.c b/drivers/clk/renesas/clk-r8a7778.c index 3ccc53685bdd..797556259370 100644 --- a/drivers/clk/renesas/clk-r8a7778.c +++ b/drivers/clk/renesas/clk-r8a7778.c @@ -11,12 +11,6 @@ #include #include -struct r8a7778_cpg { - struct clk_onecell_data data; - spinlock_t lock; - void __iomem *reg; -}; - /* PLL multipliers per bits 11, 12, and 18 of MODEMR */ static const struct { unsigned long plla_mult; @@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata; static u32 cpg_mode_divs __initdata; static struct clk * __init -r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, - const char *name) +r8a7778_cpg_register_clock(struct device_node *np, const char *name) { if (!strcmp(name, "plla")) { return clk_register_fixed_factor(NULL, "plla", @@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, static void __init r8a7778_cpg_clocks_init(struct device_node *np) { - struct r8a7778_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; unsigned int i; int num_clks; @@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) return; } - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); - if (cpg == NULL || clks == NULL) { + if (data == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } - spin_lock_init(&cpg->lock); - - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; - - cpg->reg = of_iomap(np, 0); - if (WARN_ON(cpg->reg == NULL)) - return; + data->clks = clks; + data->clk_num = num_clks; for (i = 0; i < num_clks; ++i) { const char *name; @@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7778_cpg_register_clock(np, cpg, name); + clk = r8a7778_cpg_register_clock(np, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From 444877983933d0efaf6788eabf2f750b1c175419 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:14 +0200 Subject: [PATCH 14/93] clk: renesas: r8a7779: Remove struct r8a7779_cpg All but the data member of the r8a7779_cpg structure are unused, so the whole structure can be replaced by the single member used. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/eb94c0f6c54a4f3a7e0e07f12781333a700c0a05.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-r8a7779.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/clk-r8a7779.c b/drivers/clk/renesas/clk-r8a7779.c index 9f3b5522eef5..9a2fea8cf4d7 100644 --- a/drivers/clk/renesas/clk-r8a7779.c +++ b/drivers/clk/renesas/clk-r8a7779.c @@ -21,12 +21,6 @@ #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1) -struct r8a7779_cpg { - struct clk_onecell_data data; - spinlock_t lock; - void __iomem *reg; -}; - /* ----------------------------------------------------------------------------- * CPG Clock Data */ @@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; */ static struct clk * __init -r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, +r8a7779_cpg_register_clock(struct device_node *np, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) { @@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; - struct r8a7779_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; unsigned int i, plla_mult; int num_clks; @@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) return; } - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL); - if (cpg == NULL || clks == NULL) { + if (data == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } - spin_lock_init(&cpg->lock); - - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; + data->clks = clks; + data->clk_num = num_clks; config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)]; plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)]; @@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = r8a7779_cpg_register_clock(np, cpg, config, - plla_mult, name); + clk = r8a7779_cpg_register_clock(np, config, plla_mult, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From 980bcaf33988e201dfd09cd75b20eea691fb3a0e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:41:15 +0200 Subject: [PATCH 15/93] clk: renesas: rza1: Remove struct rz_cpg The register block base pointer as stored in the reg member of the rz_cpg structure is only used during initialization. Hence move it to a local variable, and pass it as a parameter to rz_cpg_register_clock(). After this, the data member is the only remaining member of the rz_cpg structure, so the whole structure can be replaced by the data member. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-rz.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index 7b703f14e20b..e770f09a27ed 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -15,11 +15,6 @@ #include #include -struct rz_cpg { - struct clk_onecell_data data; - void __iomem *reg; -}; - #define CPG_FRQCR 0x10 #define CPG_FRQCR2 0x14 @@ -49,7 +44,8 @@ static u16 __init rz_cpg_read_mode_pins(void) } static struct clk * __init -rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) +rz_cpg_register_clock(struct device_node *np, void __iomem *base, + const char *name) { u32 val; unsigned mult; @@ -65,7 +61,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na } /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */ - if (!cpg->reg) + if (!base) return ERR_PTR(-ENXIO); /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3) @@ -73,9 +69,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na * let them run at fixed current speed and implement the details later. */ if (strcmp(name, "i") == 0) - val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; + val = (readl(base + CPG_FRQCR) >> 8) & 3; else if (strcmp(name, "g") == 0) - val = readl(cpg->reg + CPG_FRQCR2) & 3; + val = readl(base + CPG_FRQCR2) & 3; else return ERR_PTR(-EINVAL); @@ -85,8 +81,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na static void __init rz_cpg_clocks_init(struct device_node *np) { - struct rz_cpg *cpg; + struct clk_onecell_data *data; struct clk **clks; + void __iomem *base; unsigned i; int num_clks; @@ -94,14 +91,14 @@ static void __init rz_cpg_clocks_init(struct device_node *np) if (WARN(num_clks <= 0, "can't count CPG clocks\n")) return; - cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); - BUG_ON(!cpg || !clks); + BUG_ON(!data || !clks); - cpg->data.clks = clks; - cpg->data.clk_num = num_clks; + data->clks = clks; + data->clk_num = num_clks; - cpg->reg = of_iomap(np, 0); + base = of_iomap(np, 0); for (i = 0; i < num_clks; ++i) { const char *name; @@ -109,15 +106,15 @@ static void __init rz_cpg_clocks_init(struct device_node *np) of_property_read_string_index(np, "clock-output-names", i, &name); - clk = rz_cpg_register_clock(np, cpg, name); + clk = rz_cpg_register_clock(np, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else - cpg->data.clks[i] = clk; + data->clks[i] = clk; } - of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); + of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } From fc9e01676cc4eae0a66a8b5ee60cda68537718b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:48:34 +0200 Subject: [PATCH 16/93] dt-bindings: clock: renesas,rzg2l: Simplify header file references The bindings already uses to refer to the header files with DT binding definitions for core clocks. Use more wildcards to simplify more references to these files. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/f274ad16010798dd4a45d2dca5f870da8acbb470.1654696009.git.geert+renesas@glider.be --- .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8880b834f264..d036675e0779 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -45,10 +45,9 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the or - . + a module number, as defined in . const: 2 '#power-domain-cells': @@ -62,7 +61,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the or . + . const: 1 required: From 18d6d8fe4f24938985844d52c481b86fcce9d102 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Thu, 9 Jun 2022 21:28:56 +0800 Subject: [PATCH 17/93] clk: imx93: use adc_root as the parent clock of adc1 When debug, find after system boot up, all adc register operation will trigger system hang, this is because the internal adc ipg clock is gate off. In dts, only reference the IMX93_CLK_ADC1_GATE, which is adc1, no one touch the adc_root, so adc_root will be gate off automatically after system boot up. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Haibo Chen Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index edcc87661d1f..172cd56c9610 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -150,7 +150,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, }, /* M33 critical clk for system run */ { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, - { IMX93_CLK_ADC1_GATE, "adc1", "osc_24m", 0x82c0, }, + { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, }, { IMX93_CLK_WDOG1_GATE, "wdog1", "osc_24m", 0x8300, }, { IMX93_CLK_WDOG2_GATE, "wdog2", "osc_24m", 0x8340, }, { IMX93_CLK_WDOG3_GATE, "wdog3", "osc_24m", 0x8380, }, From 1e3c837a663e9a12c4afabb3279d18cb5110a8f4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Jun 2022 21:28:57 +0800 Subject: [PATCH 18/93] clk: imx93: correct nic_media parent NIC_MEDIA sources from media_axi_root, not media_apb_root. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 172cd56c9610..26885bd3971c 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -219,7 +219,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, - { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, }, + { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, }, { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, }, From ebb4f1eb9360036be5ea70de82c5703ca0e64d43 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 9 Jun 2022 21:28:58 +0800 Subject: [PATCH 19/93] clk: imx93: Correct the edma1's parent clock For EDMA1 in AONMIX, its parent clock should be from cm33_root, so Correct it. Fixes: 24defbe194b65("clk: imx: add i.MX93 clk") Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 26885bd3971c..f5c9fa40491c 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -160,7 +160,7 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, { IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, }, { IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, }, - { IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, }, + { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, }, { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, From 044034efbeea05f65c09d2ba15ceeab53b60e947 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Jun 2022 21:28:59 +0800 Subject: [PATCH 20/93] clk: imx: clk-fracn-gppll: fix mfd value According to spec: A value of 0 is disallowed and should not be programmed in this register Fix to 1. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan Reviewed-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 71c102d950ab..36a53c60e71f 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -64,10 +64,10 @@ struct clk_fracn_gppll { * Fout = Fvco / (rdiv * odiv) */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { - PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3), - PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8), - PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3), - PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3), + PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), + PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), + PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), + PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) }; From 5ebaf9f7da5bb2dc56d394eabfcbe46dc6b1ea8d Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Thu, 9 Jun 2022 21:29:00 +0800 Subject: [PATCH 21/93] clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate() The PLL parameters in rate table should be directly compared with those read from PLL registers instead of the cooked ones. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Cc: Abel Vesa Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Peng Fan Signed-off-by: Liu Ying Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 36a53c60e71f..cb06b0045e9e 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -131,18 +131,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon mfi = FIELD_GET(PLL_MFI_MASK, pll_div); rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); - rdiv = rdiv + 1; odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); - switch (odiv) { - case 0: - odiv = 2; - break; - case 1: - odiv = 3; - break; - default: - break; - } /* * Sometimes, the recalculated rate has deviation due to @@ -160,6 +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon if (rate) return (unsigned long)rate; + rdiv = rdiv + 1; + + switch (odiv) { + case 0: + odiv = 2; + break; + case 1: + odiv = 3; + break; + default: + break; + } + /* Fvco = Fref * (MFI + MFN / MFD) */ fvco = fvco * mfi * mfd + fvco * mfn; do_div(fvco, mfd * rdiv * odiv); From f300cb7fccf69ba1835b983c76d70deb818ad194 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Jun 2022 21:29:01 +0800 Subject: [PATCH 22/93] clk: imx: clk-fracn-gppll: correct rdiv According to Reference Manual: 000b - Divide by 1 001b - Divide by 1 010b - Divide by 2 011b - Divide by 3 100b - Divide by 4 101b - Divide by 5 110b - Divide by 6 111b - Divide by 7 So only need increase rdiv by 1 when the register value is 0. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan Reviewed-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-7-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index cb06b0045e9e..025b73229cdd 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -149,7 +149,8 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon if (rate) return (unsigned long)rate; - rdiv = rdiv + 1; + if (!rdiv) + rdiv = rdiv + 1; switch (odiv) { case 0: From c196175acdd3ab06114bde2955971bc7282f2b85 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Jun 2022 21:29:02 +0800 Subject: [PATCH 23/93] clk: imx: clk-fracn-gppll: Add more freq config for video pll Add the [484,498,445.3]MHz frequency support that will be used by video subsystem on imx93. Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220609132902.3504651-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 025b73229cdd..a2aaa14fc1ae 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -67,6 +67,9 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), + PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4), + PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), + PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) }; From d5c10876c76f6110a968c4afa065ef09a8630868 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 15:46:32 +0200 Subject: [PATCH 24/93] clk: renesas: r8a779f0: Add Z0 and Z1 clock support Add support for the Z0 and Z1 (Cortex-A55 Sub-System 0 (CPU 0-3) and Sub-System 1 (CPU 4-7)) clocks on R-Car S4-8, based on the existing support for Z clocks on R-Car Gen4. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/43009e25be1223a717e00c392cb2d416f5d47032.1654695893.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index e6f41b9f765a..ac0383c38aee 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -77,6 +77,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), /* Core Clock Outputs */ + DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), + DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8), DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), From b7f64eaee5a345fe0c454f939252b46a26b47434 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 13 Jun 2022 20:56:27 +0900 Subject: [PATCH 25/93] clk: renesas: r8a779f0: Add PCIe clocks Add the module clocks used by the PCIe controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220613115627.2831257-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index ac0383c38aee..4610d6bd8b3b 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -126,6 +126,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), + DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2), + DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2), DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), From 080bcd8d5997b1a615e17cab02bd9d16d1d4fbf3 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 14 Jun 2022 11:49:37 +0200 Subject: [PATCH 26/93] clk: renesas: r8a779f0: Add HSCIF clocks Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220614094937.8104-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 4610d6bd8b3b..cd80b6084ece 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -120,6 +120,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { + DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3), + DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3), + DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3), + DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3), DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), From 29f66b625281a3026653fd33b710771a4ae394d2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 17 May 2022 12:09:49 -0700 Subject: [PATCH 27/93] clk: qcom: rpmh: Add note about sleep/wake state for BCMs The sleep/wake state doesn't need to be set here because of specific RPMh behavior that carries over the active state when sleep/wake state hasn't been modified. Add a note to the code so we aren't tempted to set the sleep/wake states. Cc: Alex Elder Cc: Taniya Das Signed-off-by: Stephen Boyd Reviewed-by: Alex Elder Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220517190949.2922197-1-swboyd@chromium.org --- drivers/clk/qcom/clk-rpmh.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index aed907982344..c07cab6905cb 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -274,6 +274,11 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) cmd.addr = c->res_addr; cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); + /* + * Send only an active only state request. RPMh continues to + * use the active state when we're in sleep/wake state as long + * as the sleep/wake state has never been set. + */ ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); if (ret) { dev_err(c->dev, "set active state of %s failed: (%d)\n", From a7a4fc9498f55f3e91f89a19f74e2016c3e7f62f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 17 Jun 2022 15:29:19 +0300 Subject: [PATCH 28/93] clk: qcom: mmcc-msm8996: use ARRAY_SIZE instead of specifying num_parents Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220617122922.769562-4-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/mmcc-msm8996.c | 88 ++++++++++++++++----------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 24843e4f2599..bf0f8eb78989 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -486,7 +486,7 @@ static struct clk_rcg2 ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ahb_clk_src", .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -510,7 +510,7 @@ static struct clk_rcg2 axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "axi_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -523,7 +523,7 @@ static struct clk_rcg2 maxi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "maxi_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -536,7 +536,7 @@ static struct clk_rcg2_gfx3d gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0), .ops = &clk_gfx3d_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -561,7 +561,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbbmtimer_clk_src", .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -573,7 +573,7 @@ static struct clk_rcg2 isense_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "isense_clk_src", .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -592,7 +592,7 @@ static struct clk_rcg2 rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbcpr_clk_src", .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -614,7 +614,7 @@ static struct clk_rcg2 video_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_core_clk_src", .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -628,7 +628,7 @@ static struct clk_rcg2 video_subcore0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_subcore0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -642,7 +642,7 @@ static struct clk_rcg2 video_subcore1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_subcore1_clk_src", .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmss_xo_dsi0pll_dsi1pll, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -669,7 +669,7 @@ static struct clk_rcg2 pclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmss_xo_dsi0pll_dsi1pll, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -696,7 +696,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -714,7 +714,7 @@ static struct clk_rcg2 extpclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", .parent_names = mmss_xo_hdmi, - .num_parents = 2, + .num_parents = ARRAY_SIZE(mmss_xo_hdmi), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -733,7 +733,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = mmss_xo_gpll0_gpll0_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -751,7 +751,7 @@ static struct clk_rcg2 hdmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", .parent_names = mmss_xo_gpll0_gpll0_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -763,7 +763,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = mmss_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -776,7 +776,7 @@ static struct clk_rcg2 byte1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_names = mmss_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -795,7 +795,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = mmss_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_rcg2_ops, }, }; @@ -808,7 +808,7 @@ static struct clk_rcg2 esc1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", .parent_names = mmss_xo_dsibyte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_rcg2_ops, }, }; @@ -832,7 +832,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -846,7 +846,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -874,7 +874,7 @@ static struct clk_rcg2 mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -888,7 +888,7 @@ static struct clk_rcg2 mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -902,7 +902,7 @@ static struct clk_rcg2 mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -916,7 +916,7 @@ static struct clk_rcg2 mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -938,7 +938,7 @@ static struct clk_rcg2 cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -958,7 +958,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -971,7 +971,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -984,7 +984,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1005,7 +1005,7 @@ static struct clk_rcg2 csiphy0_3p_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy0_3p_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1018,7 +1018,7 @@ static struct clk_rcg2 csiphy1_3p_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy1_3p_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1031,7 +1031,7 @@ static struct clk_rcg2 csiphy2_3p_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy2_3p_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1054,7 +1054,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1089,7 +1089,7 @@ static struct clk_rcg2 jpeg_dma_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg_dma_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1112,7 +1112,7 @@ static struct clk_rcg2 vfe0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1125,7 +1125,7 @@ static struct clk_rcg2 vfe1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1147,7 +1147,7 @@ static struct clk_rcg2 cpp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1169,7 +1169,7 @@ static struct clk_rcg2 csi0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1182,7 +1182,7 @@ static struct clk_rcg2 csi1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1195,7 +1195,7 @@ static struct clk_rcg2 csi2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1208,7 +1208,7 @@ static struct clk_rcg2 csi3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; @@ -1228,7 +1228,7 @@ static struct clk_rcg2 fd_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "fd_core_clk_src", .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, }; From 208c564fe66e2f76abb29468d067223eb50b3005 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 17 Jun 2022 15:29:20 +0300 Subject: [PATCH 29/93] clk: qcom: mmcc-msm8996: move clock parent tables down Move clock parent tables down, after the MMPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220617122922.769562-5-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/mmcc-msm8996.c | 364 ++++++++++++++++---------------- 1 file changed, 182 insertions(+), 182 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index bf0f8eb78989..27c92818c49c 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -45,188 +45,6 @@ enum { P_MMPLL4, }; -static const struct parent_map mmss_xo_hdmi_map[] = { - { P_XO, 0 }, - { P_HDMIPLL, 1 } -}; - -static const char * const mmss_xo_hdmi[] = { - "xo", - "hdmipll" -}; - -static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { - { P_XO, 0 }, - { P_DSI0PLL, 1 }, - { P_DSI1PLL, 2 } -}; - -static const char * const mmss_xo_dsi0pll_dsi1pll[] = { - "xo", - "dsi0pll", - "dsi1pll" -}; - -static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_gpll0_gpll0_div[] = { - "xo", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_dsibyte_map[] = { - { P_XO, 0 }, - { P_DSI0PLL_BYTE, 1 }, - { P_DSI1PLL_BYTE, 2 } -}; - -static const char * const mmss_xo_dsibyte[] = { - "xo", - "dsi0pllbyte", - "dsi1pllbyte" -}; - -static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL1, 2 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll1", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL3, 3 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll3", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL5, 2 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll5", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL4, 3 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll4", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL9, 2 }, - { P_MMPLL2, 3 }, - { P_MMPLL8, 4 }, - { P_GPLL0, 5 } -}; - -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { - "xo", - "mmpll0", - "mmpll9", - "mmpll2", - "mmpll8", - "gpll0" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL9, 2 }, - { P_MMPLL2, 3 }, - { P_MMPLL8, 4 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll9", - "mmpll2", - "mmpll8", - "gpll0", - "gpll0_div" -}; - -static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { - { P_XO, 0 }, - { P_MMPLL0, 1 }, - { P_MMPLL1, 2 }, - { P_MMPLL4, 3 }, - { P_MMPLL3, 4 }, - { P_GPLL0, 5 }, - { P_GPLL0_DIV, 6 } -}; - -static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll1", - "mmpll4", - "mmpll3", - "gpll0", - "gpll0_div" -}; - static struct clk_fixed_factor gpll0_div = { .mult = 1, .div = 2, @@ -471,6 +289,188 @@ static struct clk_alpha_pll_postdiv mmpll9 = { }, }; +static const struct parent_map mmss_xo_hdmi_map[] = { + { P_XO, 0 }, + { P_HDMIPLL, 1 } +}; + +static const char * const mmss_xo_hdmi[] = { + "xo", + "hdmipll" +}; + +static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { + { P_XO, 0 }, + { P_DSI0PLL, 1 }, + { P_DSI1PLL, 2 } +}; + +static const char * const mmss_xo_dsi0pll_dsi1pll[] = { + "xo", + "dsi0pll", + "dsi1pll" +}; + +static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_gpll0_gpll0_div[] = { + "xo", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_dsibyte_map[] = { + { P_XO, 0 }, + { P_DSI0PLL_BYTE, 1 }, + { P_DSI1PLL_BYTE, 2 } +}; + +static const char * const mmss_xo_dsibyte[] = { + "xo", + "dsi0pllbyte", + "dsi1pllbyte" +}; + +static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll1", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL3, 3 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll3", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL5, 2 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll5", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL4, 3 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll4", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL9, 2 }, + { P_MMPLL2, 3 }, + { P_MMPLL8, 4 }, + { P_GPLL0, 5 } +}; + +static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { + "xo", + "mmpll0", + "mmpll9", + "mmpll2", + "mmpll8", + "gpll0" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL9, 2 }, + { P_MMPLL2, 3 }, + { P_MMPLL8, 4 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll9", + "mmpll2", + "mmpll8", + "gpll0", + "gpll0_div" +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { + { P_XO, 0 }, + { P_MMPLL0, 1 }, + { P_MMPLL1, 2 }, + { P_MMPLL4, 3 }, + { P_MMPLL3, 4 }, + { P_GPLL0, 5 }, + { P_GPLL0_DIV, 6 } +}; + +static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { + "xo", + "mmpll0", + "mmpll1", + "mmpll4", + "mmpll3", + "gpll0", + "gpll0_div" +}; + static const struct freq_tbl ftbl_ahb_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(40000000, P_GPLL0_DIV, 7.5, 0, 0), From e7c659124c9a031c48e2fecf72c849cb63f9497b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 17 Jun 2022 15:29:21 +0300 Subject: [PATCH 30/93] clk: qcom: mmcc-msm8996: use parent_hws/_data instead of parent_names Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220617122922.769562-6-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/mmcc-msm8996.c | 734 +++++++++++++++++++++----------- 1 file changed, 495 insertions(+), 239 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 27c92818c49c..80330dab4d81 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -50,7 +50,9 @@ static struct clk_fixed_factor gpll0_div = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_div", - .parent_names = (const char *[]){ "gpll0" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gpll0", .name = "gpll0" }, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -83,7 +85,9 @@ static struct clk_alpha_pll mmpll0_early = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmpll0_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -96,7 +100,9 @@ static struct clk_alpha_pll_postdiv mmpll0 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", - .parent_names = (const char *[]){ "mmpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll0_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -113,7 +119,9 @@ static struct clk_alpha_pll mmpll1_early = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "mmpll1_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, } @@ -126,7 +134,9 @@ static struct clk_alpha_pll_postdiv mmpll1 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", - .parent_names = (const char *[]){ "mmpll1_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll1_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -140,7 +150,9 @@ static struct clk_alpha_pll mmpll2_early = { .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll2_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -152,7 +164,9 @@ static struct clk_alpha_pll_postdiv mmpll2 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll2", - .parent_names = (const char *[]){ "mmpll2_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll2_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -166,7 +180,9 @@ static struct clk_alpha_pll mmpll3_early = { .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -178,7 +194,9 @@ static struct clk_alpha_pll_postdiv mmpll3 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", - .parent_names = (const char *[]){ "mmpll3_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll3_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -192,7 +210,9 @@ static struct clk_alpha_pll mmpll4_early = { .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll4_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -204,7 +224,9 @@ static struct clk_alpha_pll_postdiv mmpll4 = { .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll4", - .parent_names = (const char *[]){ "mmpll4_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll4_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -218,7 +240,9 @@ static struct clk_alpha_pll mmpll5_early = { .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll5_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -230,7 +254,9 @@ static struct clk_alpha_pll_postdiv mmpll5 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll5", - .parent_names = (const char *[]){ "mmpll5_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll5_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -244,7 +270,9 @@ static struct clk_alpha_pll mmpll8_early = { .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll8_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -256,7 +284,9 @@ static struct clk_alpha_pll_postdiv mmpll8 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll8", - .parent_names = (const char *[]){ "mmpll8_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll8_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -270,7 +300,9 @@ static struct clk_alpha_pll mmpll9_early = { .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll9_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -282,7 +314,9 @@ static struct clk_alpha_pll_postdiv mmpll9 = { .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll9", - .parent_names = (const char *[]){ "mmpll9_early" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll9_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, .flags = CLK_SET_RATE_PARENT, @@ -294,9 +328,9 @@ static const struct parent_map mmss_xo_hdmi_map[] = { { P_HDMIPLL, 1 } }; -static const char * const mmss_xo_hdmi[] = { - "xo", - "hdmipll" +static const struct clk_parent_data mmss_xo_hdmi[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "hdmipll", .name = "hdmipll" } }; static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { @@ -305,10 +339,10 @@ static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { { P_DSI1PLL, 2 } }; -static const char * const mmss_xo_dsi0pll_dsi1pll[] = { - "xo", - "dsi0pll", - "dsi1pll" +static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, + { .fw_name = "dsi1pll", .name = "dsi1pll" } }; static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { @@ -317,10 +351,10 @@ static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_gpll0_gpll0_div[] = { - "xo", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_dsibyte_map[] = { @@ -329,10 +363,10 @@ static const struct parent_map mmss_xo_dsibyte_map[] = { { P_DSI1PLL_BYTE, 2 } }; -static const char * const mmss_xo_dsibyte[] = { - "xo", - "dsi0pllbyte", - "dsi1pllbyte" +static const struct clk_parent_data mmss_xo_dsibyte[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, + { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" } }; static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { @@ -342,11 +376,11 @@ static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { @@ -357,12 +391,12 @@ static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll1", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll1.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { @@ -373,12 +407,12 @@ static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll3", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll3.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { @@ -389,12 +423,12 @@ static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll5", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll5.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { @@ -405,12 +439,12 @@ static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = { { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll4", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll4.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { @@ -422,13 +456,13 @@ static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = { P_GPLL0, 5 } }; -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { - "xo", - "mmpll0", - "mmpll9", - "mmpll2", - "mmpll8", - "gpll0" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll9.clkr.hw }, + { .hw = &mmpll2.clkr.hw }, + { .hw = &mmpll8.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, }; static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = { @@ -441,14 +475,14 @@ static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_d { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll9", - "mmpll2", - "mmpll8", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll9.clkr.hw }, + { .hw = &mmpll2.clkr.hw }, + { .hw = &mmpll8.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = { @@ -461,14 +495,14 @@ static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_d { P_GPLL0_DIV, 6 } }; -static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { - "xo", - "mmpll0", - "mmpll1", - "mmpll4", - "mmpll3", - "gpll0", - "gpll0_div" +static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0.clkr.hw }, + { .hw = &mmpll1.clkr.hw }, + { .hw = &mmpll4.clkr.hw }, + { .hw = &mmpll3.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw } }; static const struct freq_tbl ftbl_ahb_clk_src[] = { @@ -485,7 +519,7 @@ static struct clk_rcg2 ahb_clk_src = { .freq_tbl = ftbl_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ahb_clk_src", - .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -509,7 +543,7 @@ static struct clk_rcg2 axi_clk_src = { .freq_tbl = ftbl_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "axi_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -522,7 +556,7 @@ static struct clk_rcg2 maxi_clk_src = { .freq_tbl = ftbl_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "maxi_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -535,7 +569,7 @@ static struct clk_rcg2_gfx3d gfx3d_clk_src = { .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, + .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0), .ops = &clk_gfx3d_ops, .flags = CLK_SET_RATE_PARENT, @@ -560,7 +594,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = { .freq_tbl = ftbl_rbbmtimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "rbbmtimer_clk_src", - .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -572,7 +606,7 @@ static struct clk_rcg2 isense_clk_src = { .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, .clkr.hw.init = &(struct clk_init_data){ .name = "isense_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -591,7 +625,7 @@ static struct clk_rcg2 rbcpr_clk_src = { .freq_tbl = ftbl_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "rbcpr_clk_src", - .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -613,7 +647,7 @@ static struct clk_rcg2 video_core_clk_src = { .freq_tbl = ftbl_video_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "video_core_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -627,7 +661,7 @@ static struct clk_rcg2 video_subcore0_clk_src = { .freq_tbl = ftbl_video_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "video_subcore0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -641,7 +675,7 @@ static struct clk_rcg2 video_subcore1_clk_src = { .freq_tbl = ftbl_video_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "video_subcore1_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -654,7 +688,7 @@ static struct clk_rcg2 pclk0_clk_src = { .parent_map = mmss_xo_dsi0pll_dsi1pll_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", - .parent_names = mmss_xo_dsi0pll_dsi1pll, + .parent_data = mmss_xo_dsi0pll_dsi1pll, .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, @@ -668,7 +702,7 @@ static struct clk_rcg2 pclk1_clk_src = { .parent_map = mmss_xo_dsi0pll_dsi1pll_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", - .parent_names = mmss_xo_dsi0pll_dsi1pll, + .parent_data = mmss_xo_dsi0pll_dsi1pll, .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, @@ -695,7 +729,7 @@ static struct clk_rcg2 mdp_clk_src = { .freq_tbl = ftbl_mdp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -713,7 +747,7 @@ static struct clk_rcg2 extpclk_clk_src = { .freq_tbl = extpclk_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", - .parent_names = mmss_xo_hdmi, + .parent_data = mmss_xo_hdmi, .num_parents = ARRAY_SIZE(mmss_xo_hdmi), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, @@ -732,7 +766,7 @@ static struct clk_rcg2 vsync_clk_src = { .freq_tbl = ftbl_mdss_vsync_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", - .parent_names = mmss_xo_gpll0_gpll0_div, + .parent_data = mmss_xo_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -750,7 +784,7 @@ static struct clk_rcg2 hdmi_clk_src = { .freq_tbl = ftbl_mdss_hdmi_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", - .parent_names = mmss_xo_gpll0_gpll0_div, + .parent_data = mmss_xo_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -762,7 +796,7 @@ static struct clk_rcg2 byte0_clk_src = { .parent_map = mmss_xo_dsibyte_map, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", - .parent_names = mmss_xo_dsibyte, + .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, @@ -775,7 +809,7 @@ static struct clk_rcg2 byte1_clk_src = { .parent_map = mmss_xo_dsibyte_map, .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", - .parent_names = mmss_xo_dsibyte, + .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, @@ -794,7 +828,7 @@ static struct clk_rcg2 esc0_clk_src = { .freq_tbl = ftbl_mdss_esc0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", - .parent_names = mmss_xo_dsibyte, + .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_rcg2_ops, }, @@ -807,7 +841,7 @@ static struct clk_rcg2 esc1_clk_src = { .freq_tbl = ftbl_mdss_esc0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", - .parent_names = mmss_xo_dsibyte, + .parent_data = mmss_xo_dsibyte, .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), .ops = &clk_rcg2_ops, }, @@ -831,7 +865,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .freq_tbl = ftbl_camss_gp0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -845,7 +879,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .freq_tbl = ftbl_camss_gp0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -873,7 +907,7 @@ static struct clk_rcg2 mclk0_clk_src = { .freq_tbl = ftbl_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -887,7 +921,7 @@ static struct clk_rcg2 mclk1_clk_src = { .freq_tbl = ftbl_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -901,7 +935,7 @@ static struct clk_rcg2 mclk2_clk_src = { .freq_tbl = ftbl_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -915,7 +949,7 @@ static struct clk_rcg2 mclk3_clk_src = { .freq_tbl = ftbl_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -937,7 +971,7 @@ static struct clk_rcg2 cci_clk_src = { .freq_tbl = ftbl_cci_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -957,7 +991,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .freq_tbl = ftbl_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -970,7 +1004,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .freq_tbl = ftbl_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -983,7 +1017,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .freq_tbl = ftbl_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1004,7 +1038,7 @@ static struct clk_rcg2 csiphy0_3p_clk_src = { .freq_tbl = ftbl_csiphy0_3p_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy0_3p_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1017,7 +1051,7 @@ static struct clk_rcg2 csiphy1_3p_clk_src = { .freq_tbl = ftbl_csiphy0_3p_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy1_3p_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1030,7 +1064,7 @@ static struct clk_rcg2 csiphy2_3p_clk_src = { .freq_tbl = ftbl_csiphy0_3p_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csiphy2_3p_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1053,7 +1087,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .freq_tbl = ftbl_jpeg0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1075,7 +1109,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .freq_tbl = ftbl_jpeg2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1088,7 +1122,7 @@ static struct clk_rcg2 jpeg_dma_clk_src = { .freq_tbl = ftbl_jpeg0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg_dma_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1111,7 +1145,7 @@ static struct clk_rcg2 vfe0_clk_src = { .freq_tbl = ftbl_vfe0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1124,7 +1158,7 @@ static struct clk_rcg2 vfe1_clk_src = { .freq_tbl = ftbl_vfe0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1146,7 +1180,7 @@ static struct clk_rcg2 cpp_clk_src = { .freq_tbl = ftbl_cpp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1168,7 +1202,7 @@ static struct clk_rcg2 csi0_clk_src = { .freq_tbl = ftbl_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1181,7 +1215,7 @@ static struct clk_rcg2 csi1_clk_src = { .freq_tbl = ftbl_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1194,7 +1228,7 @@ static struct clk_rcg2 csi2_clk_src = { .freq_tbl = ftbl_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1207,7 +1241,7 @@ static struct clk_rcg2 csi3_clk_src = { .freq_tbl = ftbl_csi0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1227,7 +1261,7 @@ static struct clk_rcg2 fd_core_clk_src = { .freq_tbl = ftbl_fd_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "fd_core_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, + .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div), .ops = &clk_rcg2_ops, }, @@ -1240,7 +1274,9 @@ static struct clk_branch mmss_mmagic_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmagic_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1255,7 +1291,9 @@ static struct clk_branch mmss_mmagic_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmagic_cfg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1270,7 +1308,9 @@ static struct clk_branch mmss_misc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_misc_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1285,7 +1325,9 @@ static struct clk_branch mmss_misc_cxo_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_misc_cxo_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -1299,7 +1341,9 @@ static struct clk_branch mmss_mmagic_maxi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmagic_maxi_clk", - .parent_names = (const char *[]){ "maxi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &maxi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1314,7 +1358,9 @@ static struct clk_branch mmagic_camss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_camss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1329,7 +1375,9 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_camss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1344,7 +1392,9 @@ static struct clk_branch smmu_vfe_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_vfe_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1359,7 +1409,9 @@ static struct clk_branch smmu_vfe_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_vfe_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1374,7 +1426,9 @@ static struct clk_branch smmu_cpp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_cpp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1389,7 +1443,9 @@ static struct clk_branch smmu_cpp_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_cpp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1404,7 +1460,9 @@ static struct clk_branch smmu_jpeg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_jpeg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1419,7 +1477,9 @@ static struct clk_branch smmu_jpeg_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_jpeg_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1434,7 +1494,9 @@ static struct clk_branch mmagic_mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_mdss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1449,7 +1511,9 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_mdss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1464,7 +1528,9 @@ static struct clk_branch smmu_rot_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_rot_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1479,7 +1545,9 @@ static struct clk_branch smmu_rot_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_rot_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1494,7 +1562,9 @@ static struct clk_branch smmu_mdp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_mdp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1509,7 +1579,9 @@ static struct clk_branch smmu_mdp_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_mdp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1524,7 +1596,9 @@ static struct clk_branch mmagic_video_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1539,7 +1613,9 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_video_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1554,7 +1630,9 @@ static struct clk_branch smmu_video_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_video_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1569,7 +1647,9 @@ static struct clk_branch smmu_video_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1584,7 +1664,9 @@ static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_bimc_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" }, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1599,7 +1681,9 @@ static struct clk_branch gpu_gx_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_gx_gfx3d_clk", - .parent_names = (const char *[]){ "gfx3d_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_clk_src.rcg.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1614,7 +1698,9 @@ static struct clk_branch gpu_gx_rbbmtimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_gx_rbbmtimer_clk", - .parent_names = (const char *[]){ "rbbmtimer_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &rbbmtimer_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1629,7 +1715,9 @@ static struct clk_branch gpu_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1644,7 +1732,9 @@ static struct clk_branch gpu_aon_isense_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_aon_isense_clk", - .parent_names = (const char *[]){ "isense_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &isense_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1659,7 +1749,9 @@ static struct clk_branch vmem_maxi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vmem_maxi_clk", - .parent_names = (const char *[]){ "maxi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &maxi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1674,7 +1766,9 @@ static struct clk_branch vmem_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vmem_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1689,7 +1783,9 @@ static struct clk_branch mmss_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_rbcpr_clk", - .parent_names = (const char *[]){ "rbcpr_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &rbcpr_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1704,7 +1800,9 @@ static struct clk_branch mmss_rbcpr_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_rbcpr_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1719,7 +1817,9 @@ static struct clk_branch video_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_core_clk", - .parent_names = (const char *[]){ "video_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &video_core_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1734,7 +1834,9 @@ static struct clk_branch video_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1749,7 +1851,9 @@ static struct clk_branch video_maxi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_maxi_clk", - .parent_names = (const char *[]){ "maxi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &maxi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1764,7 +1868,9 @@ static struct clk_branch video_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1779,7 +1885,9 @@ static struct clk_branch video_subcore0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_subcore0_clk", - .parent_names = (const char *[]){ "video_subcore0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &video_subcore0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1794,7 +1902,9 @@ static struct clk_branch video_subcore1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_subcore1_clk", - .parent_names = (const char *[]){ "video_subcore1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &video_subcore1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1809,7 +1919,9 @@ static struct clk_branch mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1824,7 +1936,9 @@ static struct clk_branch mdss_hdmi_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_hdmi_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1839,7 +1953,9 @@ static struct clk_branch mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1854,7 +1970,9 @@ static struct clk_branch mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_pclk0_clk", - .parent_names = (const char *[]){ "pclk0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pclk0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1869,7 +1987,9 @@ static struct clk_branch mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_pclk1_clk", - .parent_names = (const char *[]){ "pclk1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pclk1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1884,7 +2004,9 @@ static struct clk_branch mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_mdp_clk", - .parent_names = (const char *[]){ "mdp_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mdp_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1899,7 +2021,9 @@ static struct clk_branch mdss_extpclk_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_extpclk_clk", - .parent_names = (const char *[]){ "extpclk_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &extpclk_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1914,7 +2038,9 @@ static struct clk_branch mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_vsync_clk", - .parent_names = (const char *[]){ "vsync_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vsync_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1929,7 +2055,9 @@ static struct clk_branch mdss_hdmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_hdmi_clk", - .parent_names = (const char *[]){ "hdmi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &hdmi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1944,7 +2072,9 @@ static struct clk_branch mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_byte0_clk", - .parent_names = (const char *[]){ "byte0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &byte0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1959,7 +2089,9 @@ static struct clk_branch mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_byte1_clk", - .parent_names = (const char *[]){ "byte1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &byte1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1974,7 +2106,9 @@ static struct clk_branch mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_esc0_clk", - .parent_names = (const char *[]){ "esc0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &esc0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1989,7 +2123,9 @@ static struct clk_branch mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_esc1_clk", - .parent_names = (const char *[]){ "esc1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &esc1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2004,7 +2140,9 @@ static struct clk_branch camss_top_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_top_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2019,7 +2157,9 @@ static struct clk_branch camss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2034,7 +2174,9 @@ static struct clk_branch camss_micro_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_micro_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2049,7 +2191,9 @@ static struct clk_branch camss_gp0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk", - .parent_names = (const char *[]){ "camss_gp0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &camss_gp0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2064,7 +2208,9 @@ static struct clk_branch camss_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk", - .parent_names = (const char *[]){ "camss_gp1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &camss_gp1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2079,7 +2225,9 @@ static struct clk_branch camss_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk0_clk", - .parent_names = (const char *[]){ "mclk0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mclk0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2094,7 +2242,9 @@ static struct clk_branch camss_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk1_clk", - .parent_names = (const char *[]){ "mclk1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mclk1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2109,7 +2259,9 @@ static struct clk_branch camss_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk2_clk", - .parent_names = (const char *[]){ "mclk2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mclk2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2124,7 +2276,9 @@ static struct clk_branch camss_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk3_clk", - .parent_names = (const char *[]){ "mclk3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mclk3_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2139,7 +2293,9 @@ static struct clk_branch camss_cci_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cci_clk", - .parent_names = (const char *[]){ "cci_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &cci_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2154,7 +2310,9 @@ static struct clk_branch camss_cci_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cci_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2169,7 +2327,9 @@ static struct clk_branch camss_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0phytimer_clk", - .parent_names = (const char *[]){ "csi0phytimer_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0phytimer_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2184,7 +2344,9 @@ static struct clk_branch camss_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1phytimer_clk", - .parent_names = (const char *[]){ "csi1phytimer_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1phytimer_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2199,7 +2361,9 @@ static struct clk_branch camss_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2phytimer_clk", - .parent_names = (const char *[]){ "csi2phytimer_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2phytimer_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2214,7 +2378,9 @@ static struct clk_branch camss_csiphy0_3p_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csiphy0_3p_clk", - .parent_names = (const char *[]){ "csiphy0_3p_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csiphy0_3p_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2229,7 +2395,9 @@ static struct clk_branch camss_csiphy1_3p_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csiphy1_3p_clk", - .parent_names = (const char *[]){ "csiphy1_3p_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csiphy1_3p_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2244,7 +2412,9 @@ static struct clk_branch camss_csiphy2_3p_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csiphy2_3p_clk", - .parent_names = (const char *[]){ "csiphy2_3p_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csiphy2_3p_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2259,7 +2429,9 @@ static struct clk_branch camss_jpeg0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg0_clk", - .parent_names = (const char *[]){ "jpeg0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &jpeg0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2274,7 +2446,9 @@ static struct clk_branch camss_jpeg2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg2_clk", - .parent_names = (const char *[]){ "jpeg2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &jpeg2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2289,7 +2463,9 @@ static struct clk_branch camss_jpeg_dma_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_dma_clk", - .parent_names = (const char *[]){ "jpeg_dma_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &jpeg_dma_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2304,7 +2480,9 @@ static struct clk_branch camss_jpeg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2319,7 +2497,9 @@ static struct clk_branch camss_jpeg_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2334,7 +2514,9 @@ static struct clk_branch camss_vfe_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2349,7 +2531,9 @@ static struct clk_branch camss_vfe_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2364,7 +2548,9 @@ static struct clk_branch camss_vfe0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe0_clk", - .parent_names = (const char *[]){ "vfe0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2379,7 +2565,9 @@ static struct clk_branch camss_vfe0_stream_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe0_stream_clk", - .parent_names = (const char *[]){ "vfe0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2394,7 +2582,9 @@ static struct clk_branch camss_vfe0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe0_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2409,7 +2599,9 @@ static struct clk_branch camss_vfe1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe1_clk", - .parent_names = (const char *[]){ "vfe1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2424,7 +2616,9 @@ static struct clk_branch camss_vfe1_stream_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe1_stream_clk", - .parent_names = (const char *[]){ "vfe1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2439,7 +2633,9 @@ static struct clk_branch camss_vfe1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe1_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2454,7 +2650,9 @@ static struct clk_branch camss_csi_vfe0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi_vfe0_clk", - .parent_names = (const char *[]){ "vfe0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2469,7 +2667,9 @@ static struct clk_branch camss_csi_vfe1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi_vfe1_clk", - .parent_names = (const char *[]){ "vfe1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2484,7 +2684,9 @@ static struct clk_branch camss_cpp_vbif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_vbif_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2499,7 +2701,9 @@ static struct clk_branch camss_cpp_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &axi_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2514,7 +2718,9 @@ static struct clk_branch camss_cpp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_clk", - .parent_names = (const char *[]){ "cpp_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &cpp_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2529,7 +2735,9 @@ static struct clk_branch camss_cpp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2544,7 +2752,9 @@ static struct clk_branch camss_csi0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0_clk", - .parent_names = (const char *[]){ "csi0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2559,7 +2769,9 @@ static struct clk_branch camss_csi0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2574,7 +2786,9 @@ static struct clk_branch camss_csi0phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0phy_clk", - .parent_names = (const char *[]){ "csi0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2589,7 +2803,9 @@ static struct clk_branch camss_csi0rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0rdi_clk", - .parent_names = (const char *[]){ "csi0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2604,7 +2820,9 @@ static struct clk_branch camss_csi0pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0pix_clk", - .parent_names = (const char *[]){ "csi0_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2619,7 +2837,9 @@ static struct clk_branch camss_csi1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1_clk", - .parent_names = (const char *[]){ "csi1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2634,7 +2854,9 @@ static struct clk_branch camss_csi1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2649,7 +2871,9 @@ static struct clk_branch camss_csi1phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1phy_clk", - .parent_names = (const char *[]){ "csi1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2664,7 +2888,9 @@ static struct clk_branch camss_csi1rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1rdi_clk", - .parent_names = (const char *[]){ "csi1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2679,7 +2905,9 @@ static struct clk_branch camss_csi1pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1pix_clk", - .parent_names = (const char *[]){ "csi1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2694,7 +2922,9 @@ static struct clk_branch camss_csi2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2_clk", - .parent_names = (const char *[]){ "csi2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2709,7 +2939,9 @@ static struct clk_branch camss_csi2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2724,7 +2956,9 @@ static struct clk_branch camss_csi2phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2phy_clk", - .parent_names = (const char *[]){ "csi2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2739,7 +2973,9 @@ static struct clk_branch camss_csi2rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2rdi_clk", - .parent_names = (const char *[]){ "csi2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2754,7 +2990,9 @@ static struct clk_branch camss_csi2pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2pix_clk", - .parent_names = (const char *[]){ "csi2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2769,7 +3007,9 @@ static struct clk_branch camss_csi3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3_clk", - .parent_names = (const char *[]){ "csi3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2784,7 +3024,9 @@ static struct clk_branch camss_csi3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2799,7 +3041,9 @@ static struct clk_branch camss_csi3phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3phy_clk", - .parent_names = (const char *[]){ "csi3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2814,7 +3058,9 @@ static struct clk_branch camss_csi3rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3rdi_clk", - .parent_names = (const char *[]){ "csi3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2829,7 +3075,9 @@ static struct clk_branch camss_csi3pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3pix_clk", - .parent_names = (const char *[]){ "csi3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2844,7 +3092,9 @@ static struct clk_branch camss_ispif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_ispif_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2859,7 +3109,9 @@ static struct clk_branch fd_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "fd_core_clk", - .parent_names = (const char *[]){ "fd_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &fd_core_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2874,7 +3126,9 @@ static struct clk_branch fd_core_uar_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "fd_core_uar_clk", - .parent_names = (const char *[]){ "fd_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &fd_core_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2889,7 +3143,9 @@ static struct clk_branch fd_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "fd_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ahb_clk_src.clkr.hw + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, From 74e4190cdebe5a4aa099185edb4db418fc9883e3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 8 Jun 2022 13:52:34 +0300 Subject: [PATCH 31/93] clk: qcom: regmap: add PHY clock source implementation On recent Qualcomm platforms the QMP PIPE clocks feed into a set of muxes which must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom endpoint, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. Supplement the regmap-mux with the new clk_regmap_phy_mux type, which implements such multiplexers as a simple gate clocks. This is possible since each of these multiplexers has just two clock sources: one coming from the PHY and a reference (XO) one. If the clock is running off the from-PHY source, report it as enabled. Report it as disabled otherwise (if it uses reference source). This way the PHY will disable the pipe clock before turning off the GDSC, which in turn would lead to disabling corresponding pipe_clk_src (and thus it being parked to a safe, reference clock source). And vice versa, after enabling the GDSC the PHY will enable the pipe clock, which would cause pipe_clk_src to be switched from a safe source to the working one. Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reported-by: kernel test robot Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-regmap-phy-mux.c | 62 +++++++++++++++++++++++++++ drivers/clk/qcom/clk-regmap-phy-mux.h | 33 ++++++++++++++ 3 files changed, 96 insertions(+) create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 36789f5233ef..08594230c1c1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o clk-qcom-y += clk-regmap-mux-div.o +clk-qcom-y += clk-regmap-phy-mux.o clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o clk-qcom-y += clk-hfpll.o clk-qcom-y += reset.o diff --git a/drivers/clk/qcom/clk-regmap-phy-mux.c b/drivers/clk/qcom/clk-regmap-phy-mux.c new file mode 100644 index 000000000000..7b7243b7107d --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-phy-mux.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Linaro Ltd. + */ + +#include +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-regmap-phy-mux.h" + +#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr) +{ + return container_of(clkr, struct clk_regmap_phy_mux, clkr); +} + +static int phy_mux_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr); + unsigned int val; + + regmap_read(clkr->regmap, phy_mux->reg, &val); + val = FIELD_GET(PHY_MUX_MASK, val); + + WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC); + + return val == PHY_MUX_PHY_SRC; +} + +static int phy_mux_enable(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr); + + return regmap_update_bits(clkr->regmap, phy_mux->reg, + PHY_MUX_MASK, + FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC)); +} + +static void phy_mux_disable(struct clk_hw *hw) +{ + struct clk_regmap *clkr = to_clk_regmap(hw); + struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr); + + regmap_update_bits(clkr->regmap, phy_mux->reg, + PHY_MUX_MASK, + FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC)); +} + +const struct clk_ops clk_regmap_phy_mux_ops = { + .enable = phy_mux_enable, + .disable = phy_mux_disable, + .is_enabled = phy_mux_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops); diff --git a/drivers/clk/qcom/clk-regmap-phy-mux.h b/drivers/clk/qcom/clk-regmap-phy-mux.h new file mode 100644 index 000000000000..614dd384695c --- /dev/null +++ b/drivers/clk/qcom/clk-regmap-phy-mux.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Linaro Ltd. + */ + +#ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__ +#define __QCOM_CLK_REGMAP_PHY_MUX_H__ + +#include "clk-regmap.h" + +/* + * A clock implementation for PHY pipe and symbols clock muxes. + * + * If the clock is running off the from-PHY source, report it as enabled. + * Report it as disabled otherwise (if it uses reference source). + * + * This way the PHY will disable the pipe clock before turning off the GDSC, + * which in turn would lead to disabling corresponding pipe_clk_src (and thus + * it being parked to a safe, reference clock source). And vice versa, after + * enabling the GDSC the PHY will enable the pipe clock, which would cause + * pipe_clk_src to be switched from a safe source to the working one. + * + * For some platforms this should be used for the UFS symbol_clk_src clocks + * too. + */ +struct clk_regmap_phy_mux { + u32 reg; + struct clk_regmap clkr; +}; + +extern const struct clk_ops clk_regmap_phy_mux_ops; + +#endif From 7ee9d2e8b9c9f4a829cd2d77c8cba36c514f24ba Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 8 Jun 2022 13:52:35 +0300 Subject: [PATCH 32/93] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220608105238.2973600-3-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-sm8450.c | 49 ++++++++++------------------------- 1 file changed, 13 insertions(+), 36 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..666efa5ff978 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "gdsc.h" #include "reset.h" @@ -26,9 +27,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, - P_PCIE_0_PIPE_CLK, P_PCIE_1_PHY_AUX_CLK, - P_PCIE_1_PIPE_CLK, P_SLEEP_CLK, P_UFS_PHY_RX_SYMBOL_0_CLK, P_UFS_PHY_RX_SYMBOL_1_CLK, @@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -239,17 +218,16 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; @@ -269,17 +247,16 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; From 553d12b20c10953617cc195f9e447a177c776f9d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 8 Jun 2022 13:52:36 +0300 Subject: [PATCH 33/93] clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220608105238.2973600-4-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-sc7280.c | 49 +++++++++++------------------------ 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 423627d49719..7ff64d4d5920 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -17,6 +17,7 @@ #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "common.h" #include "gdsc.h" #include "reset.h" @@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .hw = &gcc_gpll0_out_even.clkr.hw }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -369,32 +350,32 @@ static const struct clk_parent_data gcc_parent_data_15[] = { { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x6b054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + .name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x8d054, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + .name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; From c4f40351901a10cd662ac2c081396d8fb04f584d Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 18 May 2022 13:35:54 +0300 Subject: [PATCH 34/93] clk: qcom: camcc-sm8250: Fix halt on boot by reducing driver's init level Access to I/O of SM8250 camera clock controller IP depends on enabled GCC_CAMERA_AHB_CLK clock supplied by global clock controller, the latter one is inited on subsys level, so, to satisfy the dependency, it would make sense to deprive the init level of camcc-sm8250 driver. If both drivers are compiled as built-in, there is a change that a board won't boot up due to a race, which happens on the same init level. Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220518103554.949511-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/camcc-sm8250.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index 439eaafdcc86..ae4e9774f36e 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -2440,17 +2440,7 @@ static struct platform_driver cam_cc_sm8250_driver = { }, }; -static int __init cam_cc_sm8250_init(void) -{ - return platform_driver_register(&cam_cc_sm8250_driver); -} -subsys_initcall(cam_cc_sm8250_init); - -static void __exit cam_cc_sm8250_exit(void) -{ - platform_driver_unregister(&cam_cc_sm8250_driver); -} -module_exit(cam_cc_sm8250_exit); +module_platform_driver(cam_cc_sm8250_driver); MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver"); MODULE_LICENSE("GPL v2"); From e73cb8527c597598599119fcd9c7d1752d9e9fd7 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 20 May 2022 12:09:46 +0200 Subject: [PATCH 35/93] clk: qcom: gdsc: add collapse-bit helper Add a helper for updating the SW_COLLAPSE bit during initialisation and state updates. Note that the update during initialisation was relying on the SW_COLLAPSE bit not having been set earlier rather than passing in zero explicitly to clear the collapse vote. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220520100948.19622-2-johan+linaro@kernel.org --- drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 44520efc6c72..c676416e685f 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -132,10 +132,24 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) return -ETIMEDOUT; } +static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) +{ + u32 reg, mask; + int ret; + + reg = sc->gdscr; + mask = SW_COLLAPSE_MASK; + + ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0); + if (ret) + return ret; + + return 0; +} + static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) { int ret; - u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK; if (status == GDSC_ON && sc->rsupply) { ret = regulator_enable(sc->rsupply); @@ -143,9 +157,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) return ret; } - ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); - if (ret) - return ret; + ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF); /* If disabling votable gdscs, don't poll on status */ if ((sc->flags & VOTABLE) && status == GDSC_OFF) { @@ -425,8 +437,7 @@ static int gdsc_init(struct gdsc *sc) * If a Votable GDSC is ON, make sure we have a Vote. */ if (sc->flags & VOTABLE) { - ret = regmap_update_bits(sc->regmap, sc->gdscr, - SW_COLLAPSE_MASK, val); + ret = gdsc_update_collapse_bit(sc, false); if (ret) return ret; } From 77ea2bd72da4f61f59ad2e839babe83849f35dea Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 20 May 2022 12:09:47 +0200 Subject: [PATCH 36/93] clk: qcom: gdsc: add support for collapse-vote registers Recent Qualcomm platforms have APCS collapse-vote registers that allow for sharing GDSCs with other masters (e.g. LPASS). Add support for using such vote registers instead of the control register when updating the GDSC power state. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220520100948.19622-3-johan+linaro@kernel.org --- drivers/clk/qcom/gdsc.c | 9 +++++++-- drivers/clk/qcom/gdsc.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index c676416e685f..6f746158d28f 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -137,8 +137,13 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val) u32 reg, mask; int ret; - reg = sc->gdscr; - mask = SW_COLLAPSE_MASK; + if (sc->collapse_mask) { + reg = sc->collapse_ctrl; + mask = sc->collapse_mask; + } else { + reg = sc->gdscr; + mask = SW_COLLAPSE_MASK; + } ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0); if (ret) diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index ad313d7210bd..5de48c9439b2 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -18,6 +18,8 @@ struct reset_controller_dev; * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @collapse_ctrl: APCS collapse-vote register + * @collapse_mask: APCS collapse-vote mask * @gds_hw_ctrl: gds_hw_ctrl register * @cxcs: offsets of branch registers to toggle mem/periph bits in * @cxc_count: number of @cxcs @@ -35,6 +37,8 @@ struct gdsc { struct generic_pm_domain *parent; struct regmap *regmap; unsigned int gdscr; + unsigned int collapse_ctrl; + unsigned int collapse_mask; unsigned int gds_hw_ctrl; unsigned int clamp_io_ctrl; unsigned int *cxcs; From 8d114b94fc39210b88b203b57aaf04836a87a4f0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 20 May 2022 12:09:48 +0200 Subject: [PATCH 37/93] clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org --- drivers/clk/qcom/gcc-sc8280xp.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 4b894442fdf5..f186ddf6954e 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6807,58 +6807,79 @@ static struct clk_branch gcc_video_vcodec_throttle_clk = { static struct gdsc pcie_0_tunnel_gdsc = { .gdscr = 0xa4004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(0), .pd = { .name = "pcie_0_tunnel_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_1_tunnel_gdsc = { .gdscr = 0x8d004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(1), .pd = { .name = "pcie_1_tunnel_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_2a_gdsc = { .gdscr = 0x9d004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(2), .pd = { .name = "pcie_2a_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_2b_gdsc = { .gdscr = 0x9e004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(3), .pd = { .name = "pcie_2b_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_3a_gdsc = { .gdscr = 0xa0004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(4), .pd = { .name = "pcie_3a_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_3b_gdsc = { .gdscr = 0xa2004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(5), .pd = { .name = "pcie_3b_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc pcie_4_gdsc = { .gdscr = 0x6b004, + .collapse_ctrl = 0x52128, + .collapse_mask = BIT(6), .pd = { .name = "pcie_4_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, }; static struct gdsc ufs_card_gdsc = { From 255a47e745674dbbda9250ae0ad1f78a49179988 Mon Sep 17 00:00:00 2001 From: Li kunyu Date: Mon, 27 Jun 2022 10:05:00 +0800 Subject: [PATCH 38/93] clk: qcom: gcc-sm6350: Drop extra semicolon Drop the extra semicolon after qcom_cc_really_probe() Signed-off-by: Li kunyu [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220627020500.135125-1-kunyu@nfschina.com --- drivers/clk/qcom/gcc-sm6350.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c index a4f7fba70393..69412400efa4 100644 --- a/drivers/clk/qcom/gcc-sm6350.c +++ b/drivers/clk/qcom/gcc-sm6350.c @@ -2558,7 +2558,7 @@ static int gcc_sm6350_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);; + return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap); } static struct platform_driver gcc_sm6350_driver = { From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 30 Apr 2022 07:44:56 +0200 Subject: [PATCH 39/93] clk: qcom: clk-hfpll: use poll_timeout macro Use regmap_read_poll_timeout macro instead of do-while structure to tidy things up. Also set a timeout to prevent any sort of system stall. Signed-off-by: Ansuel Smith Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..7dd17c184b69 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + /* + * Busy wait. Should never timeout, we add a timeout to + * prevent any sort of stall. + */ + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), 0, + 100 * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); From df83d2c9e72910416f650ade1e07cc314ff02731 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 30 Apr 2022 07:44:57 +0200 Subject: [PATCH 40/93] clk: qcom: clk-krait: unlock spin after mux completion Unlock spinlock after the mux switch is completed to prevent any corner case of mux request while the switch still needs to be done. Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks") Signed-off-by: Ansuel Smith Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220430054458.31321-3-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-krait.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 59f1af415b58..90046428693c 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -32,11 +32,16 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); } krait_set_l2_indirect_reg(mux->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); /* Wait for switch to complete. */ mb(); udelay(1); + + /* + * Unlock now to make sure the mux register is not + * modified while switching to the new parent. + */ + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); } static int krait_mux_set_parent(struct clk_hw *hw, u8 index) From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 30 Apr 2022 07:44:58 +0200 Subject: [PATCH 41/93] clk: qcom: clk-krait: add apq/ipq8064 errata workaround Add apq/ipq8064 errata workaround where the sec_src clock gating needs to be disabled during switching. krait-cc compatible is not enough to handle this and limit this workaround to apq/ipq8064. We check machine compatible to handle this. Signed-off-by: Ansuel Smith Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 90046428693c..45da736bd5f4 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval = krait_get_l2_indirect_reg(mux->offset); + + /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |= SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &= ~(mux->mask << mux->shift); regval |= (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); + /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &= ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..cfd961d5cc45 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, int id, const char *s, mux->hw.init = &init; mux->safe_sel = 0; + /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not + * enough to limit this to apq/ipq8064. Directly check machine + * compatible to correctly handle this errata. + */ + if (of_machine_is_compatible("qcom,ipq8064") || + of_machine_is_compatible("qcom,apq8064")) + mux->disable_sec_src_gating = true; + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) return -ENOMEM; From d62cac46b0184b8730c68b01359a33769fee821b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 13 May 2022 08:13:41 +0200 Subject: [PATCH 42/93] dt-bindings: clock: qcom,gcc-sdm845: add parent power domain Allow Qualcomm GCC to register its parent power domain (e.g. RPMHPD) to properly pass performance state from children. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220513061347.46480-2-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml index d902f137ab17..daf7906ebc40 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -43,6 +43,9 @@ properties: '#reset-cells': const: 1 + power-domains: + maxItems: 1 + '#power-domain-cells': const: 1 From 9410fb940114444f37a0b787bd84077b61d76bf6 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 28 Jun 2022 10:57:07 +0200 Subject: [PATCH 43/93] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe Use the new phy-mux clock implementation for the PCIe pipe clock muxes so that the pipe clock source is set to the QMP PHY PLL when the downstream pipe clock is enabled and restored to the always-on XO when it is again disabled. This is needed to prevent the corresponding GDSC from hanging when enabling or disabling the PCIe power domain, something which requires a ticking source. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org --- drivers/clk/qcom/gcc-sc8280xp.c | 121 ++++++++------------------------ 1 file changed, 31 insertions(+), 90 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index f186ddf6954e..a2f3ffcc5849 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -20,6 +20,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "common.h" #include "gdsc.h" #include "reset.h" @@ -82,11 +83,6 @@ enum { P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, - P_PCIE_2A_PIPE_CLK, - P_PCIE_2B_PIPE_CLK, - P_PCIE_3A_PIPE_CLK, - P_PCIE_3B_PIPE_CLK, - P_PCIE_4_PIPE_CLK, P_QUSB4PHY_1_GCC_USB4_RX0_CLK, P_QUSB4PHY_1_GCC_USB4_RX1_CLK, P_QUSB4PHY_GCC_USB4_RX0_CLK, @@ -351,56 +347,6 @@ static const struct clk_parent_data gcc_parent_data_9[] = { { .hw = &gcc_gpll0_out_even.clkr.hw }, }; -static const struct parent_map gcc_parent_map_10[] = { - { P_PCIE_2A_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_10[] = { - { .index = DT_PCIE_2A_PIPE_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_11[] = { - { P_PCIE_2B_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_11[] = { - { .index = DT_PCIE_2B_PIPE_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_12[] = { - { P_PCIE_3A_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_12[] = { - { .index = DT_PCIE_3A_PIPE_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_13[] = { - { P_PCIE_3B_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_13[] = { - { .index = DT_PCIE_3B_PIPE_CLK }, - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map gcc_parent_map_14[] = { - { P_PCIE_4_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_14[] = { - { .index = DT_PCIE_4_PIPE_CLK }, - { .index = DT_BI_TCXO }, -}; - static const struct parent_map gcc_parent_map_15[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -741,77 +687,72 @@ static const struct clk_parent_data gcc_parent_data_41[] = { { .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK }, }; -static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = { .reg = 0x9d05c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_10, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_2a_pipe_clk_src", - .parent_data = gcc_parent_data_10, - .num_parents = ARRAY_SIZE(gcc_parent_data_10), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_2A_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = { .reg = 0x9e05c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_11, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_2b_pipe_clk_src", - .parent_data = gcc_parent_data_11, - .num_parents = ARRAY_SIZE(gcc_parent_data_11), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_2B_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = { .reg = 0xa005c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_12, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_3a_pipe_clk_src", - .parent_data = gcc_parent_data_12, - .num_parents = ARRAY_SIZE(gcc_parent_data_12), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_3A_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = { .reg = 0xa205c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_13, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_3b_pipe_clk_src", - .parent_data = gcc_parent_data_13, - .num_parents = ARRAY_SIZE(gcc_parent_data_13), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_3B_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; -static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = { .reg = 0x6b05c, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_14, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_4_pipe_clk_src", - .parent_data = gcc_parent_data_14, - .num_parents = ARRAY_SIZE(gcc_parent_data_14), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_4_PIPE_CLK, + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; From 07e7fcf1714c5f9930ad27613fea940aedba68da Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 4 May 2022 17:38:32 +0100 Subject: [PATCH 44/93] clk: qcom: gcc-msm8939: Add missing SYSTEM_MM_NOC_BFDCD_CLK_SRC When adding in the indexes for this clock-controller we missed SYSTEM_MM_NOC_BFDCD_CLK_SRC. Add it in now. Fixes: 4c71d6abc4fc ("clk: qcom: Add DT bindings for MSM8939 GCC") Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org Signed-off-by: Bryan O'Donoghue Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220504163835.40130-2-bryan.odonoghue@linaro.org --- include/dt-bindings/clock/qcom,gcc-msm8939.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h index 0634467c4ce5..2d545ed0d35a 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8939.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h @@ -192,6 +192,7 @@ #define GCC_VENUS0_CORE0_VCODEC0_CLK 183 #define GCC_VENUS0_CORE1_VCODEC0_CLK 184 #define GCC_OXILI_TIMER_CLK 185 +#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186 /* Indexes for GDSCs */ #define BIMC_GDSC 0 From 63d42708320d6d2ca9ed505123d50ff4a542c36f Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 4 May 2022 17:38:33 +0100 Subject: [PATCH 45/93] clk: qcom: gcc-msm8939: Fix bimc_ddr_clk_src rcgr base address Reviewing qcom docs for the 8939 we can see the command rcgr is pointing to the wrong address. bimc_ddr_clk_src_rcgr is @ 0x01832024 not 0x01832004. Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220504163835.40130-3-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 39ebb443ae3d..31568658d23d 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -632,7 +632,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { }; static struct clk_rcg2 bimc_ddr_clk_src = { - .cmd_rcgr = 0x32004, + .cmd_rcgr = 0x32024, .hid_width = 5, .parent_map = gcc_xo_gpll0_bimc_map, .clkr.hw.init = &(struct clk_init_data){ From dd363e2f7196278e7a30f509a0e8a841cb763b14 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 4 May 2022 17:38:34 +0100 Subject: [PATCH 46/93] clk: qcom: gcc-msm8939: Add missing system_mm_noc_bfdcd_clk_src The msm8939 has an additional higher operating point for the multi-media peripherals. The higher throughput MM componets operate off of the system-mm noc not the system noc. system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency capable system noc mm. Maximum frequency for the MM SNOC is 400 MHz. Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220504163835.40130-4-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 31568658d23d..12bab9067ea8 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -644,6 +644,18 @@ static struct clk_rcg2 bimc_ddr_clk_src = { }, }; +static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = { + .cmd_rcgr = 0x2600c, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6a_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_mm_noc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll6a_parent_data, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { F(40000000, P_GPLL0, 10, 1, 2), F(80000000, P_GPLL0, 10, 0, 0), @@ -3623,6 +3635,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = { [GPLL2_VOTE] = &gpll2_vote, [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, + [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr, [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, [CSI0_CLK_SRC] = &csi0_clk_src.clkr, From 05eed0990927aa9634682fec58660e30f7b7ae30 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 4 May 2022 17:38:35 +0100 Subject: [PATCH 47/93] clk: qcom: gcc-msm8939: Point MM peripherals to system_mm_noc clock Qcom docs indciate the following peripherals operating from System NOC MM not from System NOC clocks. - MDP - VFE - JPEGe - Venus Switch over the relevant parent pointers. Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220504163835.40130-5-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 12bab9067ea8..c7377ec0f423 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -2453,7 +2453,7 @@ static struct clk_branch gcc_camss_jpeg_axi_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_camss_jpeg_axi_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2657,7 +2657,7 @@ static struct clk_branch gcc_camss_vfe_axi_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_camss_vfe_axi_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2813,7 +2813,7 @@ static struct clk_branch gcc_mdss_axi_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_axi_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3205,7 +3205,7 @@ static struct clk_branch gcc_mdp_tbu_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_mdp_tbu_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3223,7 +3223,7 @@ static struct clk_branch gcc_venus_tbu_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_venus_tbu_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3241,7 +3241,7 @@ static struct clk_branch gcc_vfe_tbu_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_vfe_tbu_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3259,7 +3259,7 @@ static struct clk_branch gcc_jpeg_tbu_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_jpeg_tbu_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3496,7 +3496,7 @@ static struct clk_branch gcc_venus0_axi_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_venus0_axi_clk", .parent_data = &(const struct clk_parent_data){ - .hw = &system_noc_bfdcd_clk_src.clkr.hw, + .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From ca41ec1b30434636c56c5600b24a8d964d359d9c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:38 +0200 Subject: [PATCH 48/93] clk: qcom: ipq8074: fix NSS core PLL-s MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-1-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 541016db3c4b..1a5141da7e23 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4772,7 +4799,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { From 3401ea2856ef84f39b75f0dc5ebcaeda81cb90ec Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:39 +0200 Subject: [PATCH 49/93] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1a5141da7e23..b4291ba53c78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4805,6 +4805,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* SW Workaround for UBI32 Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From 0e9e61a2815b5cd34f1b495b2d72e8127ce9b794 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:40 +0200 Subject: [PATCH 50/93] clk: qcom: ipq8074: fix NSS port frequency tables NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index b4291ba53c78..f1017f2e61bd 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_RX, 5, 0, 0), F(78125000, P_UNIPHY1_RX, 4, 0, 0), F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_RX, 1, 0, 0), F(156250000, P_UNIPHY1_RX, 2, 0, 0), F(312500000, P_UNIPHY1_RX, 1, 0, 0), { } @@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_TX, 5, 0, 0), F(78125000, P_UNIPHY1_TX, 4, 0, 0), F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_TX, 1, 0, 0), F(156250000, P_UNIPHY1_TX, 2, 0, 0), F(312500000, P_UNIPHY1_TX, 1, 0, 0), { } @@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_RX, 5, 0, 0), F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), F(78125000, P_UNIPHY2_RX, 4, 0, 0), + F(125000000, P_UNIPHY2_RX, 1, 0, 0), F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), F(156250000, P_UNIPHY2_RX, 2, 0, 0), F(312500000, P_UNIPHY2_RX, 1, 0, 0), @@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_TX, 5, 0, 0), F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), F(78125000, P_UNIPHY2_TX, 4, 0, 0), + F(125000000, P_UNIPHY2_TX, 1, 0, 0), F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), F(156250000, P_UNIPHY2_TX, 2, 0, 0), F(312500000, P_UNIPHY2_TX, 1, 0, 0), From 90e6d290603df6387c95c114cc8154862c3e7515 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:41 +0200 Subject: [PATCH 51/93] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock Add binding for the PPE crypto clock in IPQ8074. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..5f0928785d7a 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 From 74521205b64030b1321ccc04372729cfd2800996 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:42 +0200 Subject: [PATCH 52/93] clk: qcom: ipq8074: add PPE crypto clock The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index f1017f2e61bd..c964e43ba68a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { From 2bd357e698207e2e65db03007e4be65bf9d6a7b3 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:43 +0200 Subject: [PATCH 53/93] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index c964e43ba68a..85076c1383c7 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0), From 2c930dc1e34f08d32ccf1b2baf01dec56b41ab05 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:44 +0200 Subject: [PATCH 54/93] dt-bindings: clocks: qcom,gcc-ipq8074: support power domains GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-7-robimarko@gmail.com --- .../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 98572b4a9b60..21470f52ce36 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -24,6 +24,9 @@ properties: '#clock-cells': const: 1 + '#power-domain-cells': + const: 1 + '#reset-cells': const: 1 @@ -38,6 +41,7 @@ required: - compatible - reg - '#clock-cells' + - '#power-domain-cells' - '#reset-cells' additionalProperties: false @@ -48,6 +52,7 @@ examples: compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; ... From 74622e401e2109a9aacce0b9698bbcd2307db17a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:45 +0200 Subject: [PATCH 55/93] dt-bindings: clock: qcom: ipq8074: add USB GDSCs Add bindings for the USB GDSCs found in IPQ8074 GCC. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..55f8322a1e50 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -367,4 +367,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif From 8add990ace3db767c2dab59113fbdf137d237529 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:46 +0200 Subject: [PATCH 56/93] clk: qcom: ipq8074: add USB GDSCs Add GDSC-s for each of the two USB controllers built-in the IPQ8074. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bc4dcf356d82..fc45d00eec42 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -166,6 +166,7 @@ config IPQ_LCC_806X config IPQ_GCC_8074 tristate "IPQ8074 Global Clock Controller" + select QCOM_GDSC help Support for global clock controller on ipq8074 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 85076c1383c7..3204d550ff76 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -22,6 +22,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -4407,6 +4408,22 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static struct gdsc usb0_gdsc = { + .gdscr = 0x3e078, + .pd = { + .name = "usb0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb1_gdsc = { + .gdscr = 0x3f078, + .pd = { + .name = "usb1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static const struct alpha_pll_config ubi32_pll_config = { .l = 0x4e, .config_ctl_val = 0x200d4aa8, @@ -4810,6 +4827,11 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, }; +static struct gdsc *gcc_ipq8074_gdscs[] = { + [USB0_GDSC] = &usb0_gdsc, + [USB1_GDSC] = &usb1_gdsc, +}; + static const struct of_device_id gcc_ipq8074_match_table[] = { { .compatible = "qcom,gcc-ipq8074" }, { } @@ -4832,6 +4854,8 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), .clk_hws = gcc_ipq8074_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), + .gdscs = gcc_ipq8074_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), }; static int gcc_ipq8074_probe(struct platform_device *pdev) From 1bf7305e79aab095196131bdc87a97796e0e3fac Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 15 May 2022 23:00:47 +0200 Subject: [PATCH 57/93] clk: qcom: ipq8074: dont disable gcc_sleep_clk_src Once the usb sleep clocks are disabled, clock framework is trying to disable the sleep clock source also. However, it seems that it cannot be disabled and trying to do so produces: [ 245.436390] ------------[ cut here ]------------ [ 245.441233] gcc_sleep_clk_src status stuck at 'on' [ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140 [ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio [ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215 [ 245.463889] Hardware name: Xiaomi AX9000 (DT) [ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 245.474307] pc : clk_branch_wait+0x130/0x140 [ 245.481073] lr : clk_branch_wait+0x130/0x140 [ 245.485588] sp : ffffffc009f2bad0 [ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000 [ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20 [ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0 [ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7 [ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777 [ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129 [ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001 [ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001 [ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027 [ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026 [ 245.557122] Call trace: [ 245.564229] clk_branch_wait+0x130/0x140 [ 245.566490] clk_branch2_disable+0x2c/0x40 [ 245.570656] clk_core_disable+0x60/0xb0 [ 245.574561] clk_core_disable+0x68/0xb0 [ 245.578293] clk_disable+0x30/0x50 [ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom] [ 245.585588] platform_remove+0x28/0x60 [ 245.590361] device_remove+0x4c/0x80 [ 245.594179] device_release_driver_internal+0x1dc/0x230 [ 245.597914] device_driver_detach+0x18/0x30 [ 245.602861] unbind_store+0xec/0x110 [ 245.607027] drv_attr_store+0x24/0x40 [ 245.610847] sysfs_kf_write+0x44/0x60 [ 245.614405] kernfs_fop_write_iter+0x128/0x1c0 [ 245.618052] new_sync_write+0xc0/0x130 [ 245.622391] vfs_write+0x1d4/0x2a0 [ 245.626123] ksys_write+0x58/0xe0 [ 245.629508] __arm64_sys_write+0x1c/0x30 [ 245.632895] invoke_syscall.constprop.0+0x5c/0x110 [ 245.636890] do_el0_svc+0xa0/0x150 [ 245.641488] el0_svc+0x18/0x60 [ 245.644872] el0t_64_sync_handler+0xa4/0x130 [ 245.647914] el0t_64_sync+0x174/0x178 [ 245.652340] ---[ end trace 0000000000000000 ]--- So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try to disable the sleep clock. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220515210048.483898-10-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 3204d550ff76..42d185fe19c8 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -663,6 +663,7 @@ static struct clk_branch gcc_sleep_clk_src = { }, .num_parents = 1, .ops = &clk_branch2_ops, + .flags = CLK_IS_CRITICAL, }, }, }; From 103dd2338bbff567bce7acd00fc5a09c806b38ec Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 May 2022 00:41:32 +0300 Subject: [PATCH 58/93] clk: qcom: camcc-sdm845: Fix topology around titan_top power domain On SDM845 two found VFE GDSC power domains shall not be operated, if titan top is turned off, thus the former power domains will be set as subdomains by a GDSC registration routine. Fixes: 78412c262004 ("clk: qcom: Add camera clock controller driver for SDM845") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Robert Foss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220519214133.1728979-2-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/camcc-sdm845.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index be3f95326965..27d44188a7ab 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -1534,6 +1534,8 @@ static struct clk_branch cam_cc_sys_tmr_clk = { }, }; +static struct gdsc titan_top_gdsc; + static struct gdsc bps_gdsc = { .gdscr = 0x6004, .pd = { @@ -1567,6 +1569,7 @@ static struct gdsc ife_0_gdsc = { .name = "ife_0_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; @@ -1576,6 +1579,7 @@ static struct gdsc ife_1_gdsc = { .name = "ife_1_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; From f8acf01a6a4f84baf05181e24bd48def4ba23f5b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 20 May 2022 00:41:33 +0300 Subject: [PATCH 59/93] clk: qcom: camcc-sm8250: Fix topology around titan_top power domain On SM8250 two found VFE GDSC power domains shall not be operated, if titan top is turned off, thus the former power domains will be set as subdomains by a GDSC registration routine. Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Robert Foss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220519214133.1728979-3-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/camcc-sm8250.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index ae4e9774f36e..9b32c56a5bc5 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -2205,6 +2205,8 @@ static struct clk_branch cam_cc_sleep_clk = { }, }; +static struct gdsc titan_top_gdsc; + static struct gdsc bps_gdsc = { .gdscr = 0x7004, .pd = { @@ -2238,6 +2240,7 @@ static struct gdsc ife_0_gdsc = { .name = "ife_0_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; @@ -2247,6 +2250,7 @@ static struct gdsc ife_1_gdsc = { .name = "ife_1_gdsc", }, .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; From bdafb609c3bb848d710ad9cd4debd2ee9d6a4049 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sun, 12 Jun 2022 19:59:52 +0500 Subject: [PATCH 60/93] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled. In cases when MND is not enabled (e.g. when only Half Integer Divider is used), setting D registers makes no effect. Fail instead of making ineffective write. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220612145955.385787-2-nikita@trvn.ru --- drivers/clk/qcom/clk-rcg2.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 8e5dce09d162..2375e8122012 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -437,7 +437,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - u32 notn_m, n, m, d, not2d, mask, duty_per; + u32 notn_m, n, m, d, not2d, mask, duty_per, cfg; int ret; /* Duty-cycle cannot be modified for non-MND RCGs */ @@ -448,6 +448,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); + regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); + + /* Duty-cycle cannot be modified if MND divider is in bypass mode. */ + if (!(cfg & CFG_MODE_MASK)) + return -EINVAL; n = (~(notn_m) + m) & mask; From d0696770cef35a1fd16ea2167e2198c18aa6fbfe Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sun, 12 Jun 2022 19:59:53 +0500 Subject: [PATCH 61/93] clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register Sometimes calculation of d value may result in 0 because of the rounding after integer division. This causes the following error: [ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration. [ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc Make sure that D value is never zero. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru --- drivers/clk/qcom/clk-rcg2.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 2375e8122012..28019edd2a50 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -461,9 +462,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) /* Calculate 2d value */ d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100); - /* Check bit widths of 2d. If D is too big reduce duty cycle. */ - if (d > mask) - d = mask; + /* + * Check bit widths of 2d. If D is too big reduce duty cycle. + * Also make sure it is never zero. + */ + d = clamp_val(d, 1, mask); if ((d / 2) > (n - m)) d = (n - m) * 2; From bf8bb8eaccf4e68d79743da631f61252753ca7cd Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sun, 12 Jun 2022 19:59:55 +0500 Subject: [PATCH 62/93] clk: qcom: gcc-msm8916: Add rates to the GP clocks msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reviewed-by: Stephen Boyd Signed-off-by: Nikita Travkin Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ru --- drivers/clk/qcom/gcc-msm8916.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 17e4a5a2a9fd..9a46794f6eb8 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -765,7 +765,20 @@ static struct clk_rcg2 cci_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * See comment at ftbl_gcc_gp1_3_clk. + */ static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(100000000, P_GPLL0, 8, 0, 0), F(200000000, P_GPLL0, 4, 0, 0), { } @@ -927,7 +940,29 @@ static struct clk_rcg2 crypto_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * Please note that MND divider must be enabled for duty-cycle + * control to be possible. (M != N) Also since D register is configured + * with a value multiplied by 2, and duty cycle is calculated as + * (2 * D) % 2^W + * DutyCycle = ---------------- + * 2 * (N % 2^W) + * (where W = .mnd_width) + * N must be half or less than maximum value for the register. + * Otherwise duty-cycle control would be limited. + * (e.g. for 8-bit NMD N should be less than 128) + */ static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(19200000, P_XO, 1, 0, 0), { } }; From 91a4cbf93326f2d27dda7361c43a5bb24cfd93c3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 21 May 2022 18:14:34 +0300 Subject: [PATCH 63/93] dt-bindings: clock: qcom,gcc-apq8064: move msm8960 compat from gcc-other.yaml MSM8960 shares the design (and the driver) of the global clock controller with APQ8064. Move it from clock/qcom,gcc-other.yaml to clock/qcom,gcc-apq8064.yaml. As the example in gcc-other.yaml was using qcom,gcc-msm8960 compat string, change it to qcom,gcc-msm8974. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220521151437.1489111-2-dmitry.baryshkov@linaro.org --- .../devicetree/bindings/clock/qcom,gcc-apq8064.yaml | 6 ++++-- Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml | 5 ++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 9fafcb080069..bd7b04c75e50 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 +title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960 allOf: - $ref: qcom,gcc.yaml# @@ -23,7 +23,9 @@ description: | properties: compatible: - const: qcom,gcc-apq8064 + enum: + - qcom,gcc-apq8064 + - qcom,gcc-msm8960 nvmem-cells: minItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index 6c45e0f85494..6c78df0c46a9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -44,7 +44,6 @@ properties: - qcom,gcc-msm8916 - qcom,gcc-msm8939 - qcom,gcc-msm8953 - - qcom,gcc-msm8960 - qcom,gcc-msm8974 - qcom,gcc-msm8974pro - qcom,gcc-msm8974pro-ac @@ -58,10 +57,10 @@ required: unevaluatedProperties: false examples: - # Example for GCC for MSM8960: + # Example for GCC for MSM8974: - | clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; + compatible = "qcom,gcc-msm8974"; reg = <0x900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; From 621f984840928f0bd14b20c86b70a15590ed2d3e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 21 May 2022 18:14:35 +0300 Subject: [PATCH 64/93] dt-bindings: clock: qcom,gcc-apq8064: split tsens to the child node Split tsens properties to the child node of the gcc. This follows the lead of ipq8064 (which also uses a separate node for tsens) and makes device tree closer to other platforms, where tsens is a completely separate device. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220521151437.1489111-3-dmitry.baryshkov@linaro.org --- .../bindings/clock/qcom,gcc-apq8064.yaml | 40 ++++++++++++++----- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index bd7b04c75e50..3cf404c9325a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -23,13 +23,25 @@ description: | properties: compatible: - enum: - - qcom,gcc-apq8064 - - qcom,gcc-msm8960 + oneOf: + - items: + - enum: + - qcom,gcc-apq8064 + - qcom,gcc-msm8960 + - const: syscon + - enum: + - qcom,gcc-apq8064 + - qcom,gcc-msm8960 + deprecated: true + + thermal-sensor: + description: child tsens device + $ref: /schemas/thermal/qcom-tsens.yaml# nvmem-cells: minItems: 1 maxItems: 2 + deprecated: true description: Qualcomm TSENS (thermal sensor device) on some devices can be part of GCC and hence the TSENS properties can also be part @@ -39,31 +51,39 @@ properties: nvmem-cell-names: minItems: 1 + deprecated: true items: - const: calib - const: calib_backup '#thermal-sensor-cells': const: 1 + deprecated: true required: - compatible - - nvmem-cells - - nvmem-cell-names - - '#thermal-sensor-cells' unevaluatedProperties: false examples: - | clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; + compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - #thermal-sensor-cells = <1>; + + thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <0 178 4>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; }; ... From 93b793d88da8b2c7afd63c64772666ec4274efad Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 21 May 2022 18:14:36 +0300 Subject: [PATCH 65/93] clk: qcom: gcc-msm8960: create tsens device if there are no child nodes Currently gcc-msm8960 driver manually creates tsens platform device manually. It would be better to follow IPQ8064 approach, where tsens device is defined as gcc's child device in the device tree. If nothing else, it removes gcc's dependency on QFPROM, thus allowing clock controller to be probed earlier. Don't create it in case there are available child nodes (tsens) inside the gcc's device tree node. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220521151437.1489111-4-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8960.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 051745ef99c8..a6e13b91e4c8 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -3641,6 +3641,9 @@ static int gcc_msm8960_probe(struct platform_device *pdev) hfpll_l2.d = &hfpll_l2_8064_data; } + if (of_get_available_child_count(pdev->dev.of_node) != 0) + return devm_of_platform_populate(&pdev->dev); + tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1, NULL, 0); if (IS_ERR(tsens)) @@ -3655,7 +3658,8 @@ static int gcc_msm8960_remove(struct platform_device *pdev) { struct platform_device *tsens = platform_get_drvdata(pdev); - platform_device_unregister(tsens); + if (tsens) + platform_device_unregister(tsens); return 0; } From 668d361c9d893be3cbd4f3650e1934a62b204def Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Jun 2022 19:17:22 +0100 Subject: [PATCH 66/93] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just amend the RZ/Five CPG clock and reset definitions. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220622181723.13033-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 27e232733096..77cde8effdc7 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -108,6 +108,15 @@ #define R9A07G043_ADC_ADCLK 76 #define R9A07G043_ADC_PCLK 77 #define R9A07G043_TSU_PCLK 78 +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ +#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ +#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ /* R9A07G043 Resets */ #define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ @@ -180,5 +189,16 @@ #define R9A07G043_ADC_PRESETN 67 #define R9A07G043_ADC_ADRST_N 68 #define R9A07G043_TSU_PRESETN 69 +#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ +#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ +#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ + #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ From 95d48d270305ad2ce4e6e8d84a9fb6ea49d6f8aa Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Jun 2022 19:17:23 +0100 Subject: [PATCH 67/93] clk: renesas: r9a07g043: Add support for RZ/Five SoC Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for RZ/Five SoC. This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220622181723.13033-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 33c2bd8df2e5..37475465100d 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -36,9 +36,11 @@ enum clk_ids { CLK_PLL3_DIV2_4_2, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, +#ifdef CONFIG_ARM64 CLK_PLL5, CLK_PLL5_500, CLK_PLL5_250, +#endif CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, @@ -100,9 +102,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), +#ifdef CONFIG_ARM64 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), +#endif DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), @@ -126,12 +130,20 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { +#ifdef CONFIG_ARM64 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 0x514, 0), DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 0x518, 1), +#endif +#ifdef CONFIG_RISCV + DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, + 0x518, 0), + DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, + 0x518, 1), +#endif DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, @@ -243,9 +255,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { }; static struct rzg2l_reset r9a07g043_resets[] = { +#ifdef CONFIG_ARM64 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), +#endif +#ifdef CONFIG_RISCV + DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), +#endif DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), @@ -291,8 +308,13 @@ static struct rzg2l_reset r9a07g043_resets[] = { }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { +#ifdef CONFIG_ARM64 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, MOD_CLK_BASE + R9A07G043_IA55_CLK, +#endif +#ifdef CONFIG_RISCV + MOD_CLK_BASE + R9A07G043_IAX45_CLK, +#endif MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; @@ -310,11 +332,21 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Module Clocks */ .mod_clks = r9a07g043_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), +#ifdef CONFIG_ARM64 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, +#endif +#ifdef CONFIG_RISCV + .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, +#endif /* Resets */ .resets = r9a07g043_resets, +#ifdef CONFIG_ARM64 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ +#endif +#ifdef CONFIG_RISCV + .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ +#endif .has_clk_mon_regs = true, }; From 0e704f6c42dc64f081d0b1738d06b2dee9524f27 Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Thu, 23 Jun 2022 10:32:17 +0200 Subject: [PATCH 68/93] clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config A variable pointing to const isn't const itself. It'd have to contain "const" keyword after "*" too. Therefore, cpg_pll_config cannot be put to "rodata". Hence use __initdata instead of __initconst to fix this. Signed-off-by: Andi Kleen [js] more explanatory commit message. Signed-off-by: Jiri Slaby Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220623083217.26433-2-jslaby@suse.cz Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rcar-gen4-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index c7ed43d6aa67..e27832e5114f 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -23,7 +23,7 @@ #include "rcar-gen4-cpg.h" #include "rcar-cpg-lib.h" -static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst; +static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; From e67a004482c092e326b32f24d4542c85fb8f79bf Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Wed, 6 Jul 2022 17:43:33 +0200 Subject: [PATCH 69/93] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706154337.2026269-2-robert.foss@linaro.org --- .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From 909e5be2ca882a0384018370f065ef1c611e6ed9 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Wed, 6 Jul 2022 17:43:35 +0200 Subject: [PATCH 70/93] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706154337.2026269-4-robert.foss@linaro.org --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file From 494e984af5b26dd286baaaad8a621fd7a7258c21 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:26:21 +0300 Subject: [PATCH 71/93] dt-bindings: clock: add QCOM SM8450 camera clock bindings The change adds device tree bindings for camera clock controller found on SM8450 SoC. Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062622.2757831-2-vladimir.zapolskiy@linaro.org --- .../bindings/clock/qcom,sm8450-camcc.yaml | 80 +++++++++ include/dt-bindings/clock/qcom,sm8450-camcc.h | 159 ++++++++++++++++++ 2 files changed, 239 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8450-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml new file mode 100644 index 000000000000..268f4c6ae0ee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vladimir Zapolskiy + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SM8450. + + See also include/dt-bindings/clock/qcom,sm8450-camcc.h + +properties: + compatible: + const: qcom,sm8450-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8450-camcc.h b/include/dt-bindings/clock/qcom,sm8450-camcc.h new file mode 100644 index 000000000000..7ff67acf301a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-camcc.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_CLK 4 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 5 +#define CAM_CC_CAMNOC_DCD_XO_CLK 6 +#define CAM_CC_CCI_0_CLK 7 +#define CAM_CC_CCI_0_CLK_SRC 8 +#define CAM_CC_CCI_1_CLK 9 +#define CAM_CC_CCI_1_CLK_SRC 10 +#define CAM_CC_CORE_AHB_CLK 11 +#define CAM_CC_CPAS_AHB_CLK 12 +#define CAM_CC_CPAS_BPS_CLK 13 +#define CAM_CC_CPAS_FAST_AHB_CLK 14 +#define CAM_CC_CPAS_IFE_0_CLK 15 +#define CAM_CC_CPAS_IFE_1_CLK 16 +#define CAM_CC_CPAS_IFE_2_CLK 17 +#define CAM_CC_CPAS_IFE_LITE_CLK 18 +#define CAM_CC_CPAS_IPE_NPS_CLK 19 +#define CAM_CC_CPAS_SBI_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPAS_SFE_1_CLK 22 +#define CAM_CC_CPHY_RX_CLK_SRC 23 +#define CAM_CC_CSI0PHYTIMER_CLK 24 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI1PHYTIMER_CLK 26 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI2PHYTIMER_CLK 28 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI3PHYTIMER_CLK 30 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI4PHYTIMER_CLK 32 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI5PHYTIMER_CLK 34 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSID_CLK 36 +#define CAM_CC_CSID_CLK_SRC 37 +#define CAM_CC_CSID_CSIPHY_RX_CLK 38 +#define CAM_CC_CSIPHY0_CLK 39 +#define CAM_CC_CSIPHY1_CLK 40 +#define CAM_CC_CSIPHY2_CLK 41 +#define CAM_CC_CSIPHY3_CLK 42 +#define CAM_CC_CSIPHY4_CLK 43 +#define CAM_CC_CSIPHY5_CLK 44 +#define CAM_CC_FAST_AHB_CLK_SRC 45 +#define CAM_CC_GDSC_CLK 46 +#define CAM_CC_ICP_AHB_CLK 47 +#define CAM_CC_ICP_CLK 48 +#define CAM_CC_ICP_CLK_SRC 49 +#define CAM_CC_IFE_0_CLK 50 +#define CAM_CC_IFE_0_CLK_SRC 51 +#define CAM_CC_IFE_0_DSP_CLK 52 +#define CAM_CC_IFE_0_FAST_AHB_CLK 53 +#define CAM_CC_IFE_1_CLK 54 +#define CAM_CC_IFE_1_CLK_SRC 55 +#define CAM_CC_IFE_1_DSP_CLK 56 +#define CAM_CC_IFE_1_FAST_AHB_CLK 57 +#define CAM_CC_IFE_2_CLK 58 +#define CAM_CC_IFE_2_CLK_SRC 59 +#define CAM_CC_IFE_2_DSP_CLK 60 +#define CAM_CC_IFE_2_FAST_AHB_CLK 61 +#define CAM_CC_IFE_LITE_AHB_CLK 62 +#define CAM_CC_IFE_LITE_CLK 63 +#define CAM_CC_IFE_LITE_CLK_SRC 64 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK 66 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67 +#define CAM_CC_IPE_NPS_AHB_CLK 68 +#define CAM_CC_IPE_NPS_CLK 69 +#define CAM_CC_IPE_NPS_CLK_SRC 70 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71 +#define CAM_CC_IPE_PPS_CLK 72 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73 +#define CAM_CC_JPEG_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_MCLK0_CLK 76 +#define CAM_CC_MCLK0_CLK_SRC 77 +#define CAM_CC_MCLK1_CLK 78 +#define CAM_CC_MCLK1_CLK_SRC 79 +#define CAM_CC_MCLK2_CLK 80 +#define CAM_CC_MCLK2_CLK_SRC 81 +#define CAM_CC_MCLK3_CLK 82 +#define CAM_CC_MCLK3_CLK_SRC 83 +#define CAM_CC_MCLK4_CLK 84 +#define CAM_CC_MCLK4_CLK_SRC 85 +#define CAM_CC_MCLK5_CLK 86 +#define CAM_CC_MCLK5_CLK_SRC 87 +#define CAM_CC_MCLK6_CLK 88 +#define CAM_CC_MCLK6_CLK_SRC 89 +#define CAM_CC_MCLK7_CLK 90 +#define CAM_CC_MCLK7_CLK_SRC 91 +#define CAM_CC_PLL0 92 +#define CAM_CC_PLL0_OUT_EVEN 93 +#define CAM_CC_PLL0_OUT_ODD 94 +#define CAM_CC_PLL1 95 +#define CAM_CC_PLL1_OUT_EVEN 96 +#define CAM_CC_PLL2 97 +#define CAM_CC_PLL3 98 +#define CAM_CC_PLL3_OUT_EVEN 99 +#define CAM_CC_PLL4 100 +#define CAM_CC_PLL4_OUT_EVEN 101 +#define CAM_CC_PLL5 102 +#define CAM_CC_PLL5_OUT_EVEN 103 +#define CAM_CC_PLL6 104 +#define CAM_CC_PLL6_OUT_EVEN 105 +#define CAM_CC_PLL7 106 +#define CAM_CC_PLL7_OUT_EVEN 107 +#define CAM_CC_PLL8 108 +#define CAM_CC_PLL8_OUT_EVEN 109 +#define CAM_CC_QDSS_DEBUG_CLK 110 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 111 +#define CAM_CC_QDSS_DEBUG_XO_CLK 112 +#define CAM_CC_SBI_AHB_CLK 113 +#define CAM_CC_SBI_CLK 114 +#define CAM_CC_SFE_0_CLK 115 +#define CAM_CC_SFE_0_CLK_SRC 116 +#define CAM_CC_SFE_0_FAST_AHB_CLK 117 +#define CAM_CC_SFE_1_CLK 118 +#define CAM_CC_SFE_1_CLK_SRC 119 +#define CAM_CC_SFE_1_FAST_AHB_CLK 120 +#define CAM_CC_SLEEP_CLK 121 +#define CAM_CC_SLEEP_CLK_SRC 122 +#define CAM_CC_SLOW_AHB_CLK_SRC 123 +#define CAM_CC_XO_CLK_SRC 124 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IFE_2_BCR 4 +#define CAM_CC_IPE_0_BCR 5 +#define CAM_CC_QDSS_DEBUG_BCR 6 +#define CAM_CC_SBI_BCR 7 +#define CAM_CC_SFE_0_BCR 8 +#define CAM_CC_SFE_1_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define SBI_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define IFE_2_GDSC 5 +#define SFE_0_GDSC 6 +#define SFE_1_GDSC 7 +#define TITAN_TOP_GDSC 8 + +#endif From 94bed9bb05c7850ff5d80b87cc29004901f37956 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:27:11 +0300 Subject: [PATCH 72/93] clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description After merging lucid and trion pll functions in commit 0b01489475c6 ("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid") the function clk_trion_pll_configure() is left with an old description header, which results in a W=2 compile time warning, fix it. Acked-by: Stephen Boyd Reviewed-by: Vinod Koul Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062711.2757855-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..288692f0ea39 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1439,7 +1439,7 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); /** - * clk_lucid_pll_configure - configure the lucid pll + * clk_trion_pll_configure - configure the trion pll * * @pll: clk alpha pll * @regmap: register map From 74d40ace3f08ce4d81b4a7e5d4d87a7294f55d36 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:27:20 +0300 Subject: [PATCH 73/93] clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code Unify all exported PLL clock configuration functions and data structures as GPL symbols. Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Reviewed-by: Vinod Koul Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062720.2757874-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 288692f0ea39..47879ee5a677 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1823,7 +1823,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { .round_rate = clk_alpha_pll_round_rate, .set_rate = alpha_pll_lucid_5lpe_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { .enable = alpha_pll_lucid_5lpe_enable, @@ -1832,14 +1832,14 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) @@ -1992,7 +1992,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_zonda_pll_set_rate, }; -EXPORT_SYMBOL(clk_alpha_pll_zonda_ops); +EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { From 260e36606a0391a300bbe412b339bb68fc7aa7d9 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:27:29 +0300 Subject: [PATCH 74/93] clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces Add controls for Lucid EVO PLL configuration and export control functions to clock controller drivers, the PLL is used by Qualcomm SM8450 camera and display clock controllers. Reviewed-by: Vinod Koul Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062729.2757893-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/clk-alpha-pll.c | 64 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 5 ++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47879ee5a677..cdb1035ae3ed 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -191,8 +191,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) /* LUCID EVO PLL specific settings and offsets */ +#define LUCID_EVO_PCAL_NOT_DONE BIT(8) #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) +#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 /* ZONDA PLL specific */ #define ZONDA_PLL_OUT_MASK 0xf @@ -1994,6 +1996,32 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 lval = config->l; + + lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + + /* Disable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); + + /* Set operation mode to STANDBY and de-assert the reset */ + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); +} +EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); + static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); @@ -2079,6 +2107,31 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); } +static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + struct clk_hw *p; + u32 val = 0; + int ret; + + /* Return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); + if (!(val & LUCID_EVO_PCAL_NOT_DONE)) + return 0; + + p = clk_hw_get_parent(hw); + if (!p) + return -EINVAL; + + ret = alpha_pll_lucid_evo_enable(hw); + if (ret) + return ret; + + alpha_pll_lucid_evo_disable(hw); + + return 0; +} + static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -2114,3 +2167,14 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { .set_rate = clk_lucid_evo_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); + +const struct clk_ops clk_alpha_pll_lucid_evo_ops = { + .prepare = alpha_pll_lucid_evo_prepare, + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..0b7a6859ca2c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -152,6 +152,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops + +extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; @@ -168,6 +170,7 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); - +void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif From bbc780132d626fdacaee0dab3376250ccd3a1a22 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:27:39 +0300 Subject: [PATCH 75/93] clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces Add and export Rivian EVO PLL configuration and control functions to clock controller drivers, the PLL is used by SM8450 camera clock controller. Reviewed-by: Stephen Boyd Reviewed-by: Vinod Koul Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062739.2757912-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/clk-alpha-pll.c | 70 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 6 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index cdb1035ae3ed..b42684703fbb 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { + [PLL_OFF_OPMODE] = 0x04, + [PLL_OFF_STATUS] = 0x0c, + [PLL_OFF_L_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x14, + [PLL_OFF_USER_CTL_U] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x1c, + [PLL_OFF_CONFIG_CTL_U] = 0x20, + [PLL_OFF_CONFIG_CTL_U1] = 0x24, + [PLL_OFF_TEST_CTL] = 0x28, + [PLL_OFF_TEST_CTL_U] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -2178,3 +2190,61 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { .set_rate = alpha_pll_lucid_5lpe_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); + +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); + + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + regmap_update_bits(regmap, PLL_MODE(pll), + PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, + PLL_RESET_N | PLL_BYPASSNL); +} +EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); + +static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + + return parent_rate * l; +} + +static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long min_freq, max_freq; + u32 l; + u64 a; + + rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) + return rate; + + min_freq = pll->vco_table[0].min_freq; + max_freq = pll->vco_table[pll->num_vco - 1].max_freq; + + return clamp(rate, min_freq, max_freq); +} + +const struct clk_ops clk_alpha_pll_rivian_evo_ops = { + .enable = alpha_pll_lucid_5lpe_enable, + .disable = alpha_pll_lucid_5lpe_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_rivian_evo_pll_recalc_rate, + .round_rate = clk_rivian_evo_pll_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 0b7a6859ca2c..447efb82fe59 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -157,6 +158,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; +#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, @@ -172,5 +176,7 @@ void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif From 6082037fe62eb17aa3029fd5524fe3b02223f48b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 1 Jul 2022 09:27:44 +0300 Subject: [PATCH 76/93] clk: qcom: add camera clock controller driver for SM8450 SoC Add camera clock controller driver found on Qualcomm SM8450 SoC. Reviewed-by: Bjorn Andersson Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sm8450.c | 2856 +++++++++++++++++++++++++++++++ 3 files changed, 2864 insertions(+) create mode 100644 drivers/clk/qcom/camcc-sm8450.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index fc45d00eec42..f5e03350ea75 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -609,6 +609,13 @@ config SM_CAMCC_8250 Support for the camera clock controller on SM8250 devices. Say Y if you want to support camera devices and camera functionality. +config SM_CAMCC_8450 + tristate "SM8450 Camera Clock Controller" + select SM_GCC_8450 + help + Support for the camera clock controller on SM8450 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_6125 tristate "SM6125 Display Clock Controller" depends on SM_GCC_6125 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 08594230c1c1..7b52244c96ba 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o +obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c new file mode 100644 index 000000000000..e3c09471dadf --- /dev/null +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -0,0 +1,2856 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL7_OUT_EVEN, + P_CAM_CC_PLL8_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static const struct pll_vco rivian_evo_vco[] = { + { 864000000, 1056000000, 0 }, +}; + +static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO }; + +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x25, + .alpha = 0xeaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x90008820, + .config_ctl_hi_val = 0x00890263, + .config_ctl_hi1_val = 0x00000217, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .vco_table = rivian_evo_vco, + .num_vco = ARRAY_SIZE(rivian_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll7_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll7 = { + .offset = 0x7000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { + .offset = 0x7000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll7_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll8_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll cam_cc_pll8 = { + .offset = 0x8000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8", + .parent_data = &pll_parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { + .offset = 0x8000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll8_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8_out_even", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL8_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll8_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll7_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_9[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9_ao[] = { + { .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { + .cmd_rcgr = 0x13194, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x1312c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x13148, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x1104c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x1514c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x1516c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x1518c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x13174, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x13108, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { + F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_clk_src = { + .cmd_rcgr = 0x12064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ife_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x1008c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x130dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x131bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { + F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_0_clk_src = { + .cmd_rcgr = 0x13064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { + F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_1_clk_src = { + .cmd_rcgr = 0x130ac, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_7, + .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk_src", + .parent_data = cam_cc_parent_data_7, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x13210, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_8, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_8, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10034, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x131f4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_9, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_9_ao, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch cam_cc_gdsc_clk = { + .halt_reg = 0x1320c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1320c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_gdsc_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x1004c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1004c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x10068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_clk = { + .halt_reg = 0x131ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x131b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x13144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x13160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x131f0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x131f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x13164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x10070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x1316c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1316c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x11038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk = { + .halt_reg = 0x12038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_2_clk = { + .halt_reg = 0x12084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_2_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x13020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x100ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sbi_clk = { + .halt_reg = 0x100ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sbi_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_0_clk = { + .halt_reg = 0x13084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_1_clk = { + .halt_reg = 0x130cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x1513c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1513c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x15164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x15184, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15184, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x151a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x1318c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1318c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x15140, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x15168, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15168, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x15188, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15188, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x151a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy5_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x13128, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13128, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x13120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_dsp_clk = { + .halt_reg = 0x1103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1103c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_dsp_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0x12030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_dsp_clk = { + .halt_reg = 0x1203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_dsp_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { + .halt_reg = 0x12048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_clk = { + .halt_reg = 0x1207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1207c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_dsp_clk = { + .halt_reg = 0x12088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_dsp_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { + .halt_reg = 0x12094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x13018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x13044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x1303c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1303c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x100c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x100a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x100c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x100b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x100c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x130f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x131d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x131d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_ahb_clk = { + .halt_reg = 0x100f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_clk = { + .halt_reg = 0x100e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_clk = { + .halt_reg = 0x1307c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1307c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { + .halt_reg = 0x13090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_clk = { + .halt_reg = 0x130c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { + .halt_reg = 0x130d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_fast_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sleep_clk = { + .halt_reg = 0x13228, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13228, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &cam_cc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *cam_cc_sm8450_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, + [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, + [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, + [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, + [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, + [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL7] = &cam_cc_pll7.clkr, + [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr, + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, + [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, + [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, + [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static const struct qcom_reset_map cam_cc_sm8450_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_ICP_BCR] = { 0x13104 }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IFE_1_BCR] = { 0x12000 }, + [CAM_CC_IFE_2_BCR] = { 0x1204c }, + [CAM_CC_IPE_0_BCR] = { 0x10074 }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 }, + [CAM_CC_SBI_BCR] = { 0x100cc }, + [CAM_CC_SFE_0_BCR] = { 0x1304c }, + [CAM_CC_SFE_1_BCR] = { 0x13094 }, +}; + +static const struct regmap_config cam_cc_sm8450_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1601c, + .fast_io = true, +}; + +static struct gdsc titan_top_gdsc; + +static struct gdsc bps_gdsc = { + .gdscr = 0x10004, + .pd = { + .name = "bps_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ipe_0_gdsc = { + .gdscr = 0x10078, + .pd = { + .name = "ipe_0_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc sbi_gdsc = { + .gdscr = 0x100d0, + .pd = { + .name = "sbi_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ife_0_gdsc = { + .gdscr = 0x11004, + .pd = { + .name = "ife_0_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ife_1_gdsc = { + .gdscr = 0x12004, + .pd = { + .name = "ife_1_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ife_2_gdsc = { + .gdscr = 0x12050, + .pd = { + .name = "ife_2_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc sfe_0_gdsc = { + .gdscr = 0x13050, + .pd = { + .name = "sfe_0_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc sfe_1_gdsc = { + .gdscr = 0x13098, + .pd = { + .name = "sfe_1_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc titan_top_gdsc = { + .gdscr = 0x131dc, + .pd = { + .name = "titan_top_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc *cam_cc_sm8450_gdscs[] = { + [BPS_GDSC] = &bps_gdsc, + [IPE_0_GDSC] = &ipe_0_gdsc, + [SBI_GDSC] = &sbi_gdsc, + [IFE_0_GDSC] = &ife_0_gdsc, + [IFE_1_GDSC] = &ife_1_gdsc, + [IFE_2_GDSC] = &ife_2_gdsc, + [SFE_0_GDSC] = &sfe_0_gdsc, + [SFE_1_GDSC] = &sfe_1_gdsc, + [TITAN_TOP_GDSC] = &titan_top_gdsc, +}; + +static const struct qcom_cc_desc cam_cc_sm8450_desc = { + .config = &cam_cc_sm8450_regmap_config, + .clks = cam_cc_sm8450_clocks, + .num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks), + .resets = cam_cc_sm8450_resets, + .num_resets = ARRAY_SIZE(cam_cc_sm8450_resets), + .gdscs = cam_cc_sm8450_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs), +}; + +static const struct of_device_id cam_cc_sm8450_match_table[] = { + { .compatible = "qcom,sm8450-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); + +static int cam_cc_sm8450_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); + clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); + clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + + return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap); +} + +static struct platform_driver cam_cc_sm8450_driver = { + .probe = cam_cc_sm8450_probe, + .driver = { + .name = "camcc-sm8450", + .of_match_table = cam_cc_sm8450_match_table, + }, +}; + +module_platform_driver(cam_cc_sm8450_driver); + +MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver"); +MODULE_LICENSE("GPL"); From 160758b05ab1679dae83c7facf312b60dd263308 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Wed, 6 Jul 2022 17:43:34 +0200 Subject: [PATCH 77/93] clk: qcom: add support for SM8350 GPUCC The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss Signed-off-by: Jonathan Marek Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f5e03350ea75..2a33e93996ef 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -720,6 +720,14 @@ config SM_GPUCC_8250 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_8350 + tristate "SM8350 Graphics Clock Controller" + select SM_GCC_8350 + help + Support for the graphics clock controller on SM8350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 7b52244c96ba..fbcf04073f07 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c new file mode 100644 index 000000000000..d13fa813d190 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-divider.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x18, + .alpha = 0x6000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2a9a699c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static const struct clk_parent_data gpu_cc_parent = { + .fw_name = "bi_tcxo", +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x1a, + .alpha = 0xaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2a9a699c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = lucid_5lpe_vco, + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &gpu_cc_parent, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + gpu_cc_parent, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x117c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x11c0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x11bc, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x1170, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1170, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_at_clk = { + .halt_reg = 0x1080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_at_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { + .halt_reg = 0x1094, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_trig_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { + .halt_reg = 0x1084, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk = { + .halt_reg = 0x120c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x120c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_freq_measure_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { + .halt_reg = 0x105c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x105c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_qdss_tsctr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk = { + .halt_reg = 0x1058, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_vsense_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x1178, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1178, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x1204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { + .halt_reg = 0x802c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x802c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_0_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { + .halt_reg = 0x8030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_mnd1x_1_gfx3d_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, +}; + +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, +}; + +static struct gdsc *gpu_cc_sm8350_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8030, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { + .config = &gpu_cc_sm8350_regmap_config, + .clks = gpu_cc_sm8350_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), + .resets = gpu_cc_sm8350_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), + .gdscs = gpu_cc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), +}; + +static int gpu_cc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); + return PTR_ERR(regmap); + } + + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); +} + +static const struct of_device_id gpu_cc_sm8350_match_table[] = { + { .compatible = "qcom,sm8350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); + +static struct platform_driver gpu_cc_sm8350_driver = { + .probe = gpu_cc_sm8350_probe, + .driver = { + .name = "sm8350-gpucc", + .of_match_table = gpu_cc_sm8350_match_table, + }, +}; + +static int __init gpu_cc_sm8350_init(void) +{ + return platform_driver_register(&gpu_cc_sm8350_driver); +} +subsys_initcall(gpu_cc_sm8350_init); + +static void __exit gpu_cc_sm8350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm8350_driver); +} +module_exit(gpu_cc_sm8350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); From 205737fe3345a41a57fbdb3fbd8409421d43e482 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Wed, 6 Jul 2022 17:43:36 +0200 Subject: [PATCH 78/93] clk: qcom: add support for SM8350 DISPCC Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org --- drivers/clk/qcom/Kconfig | 6 +-- drivers/clk/qcom/dispcc-sm8250.c | 63 +++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 2a33e93996ef..1cf1ef70e347 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -626,11 +626,11 @@ config SM_DISPCC_6125 splash screen config SM_DISPCC_8250 - tristate "SM8150 and SM8250 Display Clock Controller" - depends on SM_GCC_8150 || SM_GCC_8250 + tristate "SM8150/SM8250/SM8350 Display Clock Controller" + depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8150 and SM8250 devices. + SM8150/SM8250/SM8350 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index db9379634fb2..39b344ebb049 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { { 249600000, 2000000000, 0 }, }; +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + static struct alpha_pll_config disp_cc_pll0_config = { .l = 0x47, .alpha = 0xE000, @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { { .compatible = "qcom,sc8180x-dispcc" }, { .compatible = "qcom,sm8150-dispcc" }, { .compatible = "qcom,sm8250-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - /* note: trion == lucid, except for the prepare() op */ + /* Apply differences for SM8150 and SM8350 */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { @@ -1270,6 +1275,62 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { + static struct clk_rcg2 * const rcgs[] = { + &disp_cc_mdss_byte0_clk_src, + &disp_cc_mdss_byte1_clk_src, + &disp_cc_mdss_dp_aux1_clk_src, + &disp_cc_mdss_dp_aux_clk_src, + &disp_cc_mdss_dp_link1_clk_src, + &disp_cc_mdss_dp_link_clk_src, + &disp_cc_mdss_dp_pixel1_clk_src, + &disp_cc_mdss_dp_pixel2_clk_src, + &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_mdp_clk_src, + &disp_cc_mdss_pclk0_clk_src, + &disp_cc_mdss_pclk1_clk_src, + &disp_cc_mdss_rot_clk_src, + &disp_cc_mdss_vsync_clk_src, + }; + static struct clk_regmap_div * const divs[] = { + &disp_cc_mdss_byte0_div_clk_src, + &disp_cc_mdss_byte1_div_clk_src, + &disp_cc_mdss_dp_link1_div_clk_src, + &disp_cc_mdss_dp_link_div_clk_src, + }; + unsigned int i; + static bool offset_applied; + + /* + * note: trion == lucid, except for the prepare() op + * only apply the offsets once (in case of deferred probe) + */ + if (!offset_applied) { + for (i = 0; i < ARRAY_SIZE(rcgs); i++) + rcgs[i]->cmd_rcgr -= 4; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + divs[i]->reg -= 4; + divs[i]->width = 4; + } + + disp_cc_mdss_ahb_clk.halt_reg -= 4; + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; + + offset_applied = true; + } + + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table = lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table = lucid_5lpe_vco; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); From 2b4e75a7a7c8d3531a40ebb103b92f88ff693f79 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 20 Jun 2022 10:19:33 +0300 Subject: [PATCH 79/93] dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources Add additional GCC clock sources. This includes PCIe and USB PIPE and UFS symbol clocks. Fixes: 2a8aa18c1131 ("dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft") Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220620071936.1558906-2-dmitry.baryshkov@linaro.org --- .../bindings/clock/qcom,gcc-msm8996.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml index 5a5b2214f0ca..005e0edd4609 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -22,16 +22,32 @@ properties: const: qcom,gcc-msm8996 clocks: + minItems: 3 items: - description: XO source - description: Second XO source - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: PCIe 1 PIPE clock (optional) + - description: PCIe 2 PIPE clock (optional) + - description: USB3 PIPE clock (optional) + - description: UFS RX symbol 0 clock (optional) + - description: UFS RX symbol 1 clock (optional) + - description: UFS TX symbol 0 clock (optional) clock-names: + minItems: 3 items: - const: cxo - const: cxo2 - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: pcie_1_pipe_clk_src + - const: pcie_2_pipe_clk_src + - const: usb3_phy_pipe_clk_src + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src '#clock-cells': const: 1 From 6a3a6c7ae0ef235faebf66bac56384dbd5f944dc Mon Sep 17 00:00:00 2001 From: Cixi Geng Date: Thu, 5 May 2022 18:14:30 +0800 Subject: [PATCH 80/93] dt-bindings: clk: sprd: Add bindings for ums512 clock controller Add a new bindings to describe ums512 clock compatible string. Signed-off-by: Chunyan Zhang Signed-off-by: Cixi Geng Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220505101433.1575096-2-gengcixi@gmail.com Signed-off-by: Stephen Boyd --- .../bindings/clock/sprd,ums512-clk.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml new file mode 100644 index 000000000000..5f747b0471cf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Unisoc Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: UMS512 Soc clock controller + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +properties: + compatible: + enum: + - sprd,ums512-apahb-gate + - sprd,ums512-ap-clk + - sprd,ums512-aonapb-clk + - sprd,ums512-pmu-gate + - sprd,ums512-g0-pll + - sprd,ums512-g2-pll + - sprd,ums512-g3-pll + - sprd,ums512-gc-pll + - sprd,ums512-aon-gate + - sprd,ums512-audcpapb-gate + - sprd,ums512-audcpahb-gate + - sprd,ums512-gpu-clk + - sprd,ums512-mm-clk + - sprd,ums512-mm-gate-clk + - sprd,ums512-apapb-gate + + "#clock-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for the clock, only list + fixed clocks which are declared in devicetree. + + clock-names: + minItems: 1 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + ap_clk: clock-controller@20200000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0x20200000 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; +... From 8c18fece15f64df1d8101fd32efe304bf10032d5 Mon Sep 17 00:00:00 2001 From: Cixi Geng Date: Thu, 5 May 2022 18:14:32 +0800 Subject: [PATCH 81/93] clk: sprd: Add dt-bindings include file for UMS512 This file defines all UMS512 clock indexes, it should be included in the device tree in which there's device using the clocks. Signed-off-by: Cixi Geng Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220505101433.1575096-4-gengcixi@gmail.com Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/sprd,ums512-clk.h | 397 ++++++++++++++++++++ 1 file changed, 397 insertions(+) create mode 100644 include/dt-bindings/clock/sprd,ums512-clk.h diff --git a/include/dt-bindings/clock/sprd,ums512-clk.h b/include/dt-bindings/clock/sprd,ums512-clk.h new file mode 100644 index 000000000000..4f1d90849944 --- /dev/null +++ b/include/dt-bindings/clock/sprd,ums512-clk.h @@ -0,0 +1,397 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Unisoc UMS512 SoC DTS file + * + * Copyright (C) 2022, Unisoc Inc. + */ + +#ifndef _DT_BINDINGS_CLK_UMS512_H_ +#define _DT_BINDINGS_CLK_UMS512_H_ + +#define CLK_26M_AUD 0 +#define CLK_13M 1 +#define CLK_6M5 2 +#define CLK_4M3 3 +#define CLK_2M 4 +#define CLK_1M 5 +#define CLK_250K 6 +#define CLK_RCO_25M 7 +#define CLK_RCO_4M 8 +#define CLK_RCO_2M 9 +#define CLK_ISPPLL_GATE 10 +#define CLK_DPLL0_GATE 11 +#define CLK_DPLL1_GATE 12 +#define CLK_LPLL_GATE 13 +#define CLK_TWPLL_GATE 14 +#define CLK_GPLL_GATE 15 +#define CLK_RPLL_GATE 16 +#define CLK_CPPLL_GATE 17 +#define CLK_MPLL0_GATE 18 +#define CLK_MPLL1_GATE 19 +#define CLK_MPLL2_GATE 20 +#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1) + +#define CLK_DPLL0 0 +#define CLK_DPLL0_58M31 1 +#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1) + +#define CLK_MPLL1 0 +#define CLK_MPLL1_63M38 1 +#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1) + +#define CLK_RPLL 0 +#define CLK_AUDIO_GATE 1 +#define CLK_MPLL0 2 +#define CLK_MPLL0_56M88 3 +#define CLK_MPLL2 4 +#define CLK_MPLL2_47M13 5 +#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1) + +#define CLK_TWPLL 0 +#define CLK_TWPLL_768M 1 +#define CLK_TWPLL_384M 2 +#define CLK_TWPLL_192M 3 +#define CLK_TWPLL_96M 4 +#define CLK_TWPLL_48M 5 +#define CLK_TWPLL_24M 6 +#define CLK_TWPLL_12M 7 +#define CLK_TWPLL_512M 8 +#define CLK_TWPLL_256M 9 +#define CLK_TWPLL_128M 10 +#define CLK_TWPLL_64M 11 +#define CLK_TWPLL_307M2 12 +#define CLK_TWPLL_219M4 13 +#define CLK_TWPLL_170M6 14 +#define CLK_TWPLL_153M6 15 +#define CLK_TWPLL_76M8 16 +#define CLK_TWPLL_51M2 17 +#define CLK_TWPLL_38M4 18 +#define CLK_TWPLL_19M2 19 +#define CLK_TWPLL_12M29 20 +#define CLK_LPLL 21 +#define CLK_LPLL_614M4 22 +#define CLK_LPLL_409M6 23 +#define CLK_LPLL_245M76 24 +#define CLK_LPLL_30M72 25 +#define CLK_ISPPLL 26 +#define CLK_ISPPLL_468M 27 +#define CLK_ISPPLL_78M 28 +#define CLK_GPLL 29 +#define CLK_GPLL_40M 30 +#define CLK_CPPLL 31 +#define CLK_CPPLL_39M32 32 +#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1) + +#define CLK_AP_APB 0 +#define CLK_IPI 1 +#define CLK_AP_UART0 2 +#define CLK_AP_UART1 3 +#define CLK_AP_UART2 4 +#define CLK_AP_I2C0 5 +#define CLK_AP_I2C1 6 +#define CLK_AP_I2C2 7 +#define CLK_AP_I2C3 8 +#define CLK_AP_I2C4 9 +#define CLK_AP_SPI0 10 +#define CLK_AP_SPI1 11 +#define CLK_AP_SPI2 12 +#define CLK_AP_SPI3 13 +#define CLK_AP_IIS0 14 +#define CLK_AP_IIS1 15 +#define CLK_AP_IIS2 16 +#define CLK_AP_SIM 17 +#define CLK_AP_CE 18 +#define CLK_SDIO0_2X 19 +#define CLK_SDIO1_2X 20 +#define CLK_EMMC_2X 21 +#define CLK_VSP 22 +#define CLK_DISPC0 23 +#define CLK_DISPC0_DPI 24 +#define CLK_DSI_APB 25 +#define CLK_DSI_RXESC 26 +#define CLK_DSI_LANEBYTE 27 +#define CLK_VDSP 28 +#define CLK_VDSP_M 29 +#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1) + +#define CLK_DSI_EB 0 +#define CLK_DISPC_EB 1 +#define CLK_VSP_EB 2 +#define CLK_VDMA_EB 3 +#define CLK_DMA_PUB_EB 4 +#define CLK_DMA_SEC_EB 5 +#define CLK_IPI_EB 6 +#define CLK_AHB_CKG_EB 7 +#define CLK_BM_CLK_EB 8 +#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1) + +#define CLK_AON_APB 0 +#define CLK_ADI 1 +#define CLK_AUX0 2 +#define CLK_AUX1 3 +#define CLK_AUX2 4 +#define CLK_PROBE 5 +#define CLK_PWM0 6 +#define CLK_PWM1 7 +#define CLK_PWM2 8 +#define CLK_PWM3 9 +#define CLK_EFUSE 10 +#define CLK_UART0 11 +#define CLK_UART1 12 +#define CLK_THM0 13 +#define CLK_THM1 14 +#define CLK_THM2 15 +#define CLK_THM3 16 +#define CLK_AON_I2C 17 +#define CLK_AON_IIS 18 +#define CLK_SCC 19 +#define CLK_APCPU_DAP 20 +#define CLK_APCPU_DAP_MTCK 21 +#define CLK_APCPU_TS 22 +#define CLK_DEBUG_TS 23 +#define CLK_DSI_TEST_S 24 +#define CLK_DJTAG_TCK 25 +#define CLK_DJTAG_TCK_HW 26 +#define CLK_AON_TMR 27 +#define CLK_AON_PMU 28 +#define CLK_DEBOUNCE 29 +#define CLK_APCPU_PMU 30 +#define CLK_TOP_DVFS 31 +#define CLK_OTG_UTMI 32 +#define CLK_OTG_REF 33 +#define CLK_CSSYS 34 +#define CLK_CSSYS_PUB 35 +#define CLK_CSSYS_APB 36 +#define CLK_AP_AXI 37 +#define CLK_AP_MM 38 +#define CLK_SDIO2_2X 39 +#define CLK_ANALOG_IO_APB 40 +#define CLK_DMC_REF_CLK 41 +#define CLK_EMC 42 +#define CLK_USB 43 +#define CLK_26M_PMU 44 +#define CLK_AON_APB_NUM (CLK_26M_PMU + 1) + +#define CLK_MM_AHB 0 +#define CLK_MM_MTX 1 +#define CLK_SENSOR0 2 +#define CLK_SENSOR1 3 +#define CLK_SENSOR2 4 +#define CLK_CPP 5 +#define CLK_JPG 6 +#define CLK_FD 7 +#define CLK_DCAM_IF 8 +#define CLK_DCAM_AXI 9 +#define CLK_ISP 10 +#define CLK_MIPI_CSI0 11 +#define CLK_MIPI_CSI1 12 +#define CLK_MIPI_CSI2 13 +#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1) + +#define CLK_RC100M_CAL_EB 0 +#define CLK_DJTAG_TCK_EB 1 +#define CLK_DJTAG_EB 2 +#define CLK_AUX0_EB 3 +#define CLK_AUX1_EB 4 +#define CLK_AUX2_EB 5 +#define CLK_PROBE_EB 6 +#define CLK_MM_EB 7 +#define CLK_GPU_EB 8 +#define CLK_MSPI_EB 9 +#define CLK_APCPU_DAP_EB 10 +#define CLK_AON_CSSYS_EB 11 +#define CLK_CSSYS_APB_EB 12 +#define CLK_CSSYS_PUB_EB 13 +#define CLK_SDPHY_CFG_EB 14 +#define CLK_SDPHY_REF_EB 15 +#define CLK_EFUSE_EB 16 +#define CLK_GPIO_EB 17 +#define CLK_MBOX_EB 18 +#define CLK_KPD_EB 19 +#define CLK_AON_SYST_EB 20 +#define CLK_AP_SYST_EB 21 +#define CLK_AON_TMR_EB 22 +#define CLK_OTG_UTMI_EB 23 +#define CLK_OTG_PHY_EB 24 +#define CLK_SPLK_EB 25 +#define CLK_PIN_EB 26 +#define CLK_ANA_EB 27 +#define CLK_APCPU_TS0_EB 28 +#define CLK_APB_BUSMON_EB 29 +#define CLK_AON_IIS_EB 30 +#define CLK_SCC_EB 31 +#define CLK_THM0_EB 32 +#define CLK_THM1_EB 33 +#define CLK_THM2_EB 34 +#define CLK_ASIM_TOP_EB 35 +#define CLK_I2C_EB 36 +#define CLK_PMU_EB 37 +#define CLK_ADI_EB 38 +#define CLK_EIC_EB 39 +#define CLK_AP_INTC0_EB 40 +#define CLK_AP_INTC1_EB 41 +#define CLK_AP_INTC2_EB 42 +#define CLK_AP_INTC3_EB 43 +#define CLK_AP_INTC4_EB 44 +#define CLK_AP_INTC5_EB 45 +#define CLK_AUDCP_INTC_EB 46 +#define CLK_AP_TMR0_EB 47 +#define CLK_AP_TMR1_EB 48 +#define CLK_AP_TMR2_EB 49 +#define CLK_PWM0_EB 50 +#define CLK_PWM1_EB 51 +#define CLK_PWM2_EB 52 +#define CLK_PWM3_EB 53 +#define CLK_AP_WDG_EB 54 +#define CLK_APCPU_WDG_EB 55 +#define CLK_SERDES_EB 56 +#define CLK_ARCH_RTC_EB 57 +#define CLK_KPD_RTC_EB 58 +#define CLK_AON_SYST_RTC_EB 59 +#define CLK_AP_SYST_RTC_EB 60 +#define CLK_AON_TMR_RTC_EB 61 +#define CLK_EIC_RTC_EB 62 +#define CLK_EIC_RTCDV5_EB 63 +#define CLK_AP_WDG_RTC_EB 64 +#define CLK_AC_WDG_RTC_EB 65 +#define CLK_AP_TMR0_RTC_EB 66 +#define CLK_AP_TMR1_RTC_EB 67 +#define CLK_AP_TMR2_RTC_EB 68 +#define CLK_DCXO_LC_RTC_EB 69 +#define CLK_BB_CAL_RTC_EB 70 +#define CLK_AP_EMMC_RTC_EB 71 +#define CLK_AP_SDIO0_RTC_EB 72 +#define CLK_AP_SDIO1_RTC_EB 73 +#define CLK_AP_SDIO2_RTC_EB 74 +#define CLK_DSI_CSI_TEST_EB 75 +#define CLK_DJTAG_TCK_EN 76 +#define CLK_DPHY_REF_EB 77 +#define CLK_DMC_REF_EB 78 +#define CLK_OTG_REF_EB 79 +#define CLK_TSEN_EB 80 +#define CLK_TMR_EB 81 +#define CLK_RC100M_REF_EB 82 +#define CLK_RC100M_FDK_EB 83 +#define CLK_DEBOUNCE_EB 84 +#define CLK_DET_32K_EB 85 +#define CLK_TOP_CSSYS_EB 86 +#define CLK_AP_AXI_EN 87 +#define CLK_SDIO0_2X_EN 88 +#define CLK_SDIO0_1X_EN 89 +#define CLK_SDIO1_2X_EN 90 +#define CLK_SDIO1_1X_EN 91 +#define CLK_SDIO2_2X_EN 92 +#define CLK_SDIO2_1X_EN 93 +#define CLK_EMMC_2X_EN 94 +#define CLK_EMMC_1X_EN 95 +#define CLK_PLL_TEST_EN 96 +#define CLK_CPHY_CFG_EN 97 +#define CLK_DEBUG_TS_EN 98 +#define CLK_ACCESS_AUD_EN 99 +#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1) + +#define CLK_MM_CPP_EB 0 +#define CLK_MM_JPG_EB 1 +#define CLK_MM_DCAM_EB 2 +#define CLK_MM_ISP_EB 3 +#define CLK_MM_CSI2_EB 4 +#define CLK_MM_CSI1_EB 5 +#define CLK_MM_CSI0_EB 6 +#define CLK_MM_CKG_EB 7 +#define CLK_ISP_AHB_EB 8 +#define CLK_MM_DVFS_EB 9 +#define CLK_MM_FD_EB 10 +#define CLK_MM_SENSOR2_EB 11 +#define CLK_MM_SENSOR1_EB 12 +#define CLK_MM_SENSOR0_EB 13 +#define CLK_MM_MIPI_CSI2_EB 14 +#define CLK_MM_MIPI_CSI1_EB 15 +#define CLK_MM_MIPI_CSI0_EB 16 +#define CLK_DCAM_AXI_EB 17 +#define CLK_ISP_AXI_EB 18 +#define CLK_MM_CPHY_EB 19 +#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1) + +#define CLK_SIM0_EB 0 +#define CLK_IIS0_EB 1 +#define CLK_IIS1_EB 2 +#define CLK_IIS2_EB 3 +#define CLK_APB_REG_EB 4 +#define CLK_SPI0_EB 5 +#define CLK_SPI1_EB 6 +#define CLK_SPI2_EB 7 +#define CLK_SPI3_EB 8 +#define CLK_I2C0_EB 9 +#define CLK_I2C1_EB 10 +#define CLK_I2C2_EB 11 +#define CLK_I2C3_EB 12 +#define CLK_I2C4_EB 13 +#define CLK_UART0_EB 14 +#define CLK_UART1_EB 15 +#define CLK_UART2_EB 16 +#define CLK_SIM0_32K_EB 17 +#define CLK_SPI0_LFIN_EB 18 +#define CLK_SPI1_LFIN_EB 19 +#define CLK_SPI2_LFIN_EB 20 +#define CLK_SPI3_LFIN_EB 21 +#define CLK_SDIO0_EB 22 +#define CLK_SDIO1_EB 23 +#define CLK_SDIO2_EB 24 +#define CLK_EMMC_EB 25 +#define CLK_SDIO0_32K_EB 26 +#define CLK_SDIO1_32K_EB 27 +#define CLK_SDIO2_32K_EB 28 +#define CLK_EMMC_32K_EB 29 +#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1) + +#define CLK_GPU_CORE_EB 0 +#define CLK_GPU_CORE 1 +#define CLK_GPU_MEM_EB 2 +#define CLK_GPU_MEM 3 +#define CLK_GPU_SYS_EB 4 +#define CLK_GPU_SYS 5 +#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1) + +#define CLK_AUDCP_IIS0_EB 0 +#define CLK_AUDCP_IIS1_EB 1 +#define CLK_AUDCP_IIS2_EB 2 +#define CLK_AUDCP_UART_EB 3 +#define CLK_AUDCP_DMA_CP_EB 4 +#define CLK_AUDCP_DMA_AP_EB 5 +#define CLK_AUDCP_SRC48K_EB 6 +#define CLK_AUDCP_MCDT_EB 7 +#define CLK_AUDCP_VBCIFD_EB 8 +#define CLK_AUDCP_VBC_EB 9 +#define CLK_AUDCP_SPLK_EB 10 +#define CLK_AUDCP_ICU_EB 11 +#define CLK_AUDCP_DMA_AP_ASHB_EB 12 +#define CLK_AUDCP_DMA_CP_ASHB_EB 13 +#define CLK_AUDCP_AUD_EB 14 +#define CLK_AUDCP_VBC_24M_EB 15 +#define CLK_AUDCP_TMR_26M_EB 16 +#define CLK_AUDCP_DVFS_ASHB_EB 17 +#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1) + +#define CLK_AUDCP_WDG_EB 0 +#define CLK_AUDCP_RTC_WDG_EB 1 +#define CLK_AUDCP_TMR0_EB 2 +#define CLK_AUDCP_TMR1_EB 3 +#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1) + +#define CLK_ACORE0 0 +#define CLK_ACORE1 1 +#define CLK_ACORE2 2 +#define CLK_ACORE3 3 +#define CLK_ACORE4 4 +#define CLK_ACORE5 5 +#define CLK_PCORE0 6 +#define CLK_PCORE1 7 +#define CLK_SCU 8 +#define CLK_ACE 9 +#define CLK_PERIPH 10 +#define CLK_GIC 11 +#define CLK_ATB 12 +#define CLK_DEBUG_APB 13 +#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1) + +#endif /* _DT_BINDINGS_CLK_UMS512_H_ */ From b5eb8cde863cdf455436c7ba3fb7362c49e1e64e Mon Sep 17 00:00:00 2001 From: Ren Zhijie Date: Thu, 14 Jul 2022 20:11:44 +0800 Subject: [PATCH 82/93] clk: qcom: fix build error initializer element is not constant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CONFIG_CC_VERSION_TEXT="x86_64-linux-gnu-gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0" make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this: drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not constant gpu_cc_parent, ^~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm8350.c:111:2: note: (near initialization for ‘gpu_cc_parent_data_0[0]’) drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not constant gpu_cc_parent, ^~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm8350.c:126:2: note: (near initialization for ‘gpu_cc_parent_data_1[0]’) make[3]: *** [drivers/clk/qcom/gpucc-sm8350.o] Error 1 It seems that nested constant initializer is not supported in GCC 7.4.0. For portability resons, we should fix it. Reported-by: Hulk Robot Fixes: 160758b05ab1 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by: Ren Zhijie Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220714121144.71062-1-renzhijie2@huawei.com --- drivers/clk/qcom/gpucc-sm8350.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c index d13fa813d190..5367ce654ac9 100644 --- a/drivers/clk/qcom/gpucc-sm8350.c +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -108,7 +108,7 @@ static const struct parent_map gpu_cc_parent_map_0[] = { }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { - gpu_cc_parent, + { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll0.clkr.hw }, { .hw = &gpu_cc_pll1.clkr.hw }, { .fw_name = "gcc_gpu_gpll0_clk_src" }, @@ -123,7 +123,7 @@ static const struct parent_map gpu_cc_parent_map_1[] = { }; static const struct clk_parent_data gpu_cc_parent_data_1[] = { - gpu_cc_parent, + { .fw_name = "bi_tcxo" }, { .hw = &gpu_cc_pll1.clkr.hw }, { .fw_name = "gcc_gpu_gpll0_clk_src" }, { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, From b1ec8b53c9ae5fae33d60e9638d39ca5346b941b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 13 Jul 2022 17:32:00 +0300 Subject: [PATCH 83/93] clk: qcom: Drop mmcx gdsc supply for dispcc and videocc Both dispcc and videocc use mmcx power domain now. Lets drop the supply mmcx from every gdsc. Cc: Dmitry Baryshkov Fixes: 266e5cf39a0f ("arm64: dts: qcom: sm8250: remove mmcx regulator") Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org --- drivers/clk/qcom/dispcc-sm8250.c | 1 - drivers/clk/qcom/videocc-sm8250.c | 4 ---- 2 files changed, 5 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 39b344ebb049..709076f0f9d7 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1138,7 +1138,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 8617454e4a77..f28f2cb051d7 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -277,7 +277,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -287,7 +286,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -297,7 +295,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -307,7 +304,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = { From 41fff779d7948147f2440c4bb134cdf8b45b22d7 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 13 Jul 2022 14:28:18 -0700 Subject: [PATCH 84/93] clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled When a GDSC is found to be enabled at boot the pm_runtime state will be unbalanced as the GDSC is later turned off. Fix this by increasing the usage counter on the power-domain, in line with how we handled the regulator state. Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support") Signed-off-by: Bjorn Andersson Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220713212818.130277-1-bjorn.andersson@linaro.org --- drivers/clk/qcom/gdsc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 6f746158d28f..d3244006c661 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -437,6 +437,14 @@ static int gdsc_init(struct gdsc *sc) return ret; } + /* ...and the power-domain */ + ret = gdsc_pm_runtime_get(sc); + if (ret) { + if (sc->rsupply) + regulator_disable(sc->rsupply); + return ret; + } + /* * Votable GDSCs can be ON due to Vote from other masters. * If a Votable GDSC is ON, make sure we have a Vote. From 2bc308ebc453ba22f3f120f777b9ac48f973ee80 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:17 +0100 Subject: [PATCH 85/93] clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk Adding a new item to this frequency table I see the existing indentation is incorrect. Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-2-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index c7377ec0f423..de0022e5450d 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1014,7 +1014,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { }; static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { - F(19200000, P_XO, 1, 0, 0), + F(19200000, P_XO, 1, 0, 0), { } }; From 159b2f59d65b4d34e225ef8d96ed290a13610d9c Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:18 +0100 Subject: [PATCH 86/93] clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define the 19.2 MHz but are missing the 37.5 MHz. See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[] Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-3-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index de0022e5450d..0c6c3a79d652 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1015,6 +1015,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0, 1, 3, 64), { } }; From 680b86da10a23268b24d65b567830824075eb151 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:19 +0100 Subject: [PATCH 87/93] clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions The Venus clock frequencies are a copy/paste error from msm8916. Looking at the original clock-gcc-8936.c ftbl_gcc_venus0_vcodec0_clk defines we have: - 133 MHz - 200 MHz - 266 MHz These values are born out by the relevant qualcomm documentation for the msm8936/msm8939 Venus core performance levels. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-4-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 0c6c3a79d652..6955f8669966 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1836,9 +1836,9 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { }; static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { - F(100000000, P_GPLL0, 8, 0, 0), - F(160000000, P_GPLL0, 5, 0, 0), - F(228570000, P_GPLL0, 3.5, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), { } }; From 2c37d70c82e826e44163ab2c83f8b7b81e7db35a Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:20 +0100 Subject: [PATCH 88/93] clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies Reviewing the qcom msm8936.c clock frequency tables we see static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = { F( 160000000, gpll0_out_main, 5, 0, 0), F( 200000000, gpll0_out_main, 4, 0, 0), F( 228570000, gpll0_out_main, 3.5, 0, 0), F( 266670000, gpll0_out_main, 3, 0, 0), F( 320000000, gpll0_out_main, 2.5, 0, 0), F( 465000000, gpll2_out_main, 2, 0, 0), F_END }; which is a super-set of the msm8916 original definitions. Add in the missing frequency definitions now. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-5-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 6955f8669966..8b8eb46cd159 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1155,6 +1155,9 @@ static struct clk_rcg2 csi1phytimer_clk_src = { static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), F(320000000, P_GPLL0, 2.5, 0, 0), F(465000000, P_GPLL2, 2, 0, 0), { } From 2573f7d8629afc1d2c5f841b8a2b2359396a5e77 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:21 +0100 Subject: [PATCH 89/93] clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies Again the msm8936/msm8939 supports a wider range of operating frequencies to the antecedent msm8916 from which the msm8939.c driver is derived. static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = { F( 50000000, gpll0_out_aux, 16, 0, 0), F( 80000000, gpll0_out_aux, 10, 0, 0), F( 100000000, gpll0_out_aux, 8, 0, 0), F( 145500000, gpll0_out_aux, 5.5, 0, 0), F( 153600000, gpll1_out_main, 4, 0, 0), F( 160000000, gpll0_out_aux, 5, 0, 0), F( 177780000, gpll0_out_aux, 4.5, 0, 0), F( 200000000, gpll0_out_aux, 4, 0, 0), F( 266670000, gpll0_out_aux, 3, 0, 0), F( 307200000, gpll1_out_main, 2, 0, 0), F( 366670000, gpll3_out_aux, 3, 0, 0), F_END }; We are missing 145.5 MHz and 153.6 MHz. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-6-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 8b8eb46cd159..75a7b20d4499 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1306,6 +1306,8 @@ static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { F(50000000, P_GPLL0_AUX, 16, 0, 0), F(80000000, P_GPLL0_AUX, 10, 0, 0), F(100000000, P_GPLL0_AUX, 8, 0, 0), + F(145500000, P_GPLL0_AUX, 5.5, 0, 0), + F(153600000, P_GPLL0, 4, 0, 0), F(160000000, P_GPLL0_AUX, 5, 0, 0), F(177780000, P_GPLL0_AUX, 4.5, 0, 0), F(200000000, P_GPLL0_AUX, 4, 0, 0), From 873b98538491feb0b0548ea1a8ee054fcfe0d435 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Jul 2022 13:59:22 +0100 Subject: [PATCH 90/93] clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies The shipped qcom driver defines: static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { F( 57140000, gpll0_out_main, 14, 0, 0), F( 80000000, gpll0_out_main, 10, 0, 0), F( 100000000, gpll0_out_main, 8, 0, 0), F_END }; In the upstream code we omit 57.14 MHz and 100 MHz. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220712125922.3461675-7-bryan.odonoghue@linaro.org --- drivers/clk/qcom/gcc-msm8939.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 75a7b20d4499..8e2d9fb98ad5 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1480,7 +1480,9 @@ static struct clk_rcg2 bimc_gpu_clk_src = { }; static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { + F(57140000, P_GPLL0, 14, 0, 0), F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), { } }; From 4970f3139d42d183f0d81319d6ce58d3634e7c87 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 7 Jul 2022 00:53:18 +0200 Subject: [PATCH 91/93] dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc qcom,rpmcc describe 2 different kind of device. Currently we have definition for rpm-smd based device but we lack Documentation for simple rpm based device. Add the missing clk for ipq806x, apq8060, msm8660 and apq8064 and provide additional example to describe these new simple rpm based devices. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706225321.26215-2-ansuelsmth@gmail.com --- .../devicetree/bindings/clock/qcom,rpmcc.yaml | 85 ++++++++++++++++++- 1 file changed, 83 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml index 9d296b89a8d0..d63b45ad06e8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -49,15 +49,86 @@ properties: const: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: xo + minItems: 1 + maxItems: 2 required: - compatible - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-msm8660 + + then: + properties: + clocks: + items: + - description: pxo clock + + clock-names: + items: + - const: pxo + + - if: + properties: + compatible: + contains: + const: qcom,rpmcc-apq8064 + then: + properties: + clocks: + items: + - description: pxo clock + - description: cxo clock + + clock-names: + items: + - const: pxo + - const: cxo + + - if: + properties: + compatible: + contains: + enum: + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + + then: + properties: + clocks: + items: + - description: xo clock + + clock-names: + items: + - const: xo + additionalProperties: false examples: @@ -73,3 +144,13 @@ examples: }; }; }; + + - | + rpm { + clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; + }; + }; From 129d9cd9c25041f8b8681fd6e8584fa47c385f3b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 7 Jul 2022 00:53:20 +0200 Subject: [PATCH 92/93] clk: qcom: clk-rpm: convert to parent_data API Convert clk-rpm driver to parent_data API. We keep the old pxo/cxo_board parent naming to keep compatibility with old DT and we use the new pxo/cxo for new implementation where these clock are defined in DTS. Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index a18811c38018..747c473b0b5e 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -23,6 +23,14 @@ #define QCOM_RPM_SCALING_ENABLE_ID 0x2 #define QCOM_RPM_XO_MODE_ON 0x2 +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name = "pxo", .name = "pxo_board" }, +}; + +static const struct clk_parent_data gcc_cxo[] = { + { .fw_name = "cxo", .name = "cxo_board" }, +}; + #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ static struct clk_rpm _platform##_##_active; \ static struct clk_rpm _platform##_##_name = { \ @@ -32,8 +40,8 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ .name = #_name, \ - .parent_names = (const char *[]){ "pxo_board" }, \ - .num_parents = 1, \ + .parent_data = gcc_pxo, \ + .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ }; \ static struct clk_rpm _platform##_##_active = { \ @@ -44,8 +52,8 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_ops, \ .name = #_active, \ - .parent_names = (const char *[]){ "pxo_board" }, \ - .num_parents = 1, \ + .parent_data = gcc_pxo, \ + .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ } @@ -56,8 +64,8 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_xo_ops, \ .name = #_name, \ - .parent_names = (const char *[]){ "cxo_board" }, \ - .num_parents = 1, \ + .parent_data = gcc_cxo, \ + .num_parents = ARRAY_SIZE(gcc_cxo), \ }, \ } @@ -68,8 +76,8 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_rpm_fixed_ops, \ .name = #_name, \ - .parent_names = (const char *[]){ "pxo" }, \ - .num_parents = 1, \ + .parent_data = gcc_pxo, \ + .num_parents = ARRAY_SIZE(gcc_pxo), \ }, \ } From 5e1e12d2992006a4e950ebf2e2a1f0ebaabd969f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 20 Jun 2022 11:05:05 +0300 Subject: [PATCH 93/93] clk: qcom: gcc-msm8994: use parent_hws for gpll0/4 Use parent_hws for two remaining clocks in gcc-msm8994 that used parent_names. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220620080505.1573948-1-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8994.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 6b702cdacbf2..0f52c48e89d8 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -52,7 +52,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]) { "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -81,7 +83,9 @@ static struct clk_alpha_pll_postdiv gpll4 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", - .parent_names = (const char *[]) { "gpll4_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll4_early.clkr.hw + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, },