Merge branch 'mediatek-pdma-rx'
Nelson Chang says: ==================== net: ethernet: mediatek: modify to use the PDMA for Ethernet RX This series have some modifications and refines to support Ethernet RX by the PDMA. changes since v4: - Remove the redundant OR operation in mtk_hw_init() changes since v3: - Add GDM hardware settings to send packets to PDMA for RX changes since v2: - Fix the bugs of PDMA cpu index and interrupt settings in mtk_poll_rx() changes since v1: - Modify to use the PDMA instead of the QDMA for Ethernet RX ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
e0424b616b
@ -342,25 +342,27 @@ static void mtk_mdio_cleanup(struct mtk_eth *eth)
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mdiobus_free(eth->mii_bus);
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}
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static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
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static inline void mtk_irq_disable(struct mtk_eth *eth,
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unsigned reg, u32 mask)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(ð->irq_lock, flags);
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val = mtk_r32(eth, MTK_QDMA_INT_MASK);
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mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
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val = mtk_r32(eth, reg);
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mtk_w32(eth, val & ~mask, reg);
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spin_unlock_irqrestore(ð->irq_lock, flags);
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}
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static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
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static inline void mtk_irq_enable(struct mtk_eth *eth,
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unsigned reg, u32 mask)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(ð->irq_lock, flags);
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val = mtk_r32(eth, MTK_QDMA_INT_MASK);
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mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
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val = mtk_r32(eth, reg);
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mtk_w32(eth, val | mask, reg);
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spin_unlock_irqrestore(ð->irq_lock, flags);
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}
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@ -897,12 +899,12 @@ release_desc:
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* we continue
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*/
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wmb();
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mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
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mtk_w32(eth, ring->calc_idx, MTK_PRX_CRX_IDX0);
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done++;
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}
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if (done < budget)
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
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return done;
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}
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@ -1012,7 +1014,7 @@ static int mtk_napi_tx(struct napi_struct *napi, int budget)
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return budget;
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napi_complete(napi);
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mtk_irq_enable(eth, MTK_TX_DONE_INT);
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mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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return tx_done;
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}
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@ -1024,12 +1026,12 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
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int rx_done = 0;
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mtk_handle_status_irq(eth);
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
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rx_done = mtk_poll_rx(napi, budget, eth);
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if (unlikely(netif_msg_intr(eth))) {
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status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
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status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
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mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
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dev_info(eth->dev,
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"done rx %d, intr 0x%08x/0x%x\n",
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rx_done, status, mask);
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@ -1038,12 +1040,12 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
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if (rx_done == budget)
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return budget;
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status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
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status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
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if (status & MTK_RX_DONE_INT)
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return budget;
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napi_complete(napi);
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mtk_irq_enable(eth, MTK_RX_DONE_INT);
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mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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return rx_done;
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}
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@ -1092,6 +1094,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
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mtk_w32(eth,
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ring->phys + ((MTK_DMA_SIZE - 1) * sz),
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MTK_QTX_DRX_PTR);
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mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
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return 0;
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@ -1162,11 +1165,10 @@ static int mtk_rx_alloc(struct mtk_eth *eth)
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*/
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wmb();
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mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
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mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
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mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
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mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
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mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
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mtk_w32(eth, eth->rx_ring.phys, MTK_PRX_BASE_PTR0);
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mtk_w32(eth, MTK_DMA_SIZE, MTK_PRX_MAX_CNT0);
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mtk_w32(eth, eth->rx_ring.calc_idx, MTK_PRX_CRX_IDX0);
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mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_PDMA_RST_IDX);
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return 0;
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}
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@ -1285,7 +1287,7 @@ static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
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if (likely(napi_schedule_prep(ð->rx_napi))) {
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__napi_schedule(ð->rx_napi);
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mtk_irq_disable(eth, MTK_RX_DONE_INT);
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mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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}
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return IRQ_HANDLED;
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@ -1297,7 +1299,7 @@ static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
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if (likely(napi_schedule_prep(ð->tx_napi))) {
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__napi_schedule(ð->tx_napi);
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mtk_irq_disable(eth, MTK_TX_DONE_INT);
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mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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}
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return IRQ_HANDLED;
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@ -1308,11 +1310,12 @@ static void mtk_poll_controller(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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struct mtk_eth *eth = mac->hw;
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u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
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mtk_irq_disable(eth, int_mask);
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mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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mtk_handle_irq_rx(eth->irq[2], dev);
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mtk_irq_enable(eth, int_mask);
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mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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}
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#endif
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@ -1327,11 +1330,15 @@ static int mtk_start_dma(struct mtk_eth *eth)
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}
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mtk_w32(eth,
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MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
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MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
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MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
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MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
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MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
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MTK_QDMA_GLO_CFG);
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mtk_w32(eth,
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MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
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MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
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MTK_PDMA_GLO_CFG);
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return 0;
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}
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@ -1349,7 +1356,8 @@ static int mtk_open(struct net_device *dev)
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
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mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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}
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atomic_inc(ð->dma_refcnt);
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@ -1394,7 +1402,8 @@ static int mtk_stop(struct net_device *dev)
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if (!atomic_dec_and_test(ð->dma_refcnt))
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return 0;
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mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
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mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
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mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
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napi_disable(ð->tx_napi);
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napi_disable(ð->rx_napi);
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@ -1448,7 +1457,9 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
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/* disable delay and normal interrupt */
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mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
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mtk_irq_disable(eth, ~0);
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mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
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mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
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mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
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mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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mtk_w32(eth, 0, MTK_RST_GL);
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@ -1462,9 +1473,8 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
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for (i = 0; i < 2; i++) {
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u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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/* setup the forward port to send frame to QDMA */
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/* setup the forward port to send frame to PDMA */
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val &= ~0xffff;
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val |= 0x5555;
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/* Enable RX checksum */
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val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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@ -1504,7 +1514,8 @@ static void mtk_uninit(struct net_device *dev)
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phy_disconnect(mac->phy_dev);
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mtk_mdio_cleanup(eth);
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mtk_irq_disable(eth, ~0);
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mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
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mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
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free_irq(eth->irq[1], dev);
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free_irq(eth->irq[2], dev);
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}
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@ -1683,7 +1694,7 @@ static void mtk_get_ethtool_stats(struct net_device *dev,
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}
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do {
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data_src = (u64*)hwstats;
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data_src = (u64 *)hwstats;
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data_dst = data;
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start = u64_stats_fetch_begin_irq(&hwstats->syncp);
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@ -68,6 +68,32 @@
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/* Unicast Filter MAC Address Register - High */
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#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
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/* PDMA RX Base Pointer Register */
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#define MTK_PRX_BASE_PTR0 0x900
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/* PDMA RX Maximum Count Register */
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#define MTK_PRX_MAX_CNT0 0x904
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/* PDMA RX CPU Pointer Register */
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#define MTK_PRX_CRX_IDX0 0x908
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/* PDMA Global Configuration Register */
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#define MTK_PDMA_GLO_CFG 0xa04
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#define MTK_MULTI_EN BIT(10)
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/* PDMA Reset Index Register */
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#define MTK_PDMA_RST_IDX 0xa08
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#define MTK_PST_DRX_IDX0 BIT(16)
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/* PDMA Delay Interrupt Register */
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#define MTK_PDMA_DELAY_INT 0xa0c
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/* PDMA Interrupt Status Register */
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#define MTK_PDMA_INT_STATUS 0xa20
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/* PDMA Interrupt Mask Register */
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#define MTK_PDMA_INT_MASK 0xa28
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/* PDMA Interrupt grouping registers */
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#define MTK_PDMA_INT_GRP1 0xa50
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#define MTK_PDMA_INT_GRP2 0xa54
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@ -119,13 +145,16 @@
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/* QDMA Interrupt Status Register */
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#define MTK_QMTK_INT_STATUS 0x1A18
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#define MTK_RX_DONE_INT3 BIT(19)
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#define MTK_RX_DONE_INT2 BIT(18)
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#define MTK_RX_DONE_INT1 BIT(17)
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#define MTK_RX_DONE_INT0 BIT(16)
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#define MTK_TX_DONE_INT3 BIT(3)
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#define MTK_TX_DONE_INT2 BIT(2)
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#define MTK_TX_DONE_INT1 BIT(1)
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#define MTK_TX_DONE_INT0 BIT(0)
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#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1)
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#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \
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MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3)
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#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
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MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
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