iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Amlogic clock headers updates for v5.11

Browse Source 
* Add axg's video clocks
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl+7bb4ACgkQ5vwPHDfy
 2oXPjA/9GU3khAkgiupKVOJHLuC1iIy2pQOAs7sQmgdk0BQ1tCviqLipazGdG/O/
 HHA7MhGB3PKdR9Q/YPAgGaD5/SDhfUCRnL/gVoP6OntDYaMuQS/k/X90XYrbGqm9
 e8VayudqxjMAWRt7x7RLy7+EttgFkso2IsjviiyfS0YTmWzbtQmTJ+BqCLlZHTqN
 R0nWKLEx8J8xSIO/BbnRMRDfjpeH+nM2ue1xlCv0j3atuColmAVR/jiFVRz3G6Gj
 8XlkowSCZfS3B1hW9Y4dkLo3Aknm48/rOSsmCxSXyy7IroEBwtiMxNiamGRfoQWY
 JYGYJPJwCakyf/TxerWX7myC9iCKM2buaGuF4u4Hn97kXANv7k6/1cjl9olWrajZ
 AEXmNFePnPy+Ah/dKMFtATH7L/7Vx38cqIPI/NC7ZxoV7uDarz2ZNNBLp24/nkk6
 AtAN0JI0Okhzmt8tXJ3Pd5aEPVCdi11zFl7gDreL5sy2f3WzqhXyjPB5qFxXIwmc
 t+LS1UQoBsqT69RAC4KPis1mBJCdLkrm1LtXr3/DRkO8Y5tn5mnYFp7SVK9d+gux
 2ni1AMu5bMAxz6Bxph4sT0srxCtoNAjSD+G3Soj55GKDqrNmViiqwsTih57SnTrX
 C1QYTEiOj4g8JrbE+AZ7pbf98hWxGQKlhDFB3Tl49A7kWhqKdVU=
 =4jn3
 -----END PGP SIGNATURE-----

Merge tag 'clk-meson-v5.11-headers-1' of git://github.com/BayLibre/clk-meson into v5.11/dt64-deps

Amlogic clock headers updates for v5.11

* Add axg's video clocks

* tag 'clk-meson-v5.11-headers-1' of git://github.com/BayLibre/clk-meson:
  dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding
  dt-bindings: clk: axg-clkc: add Video Clocks
This commit is contained in:
Kevin Hilman 2020-11-30 15:53:49 -08:00
commit e059eda7ee
1 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
include/dt-bindings/clock/axg-clkc.h
View File

@ -72,5 +72,30 @@
#define CLKID_PCIE_CML_EN1 80 #define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81 #define CLKID_MIPI_ENABLE 81
#define CLKID_GEN_CLK 84 #define CLKID_GEN_CLK 84
#define CLKID_VPU_0_SEL 92
#define CLKID_VPU_0 93
#define CLKID_VPU_1_SEL 95
#define CLKID_VPU_1 96
#define CLKID_VPU 97
#define CLKID_VAPB_0_SEL 99
#define CLKID_VAPB_0 100
#define CLKID_VAPB_1_SEL 102
#define CLKID_VAPB_1 103
#define CLKID_VAPB_SEL 104
#define CLKID_VAPB 105
#define CLKID_VCLK 106
#define CLKID_VCLK2 107
#define CLKID_VCLK_DIV1 122
#define CLKID_VCLK_DIV2 123
#define CLKID_VCLK_DIV4 124
#define CLKID_VCLK_DIV6 125
#define CLKID_VCLK_DIV12 126
#define CLKID_VCLK2_DIV1 127
#define CLKID_VCLK2_DIV2 128
#define CLKID_VCLK2_DIV4 129
#define CLKID_VCLK2_DIV6 130
#define CLKID_VCLK2_DIV12 131
#define CLKID_CTS_ENCL 133
#define CLKID_VDIN_MEAS 136
#endif /* __AXG_CLKC_H */ #endif /* __AXG_CLKC_H */