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Merge patch series "mpi3mr: Few Enhancements and minor fixes"

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Ranjan Kumar <ranjan.kumar@broadcom.com> says:

Few Enhancements and minor fixes of mpi3mr driver.

Link: https://lore.kernel.org/r/20230316110209.60145-1-ranjan.kumar@broadcom.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Martin K. Petersen 2023-03-16 23:55:19 -04:00
commit e05c006dac
13 changed files with 207 additions and 52 deletions
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112
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2017-2022 Broadcom Inc. All rights reserved.
* Copyright 2017-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_CNFG_H
#define MPI30_CNFG_H 1
@ -63,8 +63,9 @@
#define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff)
#define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000)
#define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000)
#define MPI3_SECURITY_PGAD_FORM_SOT_NUM (0x10000000)
#define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000)
#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00)
#define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8)
#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff)
struct mpi3_config_request {
__le16 host_tag;
@ -135,7 +136,6 @@ struct mpi3_config_page_header {
#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000)
#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000)
#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000)
#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0)
#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000)
#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000)
@ -201,6 +201,11 @@ struct mpi3_config_page_header {
#define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3)
#define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000)
#define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5)
#define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3)
#define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4)
#define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5)
#define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6)
#define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8)
struct mpi3_man_page0 {
struct mpi3_config_page_header header;
u8 chip_revision[8];
@ -466,7 +471,7 @@ struct mpi3_man_page9 {
#define MPI3_MAN9_PAGEVERSION (0x00)
struct mpi3_man10_istwi_ctrlr_entry {
__le16 slave_address;
__le16 target_address;
__le16 flags;
u8 scl_low_override;
u8 scl_high_override;
@ -476,8 +481,8 @@ struct mpi3_man10_istwi_ctrlr_entry {
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED (0x0002)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED (0x0001)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002)
#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001)
#ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
#define MPI3_MAN10_ISTWI_CTRLR_MAX (1)
#endif
@ -1160,7 +1165,7 @@ struct mpi3_io_unit_page12 {
struct mpi3_iounit13_allowed_function {
__le16 sub_function;
u8 function_code;
u8 fuction_flags;
u8 function_flags;
};
#define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04)
#define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02)
@ -1176,6 +1181,48 @@ struct mpi3_io_unit_page13 {
#define MPI3_IOUNIT13_PAGEVERSION (0x00)
#define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002)
#define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001)
#ifndef MPI3_IOUNIT14_MD_MAX
#define MPI3_IOUNIT14_MD_MAX (1)
#endif
struct mpi3_iounit14_pagemetadata {
u8 page_type;
u8 page_number;
u8 reserved02;
u8 page_flags;
};
#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02)
#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01)
struct mpi3_io_unit_page14 {
struct mpi3_config_page_header header;
u8 flags;
u8 reserved09[3];
u8 num_pages;
u8 reserved0d[3];
struct mpi3_iounit14_pagemetadata page_metadata[MPI3_IOUNIT14_MD_MAX];
};
#define MPI3_IOUNIT14_PAGEVERSION (0x00)
#define MPI3_IOUNIT14_FLAGS_READONLY (0x01)
#ifndef MPI3_IOUNIT15_PBD_MAX
#define MPI3_IOUNIT15_PBD_MAX (1)
#endif
struct mpi3_io_unit_page15 {
struct mpi3_config_page_header header;
u8 flags;
u8 reserved09[3];
__le32 reserved0c;
u8 power_budgeting_capability;
u8 reserved11[3];
u8 num_power_budget_data;
u8 reserved15[3];
__le32 power_budget_data[MPI3_IOUNIT15_PBD_MAX];
};
#define MPI3_IOUNIT15_PAGEVERSION (0x00)
#define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04)
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03)
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00)
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01)
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02)
#define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00)
struct mpi3_ioc_page0 {
struct mpi3_config_page_header header;
__le32 reserved08;
@ -1273,6 +1320,7 @@ struct mpi3_driver_page0 {
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003)
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000)
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001)
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002)
struct mpi3_driver_page1 {
struct mpi3_config_page_header header;
__le32 flags;
@ -1340,7 +1388,7 @@ union mpi3_driver2_trigger_element {
#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01)
struct mpi3_driver_page2 {
struct mpi3_config_page_header header;
__le64 master_trigger;
__le64 global_trigger;
__le32 reserved10[3];
u8 num_triggers;
u8 reserved1d[3];
@ -1348,11 +1396,13 @@ struct mpi3_driver_page2 {
};
#define MPI3_DRIVER2_PAGEVERSION (0x00)
#define MPI3_DRIVER2_MASTERTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL)
#define MPI3_DRIVER2_MASTERTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL)
#define MPI3_DRIVER2_MASTERTRIGGER_SNAPDUMP (0x2000000000000000ULL)
#define MPI3_DRIVER2_MASTERTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL)
#define MPI3_DRIVER2_MASTERTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL)
#define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL)
struct mpi3_driver_page10 {
struct mpi3_config_page_header header;
__le16 flags;
@ -1395,6 +1445,12 @@ union mpi3_security_nonce {
u8 byte[64];
};
union mpi3_security_root_digest {
__le32 dword[16];
__le16 word[32];
u8 byte[64];
};
union mpi3_security0_cert_chain {
__le32 dword[1024];
__le16 word[2048];
@ -1467,6 +1523,32 @@ struct mpi3_security_page1 {
};
#define MPI3_SECURITY1_PAGEVERSION (0x00)
#ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX
#define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1
#endif
struct mpi3_security2_trusted_root {
u8 level;
u8 hash_algorithm;
__le16 trusted_root_flags;
__le32 reserved04[3];
union mpi3_security_root_digest root_digest;
};
#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006)
#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1)
#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000)
#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002)
#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001)
struct mpi3_security_page2 {
struct mpi3_config_page_header header;
__le32 reserved08[2];
union mpi3_security_mac mac;
union mpi3_security_nonce nonce;
__le32 reserved90[3];
u8 num_roots;
u8 reserved9d[3];
struct mpi3_security2_trusted_root trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX];
};
#define MPI3_SECURITY2_PAGEVERSION (0x00)
struct mpi3_sas_io_unit0_phy_data {
u8 io_unit_port;
u8 port_flags;
@ -2351,6 +2433,10 @@ struct mpi3_device_page0 {
#define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f)
#define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80)
#define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f)
#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xe000)
#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000)
#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000)
#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000)
#define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080)
#define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010)
#define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008)

2
drivers/scsi/mpi3mr/mpi/mpi30_image.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2018-2022 Broadcom Inc. All rights reserved.
* Copyright 2018-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_IMAGE_H
#define MPI30_IMAGE_H 1

23
drivers/scsi/mpi3mr/mpi/mpi30_init.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_INIT_H
#define MPI30_INIT_H 1
@ -56,6 +56,7 @@ struct mpi3_scsi_io_request {
#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000f0)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020)
#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080)
#define MPI3_SCSIIO_METASGL_INDEX (3)
struct mpi3_scsi_io_reply {
@ -114,4 +115,24 @@ struct mpi3_scsi_io_reply {
#define MPI3_SCSI_RSP_ARI0_MASK (0xff000000)
#define MPI3_SCSI_RSP_ARI0_SHIFT (24)
#define MPI3_SCSI_TASKTAG_UNKNOWN (0xffff)
#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02)
#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a)
#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)
#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a)
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81)
#endif

2
drivers/scsi/mpi3mr/mpi/mpi30_ioc.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_IOC_H
#define MPI30_IOC_H 1

6
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
View File

@ -1,11 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*
*/
#ifndef MPI30_PCI_H
#define MPI30_PCI_H 1
#ifndef MPI3_NVME_ENCAP_CMD_MAX
#define MPI3_NVME_ENCAP_CMD_MAX (1)
#endif
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)

2
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_SAS_H
#define MPI30_SAS_H 1

4
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
* Copyright 2016-2023 Broadcom Inc. All rights reserved.
*/
#ifndef MPI30_TRANSPORT_H
#define MPI30_TRANSPORT_H 1
@ -18,7 +18,7 @@ union mpi3_version_union {
#define MPI3_VERSION_MAJOR (3)
#define MPI3_VERSION_MINOR (0)
#define MPI3_VERSION_UNIT (26)
#define MPI3_VERSION_UNIT (27)
#define MPI3_VERSION_DEV (0)
#define MPI3_DEVHANDLE_INVALID (0xffff)
struct mpi3_sysif_oper_queue_indexes {

15
drivers/scsi/mpi3mr/mpi3mr.h
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/
@ -55,8 +55,8 @@ extern struct list_head mrioc_list;
extern int prot_mask;
extern atomic64_t event_counter;
#define MPI3MR_DRIVER_VERSION "8.2.0.3.0"
#define MPI3MR_DRIVER_RELDATE "08-September-2022"
#define MPI3MR_DRIVER_VERSION "8.4.1.0.0"
#define MPI3MR_DRIVER_RELDATE "16-March-2023"
#define MPI3MR_DRIVER_NAME "mpi3mr"
#define MPI3MR_DRIVER_LICENSE "GPL"
@ -126,6 +126,7 @@ extern atomic64_t event_counter;
#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
#define MPI3MR_RESET_ACK_TIMEOUT 30
#define MPI3MR_MUR_TIMEOUT 120
#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
@ -652,7 +653,11 @@ union _form_spec_inf {
struct tgt_dev_vd vd_inf;
};
enum mpi3mr_dev_state {
MPI3MR_DEV_CREATED = 1,
MPI3MR_DEV_REMOVE_HS_STARTED = 2,
MPI3MR_DEV_DELETED = 3,
};
/**
* struct mpi3mr_tgt_dev - target device data structure
@ -676,6 +681,7 @@ union _form_spec_inf {
* @enclosure_logical_id: Enclosure logical identifier
* @dev_spec: Device type specific information
* @ref_count: Reference count
* @state: device state
*/
struct mpi3mr_tgt_dev {
struct list_head list;
@ -697,6 +703,7 @@ struct mpi3mr_tgt_dev {
u64 enclosure_logical_id;
union _form_spec_inf dev_spec;
struct kref ref_count;
enum mpi3mr_dev_state state;
};
/**

5
drivers/scsi/mpi3mr/mpi3mr_app.c
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/
@ -922,6 +922,7 @@ err_out:
/**
* mpi3mr_bsg_process_mpt_cmds - MPI Pass through BSG handler
* @job: BSG job reference
* @reply_payload_rcv_len: length of payload recvd
*
* This function is the top level handler for MPI Pass through
* command, this does basic validation of the input data buffers,
@ -1471,6 +1472,7 @@ static int mpi3mr_bsg_request(struct bsg_job *job)
/**
* mpi3mr_bsg_exit - de-registration from bsg layer
* @mrioc: Adapter instance reference
*
* This will be called during driver unload and all
* bsg resources allocated during load will be freed.
@ -1505,6 +1507,7 @@ static void mpi3mr_bsg_node_release(struct device *dev)
/**
* mpi3mr_bsg_init - registration with bsg layer
* @mrioc: Adapter instance reference
*
* This will be called during driver load and it will
* register driver with bsg layer

2
drivers/scsi/mpi3mr/mpi3mr_debug.h
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/

6
drivers/scsi/mpi3mr/mpi3mr_fw.c
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/
@ -1092,7 +1092,7 @@ static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
timeout = MPI3MR_MUR_TIMEOUT * 10;
do {
ioc_status = readl(&mrioc->sysif_regs->ioc_status);
if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
@ -2597,14 +2597,12 @@ static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
mrioc->num_admin_req = mrioc->admin_req_q_sz /
MPI3MR_ADMIN_REQ_FRAME_SZ;
mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
mrioc->admin_req_base = NULL;
mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
MPI3MR_ADMIN_REPLY_FRAME_SZ;
mrioc->admin_reply_ci = 0;
mrioc->admin_reply_ephase = 1;
mrioc->admin_reply_base = NULL;
if (!mrioc->admin_req_base) {
mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,

78
drivers/scsi/mpi3mr/mpi3mr_os.c
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/
@ -652,6 +652,7 @@ static void mpi3mr_tgtdev_add_to_list(struct mpi3mr_ioc *mrioc,
mpi3mr_tgtdev_get(tgtdev);
INIT_LIST_HEAD(&tgtdev->list);
list_add_tail(&tgtdev->list, &mrioc->tgtdev_list);
tgtdev->state = MPI3MR_DEV_CREATED;
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
}
@ -659,20 +660,25 @@ static void mpi3mr_tgtdev_add_to_list(struct mpi3mr_ioc *mrioc,
* mpi3mr_tgtdev_del_from_list -Delete tgtdevice from the list
* @mrioc: Adapter instance reference
* @tgtdev: Target device
* @must_delete: Must delete the target device from the list irrespective
* of the device state.
*
* Remove the target device from the target device list
*
* Return: Nothing.
*/
static void mpi3mr_tgtdev_del_from_list(struct mpi3mr_ioc *mrioc,
struct mpi3mr_tgt_dev *tgtdev)
struct mpi3mr_tgt_dev *tgtdev, bool must_delete)
{
unsigned long flags;
spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
if (!list_empty(&tgtdev->list)) {
list_del_init(&tgtdev->list);
mpi3mr_tgtdev_put(tgtdev);
if ((tgtdev->state == MPI3MR_DEV_REMOVE_HS_STARTED) || (must_delete == true)) {
if (!list_empty(&tgtdev->list)) {
list_del_init(&tgtdev->list);
tgtdev->state = MPI3MR_DEV_DELETED;
mpi3mr_tgtdev_put(tgtdev);
}
}
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
}
@ -1036,7 +1042,7 @@ void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc)
tgtdev->perst_id);
if (tgtdev->host_exposed)
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev, true);
mpi3mr_tgtdev_put(tgtdev);
}
}
@ -1281,12 +1287,12 @@ static void mpi3mr_devstatuschg_evt_bh(struct mpi3mr_ioc *mrioc,
if (!tgtdev->host_exposed)
mpi3mr_report_tgtdev_to_host(mrioc, tgtdev->perst_id);
}
if (tgtdev->starget && tgtdev->starget->hostdata) {
if (delete)
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
}
if (delete)
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
if (cleanup) {
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev, false);
mpi3mr_tgtdev_put(tgtdev);
}
@ -1604,7 +1610,7 @@ static void mpi3mr_sastopochg_evt_bh(struct mpi3mr_ioc *mrioc,
case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING:
if (tgtdev->host_exposed)
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev, false);
mpi3mr_tgtdev_put(tgtdev);
break;
case MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING:
@ -1762,7 +1768,7 @@ static void mpi3mr_pcietopochg_evt_bh(struct mpi3mr_ioc *mrioc,
case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING:
if (tgtdev->host_exposed)
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev, false);
mpi3mr_tgtdev_put(tgtdev);
break;
default:
@ -2016,12 +2022,18 @@ static int mpi3mr_create_tgtdev(struct mpi3mr_ioc *mrioc,
int retval = 0;
struct mpi3mr_tgt_dev *tgtdev = NULL;
u16 perst_id = 0;
unsigned long flags;
perst_id = le16_to_cpu(dev_pg0->persistent_id);
if (perst_id == MPI3_DEVICE0_PERSISTENTID_INVALID)
return retval;
tgtdev = mpi3mr_get_tgtdev_by_perst_id(mrioc, perst_id);
spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
tgtdev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, perst_id);
if (tgtdev)
tgtdev->state = MPI3MR_DEV_CREATED;
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
if (tgtdev) {
mpi3mr_update_tgtdev(mrioc, tgtdev, dev_pg0, true);
mpi3mr_tgtdev_put(tgtdev);
@ -2219,6 +2231,14 @@ static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_ioc *mrioc, u16 handle,
u8 retrycount = 5;
struct mpi3mr_drv_cmd *drv_cmd = cmdparam;
struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL;
struct mpi3mr_tgt_dev *tgtdev = NULL;
unsigned long flags;
spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
tgtdev = __mpi3mr_get_tgtdev_by_handle(mrioc, handle);
if (tgtdev && (iou_rc == MPI3_CTRL_OP_REMOVE_DEVICE))
tgtdev->state = MPI3MR_DEV_REMOVE_HS_STARTED;
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
if (drv_cmd)
goto issue_cmd;
@ -3995,10 +4015,14 @@ static int mpi3mr_eh_target_reset(struct scsi_cmnd *scmd)
stgt_priv_data = sdev_priv_data->tgt_priv_data;
dev_handle = stgt_priv_data->dev_handle;
if (stgt_priv_data->dev_removed) {
struct scmd_priv *cmd_priv = scsi_cmd_priv(scmd);
sdev_printk(KERN_INFO, scmd->device,
"%s:target(handle = 0x%04x) is removed, target reset is not issued\n",
mrioc->name, dev_handle);
retval = FAILED;
if (!cmd_priv->in_lld_scope || cmd_priv->host_tag == MPI3MR_HOSTTAG_INVALID)
retval = SUCCESS;
else
retval = FAILED;
goto out;
}
sdev_printk(KERN_INFO, scmd->device,
@ -4063,10 +4087,14 @@ static int mpi3mr_eh_dev_reset(struct scsi_cmnd *scmd)
stgt_priv_data = sdev_priv_data->tgt_priv_data;
dev_handle = stgt_priv_data->dev_handle;
if (stgt_priv_data->dev_removed) {
struct scmd_priv *cmd_priv = scsi_cmd_priv(scmd);
sdev_printk(KERN_INFO, scmd->device,
"%s: device(handle = 0x%04x) is removed, device(LUN) reset is not issued\n",
mrioc->name, dev_handle);
retval = FAILED;
if (!cmd_priv->in_lld_scope || cmd_priv->host_tag == MPI3MR_HOSTTAG_INVALID)
retval = SUCCESS;
else
retval = FAILED;
goto out;
}
sdev_printk(KERN_INFO, scmd->device,
@ -4624,13 +4652,24 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost,
goto out;
}
stgt_priv_data = sdev_priv_data->tgt_priv_data;
dev_handle = stgt_priv_data->dev_handle;
/* Avoid error handling escalation when device is removed or blocked */
if (scmd->device->host->shost_state == SHOST_RECOVERY &&
scmd->cmnd[0] == TEST_UNIT_READY &&
(stgt_priv_data->dev_removed || (dev_handle == MPI3MR_INVALID_DEV_HANDLE))) {
scsi_build_sense(scmd, 0, UNIT_ATTENTION, 0x29, 0x07);
scsi_done(scmd);
goto out;
}
if (mrioc->reset_in_progress) {
retval = SCSI_MLQUEUE_HOST_BUSY;
goto out;
}
stgt_priv_data = sdev_priv_data->tgt_priv_data;
if (atomic_read(&stgt_priv_data->block_io)) {
if (mrioc->stop_drv_processing) {
scmd->result = DID_NO_CONNECT << 16;
@ -4641,7 +4680,6 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost,
goto out;
}
dev_handle = stgt_priv_data->dev_handle;
if (dev_handle == MPI3MR_INVALID_DEV_HANDLE) {
scmd->result = DID_NO_CONNECT << 16;
scsi_done(scmd);
@ -5108,7 +5146,7 @@ static void mpi3mr_remove(struct pci_dev *pdev)
list_for_each_entry_safe(tgtdev, tgtdev_next, &mrioc->tgtdev_list,
list) {
mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
mpi3mr_tgtdev_del_from_list(mrioc, tgtdev, true);
mpi3mr_tgtdev_put(tgtdev);
}
mpi3mr_stop_watchdog(mrioc);

2
drivers/scsi/mpi3mr/mpi3mr_transport.c
View File

@ -2,7 +2,7 @@
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* Copyright (C) 2017-2023 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/