arm64: dts: qcom: sdx75: Support for I2C and SPI
Add devicetree node for I2C and SPI busses in SDX75. Signed-off-by: Rohit Agarwal <rohiagar@qti.qualcomm.com> Link: https://lore.kernel.org/r/20240517100423.2006022-3-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Rohit Agarwal
Bjorn Andersson
parent
6596118ccd
commit
e07c4a702e
@ -8,6 +8,7 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sdx75-gcc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sdx75.h>
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@ -487,6 +488,28 @@
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#mbox-cells = <2>;
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};
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gpi_dma: dma-controller@900000 {
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compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
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reg = <0x0 0x00900000 0x0 0x60000>;
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#dma-cells = <3>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <12>;
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dma-channel-mask = <0x7f>;
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iommus = <&apps_smmu 0xf6 0x0>;
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status = "disabled";
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};
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qupv3_id_0: geniqup@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x009c0000 0x0 0x2000>;
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@ -503,6 +526,52 @@
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ranges;
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status = "disabled";
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i2c0: i2c@980000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00980000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c0_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
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<&gpi_dma 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi0: spi@980000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00980000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
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<&gpi_dma 1 0 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart1: serial@984000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00984000 0x0 0x4000>;
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@ -521,6 +590,229 @@
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"sleep";
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status = "disabled";
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};
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i2c2: i2c@988000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00988000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c2_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
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<&gpi_dma 1 2 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi2: spi@988000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00988000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
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<&gpi_dma 1 2 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c3: i2c@98c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x0098c000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c3_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
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<&gpi_dma 1 3 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi3: spi@98c000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x0098c000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
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<&gpi_dma 1 3 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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uart4: serial@990000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x00990000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c5: i2c@994000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00994000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c5_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
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<&gpi_dma 1 5 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c6: i2c@998000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00998000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c6_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
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<&gpi_dma 1 6 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi6: spi@998000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00998000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
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<&gpi_dma 1 6 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c7: i2c@99c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x0099c000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_i2c7_data_clk>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
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<&gpi_dma 1 7 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi7: spi@99c000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x0099c000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
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pinctrl-names = "default";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
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<&gpi_dma 1 7 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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};
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usb_hsphy: phy@ff4000 {
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@ -771,6 +1063,145 @@
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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qup_i2c0_data_clk: qup-i2c0-data-clk-state {
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/* SDA, SCL */
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pins = "gpio8", "gpio9";
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function = "qup_se0";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c2_data_clk: qup-i2c2-data-clk-state {
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/* SDA, SCL */
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pins = "gpio14", "gpio15";
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function = "qup_se2";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c3_data_clk: qup-i2c3-data-clk-state {
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/* SDA, SCL */
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pins = "gpio52", "gpio53";
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function = "qup_se3";
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drive-strength = <2>;
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bias-pull-up;
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};
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|
||||
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
|
||||
/* SDA, SCL */
|
||||
pins = "gpio110", "gpio111";
|
||||
function = "qup_se5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
|
||||
/* SDA, SCL */
|
||||
pins = "gpio112", "gpio113";
|
||||
function = "qup_se6";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
|
||||
/* SDA, SCL */
|
||||
pins = "gpio116", "gpio117";
|
||||
function = "qup_se7";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_spi0_cs: qup-spi0-cs-state {
|
||||
pins = "gpio11";
|
||||
function = "qup_se0";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi0_data_clk: qup-spi0-data-clk-state {
|
||||
/* MISO, MOSI, CLK */
|
||||
pins = "gpio8", "gpio9", "gpio10";
|
||||
function = "qup_se0";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi2_cs: qup-spi2-cs-state {
|
||||
pins = "gpio17";
|
||||
function = "qup_se2";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi2_data_clk: qup-spi2-data-clk-state {
|
||||
/* MISO, MOSI, CLK */
|
||||
pins = "gpio14", "gpio15", "gpio16";
|
||||
function = "qup_se2";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi3_cs: qup-spi3-cs-state {
|
||||
pins = "gpio55";
|
||||
function = "qup_se3";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi3_data_clk: qup-spi3-data-clk-state {
|
||||
/* MISO, MOSI, CLK */
|
||||
pins = "gpio52", "gpio53", "gpio54";
|
||||
function = "qup_se3";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi6_cs: qup-spi6-cs-state {
|
||||
pins = "gpio115";
|
||||
function = "qup_se6";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi6_data_clk: qup-spi6-data-clk-state {
|
||||
/* MISO, MOSI, CLK */
|
||||
pins = "gpio112", "gpio113", "gpio114";
|
||||
function = "qup_se6";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi7_cs: qup-spi7-cs-state {
|
||||
pins = "gpio119";
|
||||
function = "qup_se7";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_spi7_data_clk: qup-spi7-data-clk-state {
|
||||
/* MISO, MOSI, CLK */
|
||||
pins = "gpio116", "gpio117", "gpio118";
|
||||
function = "qup_se7";
|
||||
drive-strength = <6>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_uart4_cts_rts: qup-uart4-cts-rts-state {
|
||||
/* CTS, RTS */
|
||||
pins = "gpio52", "gpio53";
|
||||
function = "qup_se3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_uart4_default: qup-uart4-default-state {
|
||||
/* TX, RX */
|
||||
pins = "gpio54", "gpio55";
|
||||
function = "qup_se3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
|
||||
tx-pins {
|
||||
pins = "gpio12";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user