arm64: lse: fix LSE atomics with LLVM's integrated assembler
Unlike gcc, clang considers each inline assembly block to be independent and therefore, when using the integrated assembler for inline assembly, any preambles that enable features must be repeated in each block. This change defines __LSE_PREAMBLE and adds it to each inline assembly block that has LSE instructions, which allows them to be compiled also with clang's assembler. Link: https://github.com/ClangBuiltLinux/linux/issues/671 Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Andrew Murray <andrew.murray@arm.com> Tested-by: Kees Cook <keescook@chromium.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Sami Tolvanen
Will Deacon
parent
46cf053efe
commit
e0d5896bd3
@ -14,6 +14,7 @@
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static inline void __lse_atomic_##op(int i, atomic_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op " %w[i], %[v]\n" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v)); \
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@ -30,6 +31,7 @@ ATOMIC_OP(add, stadd)
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static inline int __lse_atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op #mb " %w[i], %w[i], %[v]" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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@ -58,6 +60,7 @@ static inline int __lse_atomic_add_return##name(int i, atomic_t *v) \
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u32 tmp; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" ldadd" #mb " %w[i], %w[tmp], %[v]\n" \
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" add %w[i], %w[i], %w[tmp]" \
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: [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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@ -77,6 +80,7 @@ ATOMIC_OP_ADD_RETURN( , al, "memory")
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static inline void __lse_atomic_and(int i, atomic_t *v)
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{
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asm volatile(
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__LSE_PREAMBLE
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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@ -87,6 +91,7 @@ static inline void __lse_atomic_and(int i, atomic_t *v)
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static inline int __lse_atomic_fetch_and##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" mvn %w[i], %w[i]\n" \
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" ldclr" #mb " %w[i], %w[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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@ -106,6 +111,7 @@ ATOMIC_FETCH_OP_AND( , al, "memory")
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static inline void __lse_atomic_sub(int i, atomic_t *v)
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{
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asm volatile(
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__LSE_PREAMBLE
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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@ -118,6 +124,7 @@ static inline int __lse_atomic_sub_return##name(int i, atomic_t *v) \
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u32 tmp; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[tmp], %[v]\n" \
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" add %w[i], %w[i], %w[tmp]" \
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@ -139,6 +146,7 @@ ATOMIC_OP_SUB_RETURN( , al, "memory")
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static inline int __lse_atomic_fetch_sub##name(int i, atomic_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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@ -159,6 +167,7 @@ ATOMIC_FETCH_OP_SUB( , al, "memory")
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static inline void __lse_atomic64_##op(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op " %[i], %[v]\n" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v)); \
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@ -175,6 +184,7 @@ ATOMIC64_OP(add, stadd)
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static inline long __lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v)\
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" " #asm_op #mb " %[i], %[i], %[v]" \
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: [i] "+r" (i), [v] "+Q" (v->counter) \
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: "r" (v) \
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@ -203,6 +213,7 @@ static inline long __lse_atomic64_add_return##name(s64 i, atomic64_t *v)\
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unsigned long tmp; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" ldadd" #mb " %[i], %x[tmp], %[v]\n" \
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" add %[i], %[i], %x[tmp]" \
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: [i] "+r" (i), [v] "+Q" (v->counter), [tmp] "=&r" (tmp) \
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@ -222,6 +233,7 @@ ATOMIC64_OP_ADD_RETURN( , al, "memory")
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static inline void __lse_atomic64_and(s64 i, atomic64_t *v)
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{
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asm volatile(
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__LSE_PREAMBLE
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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@ -232,6 +244,7 @@ static inline void __lse_atomic64_and(s64 i, atomic64_t *v)
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static inline long __lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" mvn %[i], %[i]\n" \
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" ldclr" #mb " %[i], %[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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@ -251,6 +264,7 @@ ATOMIC64_FETCH_OP_AND( , al, "memory")
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static inline void __lse_atomic64_sub(s64 i, atomic64_t *v)
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{
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asm volatile(
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__LSE_PREAMBLE
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]"
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: [i] "+&r" (i), [v] "+Q" (v->counter)
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@ -263,6 +277,7 @@ static inline long __lse_atomic64_sub_return##name(s64 i, atomic64_t *v) \
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unsigned long tmp; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %x[tmp], %[v]\n" \
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" add %[i], %[i], %x[tmp]" \
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@ -284,6 +299,7 @@ ATOMIC64_OP_SUB_RETURN( , al, "memory")
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static inline long __lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \
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{ \
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asm volatile( \
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__LSE_PREAMBLE \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %[i], %[v]" \
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: [i] "+&r" (i), [v] "+Q" (v->counter) \
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@ -305,6 +321,7 @@ static inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v)
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unsigned long tmp;
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asm volatile(
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__LSE_PREAMBLE
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"1: ldr %x[tmp], %[v]\n"
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" subs %[ret], %x[tmp], #1\n"
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" b.lt 2f\n"
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@ -332,6 +349,7 @@ __lse__cmpxchg_case_##name##sz(volatile void *ptr, \
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unsigned long tmp; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" mov %" #w "[tmp], %" #w "[old]\n" \
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" cas" #mb #sfx "\t%" #w "[tmp], %" #w "[new], %[v]\n" \
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" mov %" #w "[ret], %" #w "[tmp]" \
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@ -379,6 +397,7 @@ __lse__cmpxchg_double##name(unsigned long old1, \
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register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
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\
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asm volatile( \
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__LSE_PREAMBLE \
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" casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
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" eor %[old1], %[old1], %[oldval1]\n" \
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" eor %[old2], %[old2], %[oldval2]\n" \
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@ -6,6 +6,8 @@
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#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
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#define __LSE_PREAMBLE ".arch armv8-a+lse\n"
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#include <linux/compiler_types.h>
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#include <linux/export.h>
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#include <linux/jump_label.h>
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@ -14,8 +16,6 @@
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#include <asm/atomic_lse.h>
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#include <asm/cpucaps.h>
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__asm__(".arch_extension lse");
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extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
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extern struct static_key_false arm64_const_caps_ready;
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@ -34,7 +34,7 @@ static inline bool system_uses_lse_atomics(void)
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/* In-line patching at runtime */
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#define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
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ALTERNATIVE(llsc, lse, ARM64_HAS_LSE_ATOMICS)
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ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS)
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#else /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
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