clk: en7523: Add reset-controller support for EN7581 SoC
Introduce reset API support to EN7581 clock driver. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/4f735d17e549ea53769bf5a3f50406debb879a44.1719485847.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lorenzo Bianconi
Stephen Boyd
parent
7aa291962f
commit
e0d8ea4ed5
@ -5,7 +5,11 @@
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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#define RST_NR_PER_BANK 32
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#define REG_PCI_CONTROL 0x88
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#define REG_PCI_CONTROL_PERSTOUT BIT(29)
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@ -40,6 +44,9 @@
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
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#define REG_RST_CTRL2 0x00
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#define REG_RST_CTRL1 0x04
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struct en_clk_desc {
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int id;
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const char *name;
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@ -64,8 +71,20 @@ struct en_clk_gate {
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struct clk_hw hw;
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};
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struct en_rst_data {
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const u16 *bank_ofs;
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const u16 *idx_map;
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void __iomem *base;
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struct reset_controller_dev rcdev;
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};
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struct en_clk_soc_data {
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const struct clk_ops pcie_ops;
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struct {
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const u16 *bank_ofs;
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const u16 *idx_map;
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u16 idx_map_nr;
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} reset;
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int (*hw_init)(struct platform_device *pdev, void __iomem *base,
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void __iomem *np_base);
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};
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@ -168,6 +187,69 @@ static const struct en_clk_desc en7523_base_clks[] = {
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}
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};
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static const u16 en7581_rst_ofs[] = {
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REG_RST_CTRL2,
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REG_RST_CTRL1,
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};
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static const u16 en7581_rst_map[] = {
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/* RST_CTRL2 */
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[EN7581_XPON_PHY_RST] = 0,
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[EN7581_CPU_TIMER2_RST] = 2,
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[EN7581_HSUART_RST] = 3,
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[EN7581_UART4_RST] = 4,
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[EN7581_UART5_RST] = 5,
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[EN7581_I2C2_RST] = 6,
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[EN7581_XSI_MAC_RST] = 7,
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[EN7581_XSI_PHY_RST] = 8,
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[EN7581_NPU_RST] = 9,
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[EN7581_I2S_RST] = 10,
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[EN7581_TRNG_RST] = 11,
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[EN7581_TRNG_MSTART_RST] = 12,
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[EN7581_DUAL_HSI0_RST] = 13,
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[EN7581_DUAL_HSI1_RST] = 14,
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[EN7581_HSI_RST] = 15,
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[EN7581_DUAL_HSI0_MAC_RST] = 16,
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[EN7581_DUAL_HSI1_MAC_RST] = 17,
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[EN7581_HSI_MAC_RST] = 18,
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[EN7581_WDMA_RST] = 19,
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[EN7581_WOE0_RST] = 20,
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[EN7581_WOE1_RST] = 21,
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[EN7581_HSDMA_RST] = 22,
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[EN7581_TDMA_RST] = 24,
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[EN7581_EMMC_RST] = 25,
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[EN7581_SOE_RST] = 26,
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[EN7581_PCIE2_RST] = 27,
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[EN7581_XFP_MAC_RST] = 28,
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[EN7581_USB_HOST_P1_RST] = 29,
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[EN7581_USB_HOST_P1_U3_PHY_RST] = 30,
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/* RST_CTRL1 */
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[EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
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[EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
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[EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
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[EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
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[EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
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[EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
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[EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
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[EN7581_UART_RST] = RST_NR_PER_BANK + 12,
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[EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
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[EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
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[EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
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[EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
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[EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
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[EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
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[EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
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[EN7581_FE_RST] = RST_NR_PER_BANK + 21,
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[EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
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[EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
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[EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
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[EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
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[EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
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[EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
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[EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
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[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
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};
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static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
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{
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const struct en_clk_desc *desc = &en7523_base_clks[i];
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@ -370,7 +452,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
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void __iomem *pb_base;
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u32 val;
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pb_base = devm_platform_ioremap_resource(pdev, 2);
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pb_base = devm_platform_ioremap_resource(pdev, 3);
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if (IS_ERR(pb_base))
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return PTR_ERR(pb_base);
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@ -423,6 +505,95 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
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clk_data->num = EN7523_NUM_CLOCKS;
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}
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static int en7523_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
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void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
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u32 val;
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val = readl(addr);
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if (assert)
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val |= BIT(id % RST_NR_PER_BANK);
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else
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val &= ~BIT(id % RST_NR_PER_BANK);
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writel(val, addr);
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return 0;
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}
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static int en7523_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return en7523_reset_update(rcdev, id, true);
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}
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static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return en7523_reset_update(rcdev, id, false);
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}
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static int en7523_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
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void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
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return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
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}
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static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
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if (reset_spec->args[0] >= rcdev->nr_resets)
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return -EINVAL;
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return rst_data->idx_map[reset_spec->args[0]];
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}
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static const struct reset_control_ops en7523_reset_ops = {
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.assert = en7523_reset_assert,
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.deassert = en7523_reset_deassert,
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.status = en7523_reset_status,
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};
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static int en7523_reset_register(struct platform_device *pdev,
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const struct en_clk_soc_data *soc_data)
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{
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struct device *dev = &pdev->dev;
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struct en_rst_data *rst_data;
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void __iomem *base;
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/* no reset lines available */
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if (!soc_data->reset.idx_map_nr)
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return 0;
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base = devm_platform_ioremap_resource(pdev, 2);
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if (IS_ERR(base))
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return PTR_ERR(base);
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rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
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if (!rst_data)
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return -ENOMEM;
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rst_data->bank_ofs = soc_data->reset.bank_ofs;
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rst_data->idx_map = soc_data->reset.idx_map;
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rst_data->base = base;
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rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
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rst_data->rcdev.of_xlate = en7523_reset_xlate;
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rst_data->rcdev.ops = &en7523_reset_ops;
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rst_data->rcdev.of_node = dev->of_node;
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rst_data->rcdev.of_reset_n_cells = 1;
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rst_data->rcdev.owner = THIS_MODULE;
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rst_data->rcdev.dev = dev;
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return devm_reset_controller_register(dev, &rst_data->rcdev);
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}
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static int en7523_clk_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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@ -456,11 +627,17 @@ static int en7523_clk_probe(struct platform_device *pdev)
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
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pdev->name);
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return r;
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r = en7523_reset_register(pdev, soc_data);
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if (r) {
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of_clk_del_provider(node);
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return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
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pdev->name);
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}
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return 0;
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}
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static const struct en_clk_soc_data en7523_data = {
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@ -479,6 +656,11 @@ static const struct en_clk_soc_data en7581_data = {
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.unprepare = en7581_pci_unprepare,
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.disable = en7581_pci_disable,
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},
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.reset = {
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.bank_ofs = en7581_rst_ofs,
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.idx_map = en7581_rst_map,
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.idx_map_nr = ARRAY_SIZE(en7581_rst_map),
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},
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.hw_init = en7581_clk_hw_init,
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};
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