drm/radeon/kms: add hpd support for r6xx/r7xx/rs780/rs880 asics
This just adds the functionality, it's not hooked up yet. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
dcfdd40835
commit
e0df1ac5c2
@ -74,6 +74,281 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
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void r600_gpu_init(struct radeon_device *rdev);
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void r600_fini(struct radeon_device *rdev);
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/* hpd for digital panel detect/disconnect */
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bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
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{
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bool connected = false;
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if (ASIC_IS_DCE3(rdev)) {
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switch (hpd) {
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case RADEON_HPD_1:
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if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_2:
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if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_3:
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if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_4:
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if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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/* DCE 3.2 */
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case RADEON_HPD_5:
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if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_6:
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if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
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connected = true;
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break;
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default:
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break;
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}
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} else {
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switch (hpd) {
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case RADEON_HPD_1:
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if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_2:
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if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
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connected = true;
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break;
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case RADEON_HPD_3:
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if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
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connected = true;
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break;
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default:
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break;
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}
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}
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return connected;
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}
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void r600_hpd_set_polarity(struct radeon_device *rdev,
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enum radeon_hpd_id hpd)
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{
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u32 tmp;
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bool connected = r600_hpd_sense(rdev, hpd);
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if (ASIC_IS_DCE3(rdev)) {
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switch (hpd) {
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case RADEON_HPD_1:
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tmp = RREG32(DC_HPD1_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD1_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_2:
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tmp = RREG32(DC_HPD2_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD2_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_3:
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tmp = RREG32(DC_HPD3_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD3_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_4:
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tmp = RREG32(DC_HPD4_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD4_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_5:
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tmp = RREG32(DC_HPD5_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD5_INT_CONTROL, tmp);
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break;
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/* DCE 3.2 */
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case RADEON_HPD_6:
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tmp = RREG32(DC_HPD6_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HPDx_INT_POLARITY;
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else
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tmp |= DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD6_INT_CONTROL, tmp);
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break;
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default:
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break;
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}
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} else {
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switch (hpd) {
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case RADEON_HPD_1:
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tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
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else
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tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_2:
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tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
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else
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tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
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break;
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case RADEON_HPD_3:
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tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
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if (connected)
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tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
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else
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tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
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break;
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default:
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break;
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}
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}
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}
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void r600_hpd_init(struct radeon_device *rdev)
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{
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struct drm_device *dev = rdev->ddev;
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struct drm_connector *connector;
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if (ASIC_IS_DCE3(rdev)) {
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u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
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if (ASIC_IS_DCE32(rdev))
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tmp |= DC_HPDx_EN;
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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switch (radeon_connector->hpd.hpd) {
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case RADEON_HPD_1:
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WREG32(DC_HPD1_CONTROL, tmp);
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rdev->irq.hpd[0] = true;
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break;
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case RADEON_HPD_2:
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WREG32(DC_HPD2_CONTROL, tmp);
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rdev->irq.hpd[1] = true;
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break;
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case RADEON_HPD_3:
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WREG32(DC_HPD3_CONTROL, tmp);
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rdev->irq.hpd[2] = true;
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break;
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case RADEON_HPD_4:
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WREG32(DC_HPD4_CONTROL, tmp);
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rdev->irq.hpd[3] = true;
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break;
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/* DCE 3.2 */
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case RADEON_HPD_5:
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WREG32(DC_HPD5_CONTROL, tmp);
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rdev->irq.hpd[4] = true;
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break;
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case RADEON_HPD_6:
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WREG32(DC_HPD6_CONTROL, tmp);
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rdev->irq.hpd[5] = true;
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break;
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default:
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break;
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}
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}
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} else {
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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switch (radeon_connector->hpd.hpd) {
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case RADEON_HPD_1:
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WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
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rdev->irq.hpd[0] = true;
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break;
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case RADEON_HPD_2:
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WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
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rdev->irq.hpd[1] = true;
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break;
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case RADEON_HPD_3:
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WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
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rdev->irq.hpd[2] = true;
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break;
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default:
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break;
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}
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}
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}
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r600_irq_set(rdev);
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}
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void r600_hpd_fini(struct radeon_device *rdev)
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{
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struct drm_device *dev = rdev->ddev;
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struct drm_connector *connector;
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if (ASIC_IS_DCE3(rdev)) {
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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switch (radeon_connector->hpd.hpd) {
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case RADEON_HPD_1:
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WREG32(DC_HPD1_CONTROL, 0);
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rdev->irq.hpd[0] = false;
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break;
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case RADEON_HPD_2:
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WREG32(DC_HPD2_CONTROL, 0);
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rdev->irq.hpd[1] = false;
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break;
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case RADEON_HPD_3:
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WREG32(DC_HPD3_CONTROL, 0);
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rdev->irq.hpd[2] = false;
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break;
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case RADEON_HPD_4:
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WREG32(DC_HPD4_CONTROL, 0);
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rdev->irq.hpd[3] = false;
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break;
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/* DCE 3.2 */
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case RADEON_HPD_5:
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WREG32(DC_HPD5_CONTROL, 0);
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rdev->irq.hpd[4] = false;
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break;
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case RADEON_HPD_6:
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WREG32(DC_HPD6_CONTROL, 0);
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rdev->irq.hpd[5] = false;
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break;
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default:
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break;
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}
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}
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} else {
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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switch (radeon_connector->hpd.hpd) {
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case RADEON_HPD_1:
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WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
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rdev->irq.hpd[0] = false;
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break;
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case RADEON_HPD_2:
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WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
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rdev->irq.hpd[1] = false;
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break;
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case RADEON_HPD_3:
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WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
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rdev->irq.hpd[2] = false;
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break;
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default:
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break;
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}
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}
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}
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}
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/*
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* R600 PCIE GART
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*/
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@ -2060,6 +2335,42 @@ static void r600_disable_interrupts(struct radeon_device *rdev)
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rdev->ih.rptr = 0;
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}
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static void r600_disable_interrupt_state(struct radeon_device *rdev)
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{
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u32 tmp;
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WREG32(CP_INT_CNTL, 0);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(DxMODE_INT_MASK, 0);
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if (ASIC_IS_DCE3(rdev)) {
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WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
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WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
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tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD1_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD2_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD3_INT_CONTROL, tmp);
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tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD4_INT_CONTROL, tmp);
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if (ASIC_IS_DCE32(rdev)) {
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tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD5_INT_CONTROL, 0);
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tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
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WREG32(DC_HPD6_INT_CONTROL, 0);
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}
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} else {
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WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
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WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
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tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
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tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
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tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
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WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
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}
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}
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int r600_irq_init(struct radeon_device *rdev)
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{
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int ret = 0;
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@ -2122,9 +2433,7 @@ int r600_irq_init(struct radeon_device *rdev)
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WREG32(IH_CNTL, ih_cntl);
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/* force the active interrupt state to all disabled */
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WREG32(CP_INT_CNTL, 0);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(DxMODE_INT_MASK, 0);
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r600_disable_interrupt_state(rdev);
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/* enable irqs */
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r600_enable_interrupts(rdev);
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@ -2141,13 +2450,29 @@ void r600_irq_fini(struct radeon_device *rdev)
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int r600_irq_set(struct radeon_device *rdev)
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{
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uint32_t cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
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uint32_t mode_int = 0;
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u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
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u32 mode_int = 0;
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u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
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/* don't enable anything if the ih is disabled */
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if (!rdev->ih.enabled)
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return 0;
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if (ASIC_IS_DCE3(rdev)) {
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hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
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if (ASIC_IS_DCE32(rdev)) {
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hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
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}
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} else {
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hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
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hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
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}
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if (rdev->irq.sw_int) {
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DRM_DEBUG("r600_irq_set: sw int\n");
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cp_int_cntl |= RB_INT_ENABLE;
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@ -2160,39 +2485,137 @@ int r600_irq_set(struct radeon_device *rdev)
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DRM_DEBUG("r600_irq_set: vblank 1\n");
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mode_int |= D2MODE_VBLANK_INT_MASK;
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}
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if (rdev->irq.hpd[0]) {
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DRM_DEBUG("r600_irq_set: hpd 1\n");
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hpd1 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[1]) {
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DRM_DEBUG("r600_irq_set: hpd 2\n");
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hpd2 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[2]) {
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DRM_DEBUG("r600_irq_set: hpd 3\n");
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hpd3 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[3]) {
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DRM_DEBUG("r600_irq_set: hpd 4\n");
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hpd4 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[4]) {
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DRM_DEBUG("r600_irq_set: hpd 5\n");
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hpd5 |= DC_HPDx_INT_EN;
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}
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if (rdev->irq.hpd[5]) {
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DRM_DEBUG("r600_irq_set: hpd 6\n");
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hpd6 |= DC_HPDx_INT_EN;
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}
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WREG32(CP_INT_CNTL, cp_int_cntl);
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WREG32(DxMODE_INT_MASK, mode_int);
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if (ASIC_IS_DCE3(rdev)) {
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WREG32(DC_HPD1_INT_CONTROL, hpd1);
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WREG32(DC_HPD2_INT_CONTROL, hpd2);
|
||||
WREG32(DC_HPD3_INT_CONTROL, hpd3);
|
||||
WREG32(DC_HPD4_INT_CONTROL, hpd4);
|
||||
if (ASIC_IS_DCE32(rdev)) {
|
||||
WREG32(DC_HPD5_INT_CONTROL, hpd5);
|
||||
WREG32(DC_HPD6_INT_CONTROL, hpd6);
|
||||
}
|
||||
} else {
|
||||
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
|
||||
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
|
||||
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void r600_irq_ack(struct radeon_device *rdev, u32 disp_int)
|
||||
static inline void r600_irq_ack(struct radeon_device *rdev,
|
||||
u32 *disp_int,
|
||||
u32 *disp_int_cont,
|
||||
u32 *disp_int_cont2)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
if (disp_int & LB_D1_VBLANK_INTERRUPT)
|
||||
if (ASIC_IS_DCE3(rdev)) {
|
||||
*disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
|
||||
*disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
|
||||
*disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
|
||||
} else {
|
||||
*disp_int = RREG32(DISP_INTERRUPT_STATUS);
|
||||
*disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
|
||||
*disp_int_cont2 = 0;
|
||||
}
|
||||
|
||||
if (*disp_int & LB_D1_VBLANK_INTERRUPT)
|
||||
WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
|
||||
if (disp_int & LB_D1_VLINE_INTERRUPT)
|
||||
if (*disp_int & LB_D1_VLINE_INTERRUPT)
|
||||
WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
|
||||
if (disp_int & LB_D2_VBLANK_INTERRUPT)
|
||||
if (*disp_int & LB_D2_VBLANK_INTERRUPT)
|
||||
WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
|
||||
if (disp_int & LB_D2_VLINE_INTERRUPT)
|
||||
if (*disp_int & LB_D2_VLINE_INTERRUPT)
|
||||
WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
|
||||
|
||||
if (*disp_int & DC_HPD1_INTERRUPT) {
|
||||
if (ASIC_IS_DCE3(rdev)) {
|
||||
tmp = RREG32(DC_HPD1_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD1_INT_CONTROL, tmp);
|
||||
} else {
|
||||
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
|
||||
}
|
||||
}
|
||||
if (*disp_int & DC_HPD2_INTERRUPT) {
|
||||
if (ASIC_IS_DCE3(rdev)) {
|
||||
tmp = RREG32(DC_HPD2_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD2_INT_CONTROL, tmp);
|
||||
} else {
|
||||
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
|
||||
}
|
||||
}
|
||||
if (*disp_int_cont & DC_HPD3_INTERRUPT) {
|
||||
if (ASIC_IS_DCE3(rdev)) {
|
||||
tmp = RREG32(DC_HPD3_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD3_INT_CONTROL, tmp);
|
||||
} else {
|
||||
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
|
||||
}
|
||||
}
|
||||
if (*disp_int_cont & DC_HPD4_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD4_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD4_INT_CONTROL, tmp);
|
||||
}
|
||||
if (ASIC_IS_DCE32(rdev)) {
|
||||
if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD5_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD5_INT_CONTROL, tmp);
|
||||
}
|
||||
if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
|
||||
tmp = RREG32(DC_HPD5_INT_CONTROL);
|
||||
tmp |= DC_HPDx_INT_ACK;
|
||||
WREG32(DC_HPD6_INT_CONTROL, tmp);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void r600_irq_disable(struct radeon_device *rdev)
|
||||
{
|
||||
u32 disp_int;
|
||||
u32 disp_int, disp_int_cont, disp_int_cont2;
|
||||
|
||||
r600_disable_interrupts(rdev);
|
||||
/* Wait and acknowledge irq */
|
||||
mdelay(1);
|
||||
if (ASIC_IS_DCE3(rdev))
|
||||
disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
|
||||
else
|
||||
disp_int = RREG32(DISP_INTERRUPT_STATUS);
|
||||
r600_irq_ack(rdev, disp_int);
|
||||
r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
|
||||
r600_disable_interrupt_state(rdev);
|
||||
}
|
||||
|
||||
static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
|
||||
@ -2249,7 +2672,7 @@ int r600_irq_process(struct radeon_device *rdev)
|
||||
u32 rptr = rdev->ih.rptr;
|
||||
u32 src_id, src_data;
|
||||
u32 last_entry = rdev->ih.ring_size - 16;
|
||||
u32 ring_index, disp_int;
|
||||
u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
|
||||
unsigned long flags;
|
||||
|
||||
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
|
||||
@ -2267,11 +2690,7 @@ int r600_irq_process(struct radeon_device *rdev)
|
||||
|
||||
restart_ih:
|
||||
/* display interrupts */
|
||||
if (ASIC_IS_DCE3(rdev))
|
||||
disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
|
||||
else
|
||||
disp_int = RREG32(DISP_INTERRUPT_STATUS);
|
||||
r600_irq_ack(rdev, disp_int);
|
||||
r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
|
||||
|
||||
rdev->ih.wptr = wptr;
|
||||
while (rptr != wptr) {
|
||||
@ -2321,6 +2740,49 @@ restart_ih:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 19: /* HPD/DAC hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
if (disp_int & DC_HPD1_INTERRUPT) {
|
||||
disp_int &= ~DC_HPD1_INTERRUPT;
|
||||
DRM_INFO("IH: HPD1\n");
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (disp_int & DC_HPD2_INTERRUPT) {
|
||||
disp_int &= ~DC_HPD2_INTERRUPT;
|
||||
DRM_INFO("IH: HPD2\n");
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
if (disp_int_cont & DC_HPD3_INTERRUPT) {
|
||||
disp_int_cont &= ~DC_HPD3_INTERRUPT;
|
||||
DRM_INFO("IH: HPD3\n");
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
if (disp_int_cont & DC_HPD4_INTERRUPT) {
|
||||
disp_int_cont &= ~DC_HPD4_INTERRUPT;
|
||||
DRM_INFO("IH: HPD4\n");
|
||||
}
|
||||
break;
|
||||
case 10:
|
||||
if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
|
||||
disp_int_cont &= ~DC_HPD5_INTERRUPT;
|
||||
DRM_INFO("IH: HPD5\n");
|
||||
}
|
||||
break;
|
||||
case 12:
|
||||
if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
|
||||
disp_int_cont &= ~DC_HPD6_INTERRUPT;
|
||||
DRM_INFO("IH: HPD6\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 176: /* CP_INT in ring buffer */
|
||||
case 177: /* CP_INT in IB1 */
|
||||
case 178: /* CP_INT in IB2 */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user