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riscv: dts: starfive: Add USB dts node for JH7110

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Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Minda Chen 2023-07-26 03:06:09 -07:00 committed by Conor Dooley
parent c2a10081c0
commit e126aa3abc
2 changed files with 37 additions and 0 deletions
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5
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -273,6 +273,11 @@
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&U74_1 {
cpu-supply = <&vdd_cpu>;
};

32
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -446,6 +446,38 @@
status = "disabled";
};
usb0: usb@10100000 {
compatible = "starfive,jh7110-usb";
ranges = <0x0 0x0 0x10100000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
starfive,stg-syscon = <&stg_syscon 0x4>;
clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
<&stgcrg JH7110_STGCLK_USB0_STB>,
<&stgcrg JH7110_STGCLK_USB0_APB>,
<&stgcrg JH7110_STGCLK_USB0_AXI>,
<&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
<&stgcrg JH7110_STGRST_USB0_APB>,
<&stgcrg JH7110_STGRST_USB0_AXI>,
<&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
reset-names = "pwrup", "apb", "axi", "utmi_apb";
status = "disabled";
usb_cdns3: usb@0 {
compatible = "cdns,usb3";
reg = <0x0 0x10000>,
<0x10000 0x10000>,
<0x20000 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <100>, <108>, <110>;
interrupt-names = "host", "peripheral", "otg";
phys = <&usbphy0>;
phy-names = "cdns3,usb2-phy";
};
};
usbphy0: phy@10200000 {
compatible = "starfive,jh7110-usb-phy";
reg = <0x0 0x10200000 0x0 0x10000>;