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drm/xe/guc_pc: Move gt register to the proper place

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Move a few defines from xe_guc_pc.c to the right register, now that
there is one: xe_gt_regs.h.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-02-24 16:15:44 -08:00 committed by Rodrigo Vivi
parent c584148145
commit e12ef39272
2 changed files with 2 additions and 6 deletions
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2
drivers/gpu/drm/xe/regs/xe_gt_regs.h
View File

@ -187,6 +187,7 @@
#define DFR_DISABLE (1 << 9)
#define GEN6_RPNSWREQ _MMIO(0xa008)
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
#define GEN6_RC_CONTROL _MMIO(0xa090)
#define GEN6_RC_STATE _MMIO(0xa094)
@ -243,6 +244,7 @@
#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
#define RCN_MASK REG_GENMASK(2, 0)
#define GEN6_RC0 0
#define GEN6_RC6 3

6
drivers/gpu/drm/xe/xe_guc_pc.c
View File

@ -31,12 +31,6 @@
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
#define RPE_MASK REG_GENMASK(15, 8)
/* For GEN6_RPNSWREQ.reg to be merged when the definition moves to Xe */
#define REQ_RATIO_MASK REG_GENMASK(31, 23)
/* For GEN6_GT_CORE_STATUS.reg to be merged when the definition moves to Xe */
#define RCN_MASK REG_GENMASK(2, 0)
#define GEN12_RPSTAT1 _MMIO(0x1381b4)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)