clk: samsung: exynos850: Implement CMU_G3D domain
CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for
BLK_G3D.
This patch adds next clocks:
- bus clocks in CMU_TOP for CMU_G3D
- all internal CMU_G3D clocks
- leaf clocks for GPU, TZPC (TrustZone Protection Controller) and
SysReg
G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-5-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Sam Protsenko
Krzysztof Kozlowski
parent
f2819ea168
commit
e145c76507
@ -36,6 +36,7 @@
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
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#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
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#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
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#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
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@ -57,6 +58,7 @@
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#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
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#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
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#define CLK_CON_DIV_CLKCMU_DPU 0x1840
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#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
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#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
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#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
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#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
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@ -84,6 +86,7 @@
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
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#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
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#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
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#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
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@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = {
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CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
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CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
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CLK_CON_MUX_MUX_CLKCMU_DPU,
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CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
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CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
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CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
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@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = {
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CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
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CLK_CON_DIV_CLKCMU_CORE_SSS,
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CLK_CON_DIV_CLKCMU_DPU,
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CLK_CON_DIV_CLKCMU_G3D_SWITCH,
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CLK_CON_DIV_CLKCMU_HSI_BUS,
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CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
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CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
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@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = {
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CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
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CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
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CLK_CON_GAT_GATE_CLKCMU_DPU,
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CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
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CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
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CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
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CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
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@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
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"oscclk", "oscclk" };
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PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
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"dout_shared0_div4", "dout_shared1_div4" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
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PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
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"dout_shared0_div3", "dout_shared1_div3" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
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PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
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PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
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@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
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MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
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CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
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/* G3D */
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MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
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CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
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/* HSI */
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MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
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CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
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@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
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DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
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CLK_CON_DIV_CLKCMU_DPU, 0, 4),
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/* G3D */
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DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
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CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
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/* HSI */
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DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
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CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
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@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
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CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
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/* G3D */
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GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
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CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
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/* HSI */
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GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
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CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
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@ -992,6 +1013,102 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
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.clk_name = "gout_clkcmu_cmgp_bus",
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};
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/* ---- CMU_G3D ------------------------------------------------------------- */
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/* Register Offset definitions for CMU_G3D (0x11400000) */
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#define PLL_LOCKTIME_PLL_G3D 0x0000
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#define PLL_CON0_PLL_G3D 0x0100
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#define PLL_CON3_PLL_G3D 0x010c
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#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
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#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
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#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
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#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
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#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
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#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
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#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
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#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
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#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
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#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
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static const unsigned long g3d_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_G3D,
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PLL_CON0_PLL_G3D,
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PLL_CON3_PLL_G3D,
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PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
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CLK_CON_MUX_MUX_CLK_G3D_BUSD,
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CLK_CON_DIV_DIV_CLK_G3D_BUSP,
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CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
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CLK_CON_GAT_CLK_G3D_GPU_CLK,
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CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
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CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
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CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
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CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
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CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
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};
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/* List of parent clocks for Muxes in CMU_G3D */
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PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
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PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
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PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
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/*
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* Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
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* for that PLL by default, so set_rate operation would fail.
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*/
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static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
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PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
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PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
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};
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static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
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MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
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PLL_CON0_PLL_G3D, 4, 1),
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MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
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mout_g3d_switch_user_p,
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PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
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MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
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CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
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};
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static const struct samsung_div_clock g3d_div_clks[] __initconst = {
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DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
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CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
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};
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static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
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GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
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"dout_g3d_busp",
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CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
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CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
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GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
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CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
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GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
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"mout_g3d_busd",
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CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
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GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
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CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
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GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
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CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
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GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
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CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
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};
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static const struct samsung_cmu_info g3d_cmu_info __initconst = {
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.pll_clks = g3d_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
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.mux_clks = g3d_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
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.div_clks = g3d_div_clks,
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.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
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.gate_clks = g3d_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
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.nr_clk_ids = G3D_NR_CLK,
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.clk_regs = g3d_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
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.clk_name = "dout_g3d_switch",
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};
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/* ---- CMU_HSI ------------------------------------------------------------- */
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/* Register Offset definitions for CMU_HSI (0x13400000) */
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@ -1700,6 +1817,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
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}, {
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.compatible = "samsung,exynos850-cmu-cmgp",
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.data = &cmgp_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-g3d",
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.data = &g3d_cmu_info,
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}, {
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.compatible = "samsung,exynos850-cmu-hsi",
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.data = &hsi_cmu_info,
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