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mlxsw: reg: Add Switch FID Flooding Profiles Register

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The SFFP register populates the fid flooding profile tables used for the
NVE flooding and Compressed-FID Flooding (CFF).

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/ca42eb67763bd0c7cf035afc62ef73632f3f61a6.1700503643.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Petr Machata 2023-11-20 19:25:21 +01:00 committed by Jakub Kicinski
parent 2d19da9277
commit e1e4ce6c6d
1 changed files with 45 additions and 0 deletions
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45
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -2168,6 +2168,50 @@ static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
mlxsw_reg_spvc_et0_set(payload, et0);
}
/* SFFP - Switch FID Flooding Profiles Register
* --------------------------------------------
* The SFFP register populates the fid flooding profile tables used for the NVE
* flooding and Compressed-FID Flooding (CFF).
*
* Reserved on Spectrum-1.
*/
#define MLXSW_REG_SFFP_ID 0x2029
#define MLXSW_REG_SFFP_LEN 0x0C
MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN);
/* reg_sffp_profile_id
* Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id
* Range 0..max_cap_nve_flood_prf-1
* Access: Index
*/
MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);
/* reg_sffp_type
* The traffic type to reach the flooding table.
* Same as SFGC.type
* Access: Index
*/
MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);
/* reg_sffp_flood_offset
* Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address
* for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD
* pointer for NVE underlay.
* Access: RW
*/
MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);
static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id,
enum mlxsw_reg_sfgc_type type,
u8 flood_offset)
{
MLXSW_REG_ZERO(sffp, payload);
mlxsw_reg_sffp_profile_id_set(payload, profile_id);
mlxsw_reg_sffp_type_set(payload, type);
mlxsw_reg_sffp_flood_offset_set(payload, flood_offset);
}
/* SPEVET - Switch Port Egress VLAN EtherType
* ------------------------------------------
* The switch port egress VLAN EtherType configures which EtherType to push at
@ -12946,6 +12990,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(spvmlr),
MLXSW_REG(spfsr),
MLXSW_REG(spvc),
MLXSW_REG(sffp),
MLXSW_REG(spevet),
MLXSW_REG(smpe),
MLXSW_REG(smid2),