mtd: rawnand: omap2: convert driver to nand_scan()
Two helpers have been added to the core to do all kind of controller side configuration/initialization between the detection phase and the final NAND scan. Implement these hooks so that we can convert the driver to just use nand_scan() instead of the nand_scan_ident() + nand_scan_tail() pair. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
This commit is contained in:
Miquel Raynal
parent
c49f3bee8c
commit
e1e6255c31
@ -144,12 +144,6 @@ static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
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0xac, 0x6b, 0xff, 0x99, 0x7b};
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static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
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/* Shared among all NAND instances to synchronize access to the ECC Engine */
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static struct nand_controller omap_gpmc_controller = {
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.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
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.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
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};
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struct omap_nand_info {
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struct nand_chip nand;
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struct platform_device *pdev;
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@ -1915,17 +1909,278 @@ static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = {
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.free = omap_sw_ooblayout_free,
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};
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static int omap_nand_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct omap_nand_info *info = mtd_to_omap(mtd);
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struct device *dev = &info->pdev->dev;
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int min_oobbytes = BADBLOCK_MARKER_LENGTH;
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int oobbytes_per_step;
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dma_cap_mask_t mask;
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int err;
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if (chip->bbt_options & NAND_BBT_USE_FLASH)
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chip->bbt_options |= NAND_BBT_NO_OOB;
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else
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chip->options |= NAND_SKIP_BBTSCAN;
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/* Re-populate low-level callbacks based on xfer modes */
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switch (info->xfer_type) {
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case NAND_OMAP_PREFETCH_POLLED:
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chip->read_buf = omap_read_buf_pref;
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chip->write_buf = omap_write_buf_pref;
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break;
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case NAND_OMAP_POLLED:
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/* Use nand_base defaults for {read,write}_buf */
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break;
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case NAND_OMAP_PREFETCH_DMA:
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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info->dma = dma_request_chan(dev, "rxtx");
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if (IS_ERR(info->dma)) {
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dev_err(dev, "DMA engine request failed\n");
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return PTR_ERR(info->dma);
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} else {
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struct dma_slave_config cfg;
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memset(&cfg, 0, sizeof(cfg));
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cfg.src_addr = info->phys_base;
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cfg.dst_addr = info->phys_base;
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.src_maxburst = 16;
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cfg.dst_maxburst = 16;
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err = dmaengine_slave_config(info->dma, &cfg);
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if (err) {
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dev_err(dev,
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"DMA engine slave config failed: %d\n",
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err);
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return err;
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}
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chip->read_buf = omap_read_buf_dma_pref;
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chip->write_buf = omap_write_buf_dma_pref;
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}
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break;
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case NAND_OMAP_PREFETCH_IRQ:
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info->gpmc_irq_fifo = platform_get_irq(info->pdev, 0);
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if (info->gpmc_irq_fifo <= 0) {
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dev_err(dev, "Error getting fifo IRQ\n");
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return -ENODEV;
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}
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err = devm_request_irq(dev, info->gpmc_irq_fifo,
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omap_nand_irq, IRQF_SHARED,
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"gpmc-nand-fifo", info);
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if (err) {
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dev_err(dev, "Requesting IRQ %d, error %d\n",
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info->gpmc_irq_fifo, err);
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info->gpmc_irq_fifo = 0;
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return err;
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}
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info->gpmc_irq_count = platform_get_irq(info->pdev, 1);
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if (info->gpmc_irq_count <= 0) {
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dev_err(dev, "Error getting IRQ count\n");
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return -ENODEV;
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}
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err = devm_request_irq(dev, info->gpmc_irq_count,
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omap_nand_irq, IRQF_SHARED,
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"gpmc-nand-count", info);
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if (err) {
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dev_err(dev, "Requesting IRQ %d, error %d\n",
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info->gpmc_irq_count, err);
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info->gpmc_irq_count = 0;
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return err;
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}
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chip->read_buf = omap_read_buf_irq_pref;
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chip->write_buf = omap_write_buf_irq_pref;
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break;
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default:
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dev_err(dev, "xfer_type %d not supported!\n", info->xfer_type);
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return -EINVAL;
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}
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if (!omap2_nand_ecc_check(info))
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return -EINVAL;
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/*
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* Bail out earlier to let NAND_ECC_SOFT code create its own
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* ooblayout instead of using ours.
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*/
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if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->ecc.algo = NAND_ECC_HAMMING;
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return 0;
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}
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/* Populate MTD interface based on ECC scheme */
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switch (info->ecc_opt) {
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case OMAP_ECC_HAM1_CODE_HW:
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dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.bytes = 3;
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chip->ecc.size = 512;
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chip->ecc.strength = 1;
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chip->ecc.calculate = omap_calculate_ecc;
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chip->ecc.hwctl = omap_enable_hwecc;
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chip->ecc.correct = omap_correct_data;
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mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
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oobbytes_per_step = chip->ecc.bytes;
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if (!(chip->options & NAND_BUSWIDTH_16))
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min_oobbytes = 1;
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break;
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case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
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pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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chip->ecc.bytes = 7;
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chip->ecc.strength = 4;
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chip->ecc.hwctl = omap_enable_hwecc_bch;
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chip->ecc.correct = nand_bch_correct_data;
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chip->ecc.calculate = omap_calculate_ecc_bch_sw;
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mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
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/* Reserve one byte for the OMAP marker */
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oobbytes_per_step = chip->ecc.bytes + 1;
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/* Software BCH library is used for locating errors */
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chip->ecc.priv = nand_bch_init(mtd);
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if (!chip->ecc.priv) {
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dev_err(dev, "Unable to use BCH library\n");
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return -EINVAL;
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}
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break;
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case OMAP_ECC_BCH4_CODE_HW:
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pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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/* 14th bit is kept reserved for ROM-code compatibility */
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chip->ecc.bytes = 7 + 1;
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chip->ecc.strength = 4;
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chip->ecc.hwctl = omap_enable_hwecc_bch;
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chip->ecc.correct = omap_elm_correct_data;
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chip->ecc.read_page = omap_read_page_bch;
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chip->ecc.write_page = omap_write_page_bch;
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chip->ecc.write_subpage = omap_write_subpage_bch;
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mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
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oobbytes_per_step = chip->ecc.bytes;
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err = elm_config(info->elm_dev, BCH4_ECC,
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mtd->writesize / chip->ecc.size,
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chip->ecc.size, chip->ecc.bytes);
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if (err < 0)
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return err;
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break;
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case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
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pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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chip->ecc.bytes = 13;
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chip->ecc.strength = 8;
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chip->ecc.hwctl = omap_enable_hwecc_bch;
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chip->ecc.correct = nand_bch_correct_data;
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chip->ecc.calculate = omap_calculate_ecc_bch_sw;
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mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
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/* Reserve one byte for the OMAP marker */
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oobbytes_per_step = chip->ecc.bytes + 1;
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/* Software BCH library is used for locating errors */
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chip->ecc.priv = nand_bch_init(mtd);
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if (!chip->ecc.priv) {
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dev_err(dev, "unable to use BCH library\n");
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return -EINVAL;
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}
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break;
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case OMAP_ECC_BCH8_CODE_HW:
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pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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/* 14th bit is kept reserved for ROM-code compatibility */
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chip->ecc.bytes = 13 + 1;
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chip->ecc.strength = 8;
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chip->ecc.hwctl = omap_enable_hwecc_bch;
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chip->ecc.correct = omap_elm_correct_data;
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chip->ecc.read_page = omap_read_page_bch;
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chip->ecc.write_page = omap_write_page_bch;
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chip->ecc.write_subpage = omap_write_subpage_bch;
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mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
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oobbytes_per_step = chip->ecc.bytes;
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err = elm_config(info->elm_dev, BCH8_ECC,
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mtd->writesize / chip->ecc.size,
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chip->ecc.size, chip->ecc.bytes);
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if (err < 0)
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return err;
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break;
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case OMAP_ECC_BCH16_CODE_HW:
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pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 512;
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chip->ecc.bytes = 26;
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chip->ecc.strength = 16;
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chip->ecc.hwctl = omap_enable_hwecc_bch;
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chip->ecc.correct = omap_elm_correct_data;
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chip->ecc.read_page = omap_read_page_bch;
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chip->ecc.write_page = omap_write_page_bch;
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chip->ecc.write_subpage = omap_write_subpage_bch;
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mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
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oobbytes_per_step = chip->ecc.bytes;
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err = elm_config(info->elm_dev, BCH16_ECC,
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mtd->writesize / chip->ecc.size,
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chip->ecc.size, chip->ecc.bytes);
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if (err < 0)
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return err;
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break;
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default:
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dev_err(dev, "Invalid or unsupported ECC scheme\n");
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return -EINVAL;
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}
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/* Check if NAND device's OOB is enough to store ECC signatures */
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min_oobbytes += (oobbytes_per_step *
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(mtd->writesize / chip->ecc.size));
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if (mtd->oobsize < min_oobbytes) {
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dev_err(dev,
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"Not enough OOB bytes: required = %d, available=%d\n",
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min_oobbytes, mtd->oobsize);
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return -EINVAL;
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}
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return 0;
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}
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static const struct nand_controller_ops omap_nand_controller_ops = {
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.attach_chip = omap_nand_attach_chip,
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};
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/* Shared among all NAND instances to synchronize access to the ECC Engine */
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static struct nand_controller omap_gpmc_controller = {
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.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
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.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
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.ops = &omap_nand_controller_ops,
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};
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static int omap_nand_probe(struct platform_device *pdev)
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{
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struct omap_nand_info *info;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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int err;
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dma_cap_mask_t mask;
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struct resource *res;
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struct device *dev = &pdev->dev;
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int min_oobbytes = BADBLOCK_MARKER_LENGTH;
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int oobbytes_per_step;
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info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
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GFP_KERNEL);
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@ -1998,266 +2253,8 @@ static int omap_nand_probe(struct platform_device *pdev)
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/* scan NAND device connected to chip controller */
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nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
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err = nand_scan_ident(mtd, 1, NULL);
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if (err) {
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dev_err(&info->pdev->dev,
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"scan failed, may be bus-width mismatch\n");
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goto return_error;
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}
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if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
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nand_chip->bbt_options |= NAND_BBT_NO_OOB;
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else
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nand_chip->options |= NAND_SKIP_BBTSCAN;
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/* re-populate low-level callbacks based on xfer modes */
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switch (info->xfer_type) {
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case NAND_OMAP_PREFETCH_POLLED:
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nand_chip->read_buf = omap_read_buf_pref;
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nand_chip->write_buf = omap_write_buf_pref;
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break;
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case NAND_OMAP_POLLED:
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/* Use nand_base defaults for {read,write}_buf */
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break;
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case NAND_OMAP_PREFETCH_DMA:
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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info->dma = dma_request_chan(pdev->dev.parent, "rxtx");
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if (IS_ERR(info->dma)) {
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dev_err(&pdev->dev, "DMA engine request failed\n");
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err = PTR_ERR(info->dma);
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goto return_error;
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} else {
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struct dma_slave_config cfg;
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memset(&cfg, 0, sizeof(cfg));
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cfg.src_addr = info->phys_base;
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cfg.dst_addr = info->phys_base;
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cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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cfg.src_maxburst = 16;
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cfg.dst_maxburst = 16;
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err = dmaengine_slave_config(info->dma, &cfg);
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if (err) {
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dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
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err);
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goto return_error;
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}
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nand_chip->read_buf = omap_read_buf_dma_pref;
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nand_chip->write_buf = omap_write_buf_dma_pref;
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}
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break;
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case NAND_OMAP_PREFETCH_IRQ:
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info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
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if (info->gpmc_irq_fifo <= 0) {
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dev_err(&pdev->dev, "error getting fifo irq\n");
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err = -ENODEV;
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goto return_error;
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}
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err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
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omap_nand_irq, IRQF_SHARED,
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"gpmc-nand-fifo", info);
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if (err) {
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dev_err(&pdev->dev, "requesting irq(%d) error:%d",
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info->gpmc_irq_fifo, err);
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info->gpmc_irq_fifo = 0;
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goto return_error;
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}
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info->gpmc_irq_count = platform_get_irq(pdev, 1);
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if (info->gpmc_irq_count <= 0) {
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dev_err(&pdev->dev, "error getting count irq\n");
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err = -ENODEV;
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goto return_error;
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}
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err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
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omap_nand_irq, IRQF_SHARED,
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"gpmc-nand-count", info);
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if (err) {
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dev_err(&pdev->dev, "requesting irq(%d) error:%d",
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info->gpmc_irq_count, err);
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info->gpmc_irq_count = 0;
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goto return_error;
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}
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nand_chip->read_buf = omap_read_buf_irq_pref;
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nand_chip->write_buf = omap_write_buf_irq_pref;
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break;
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default:
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dev_err(&pdev->dev,
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"xfer_type(%d) not supported!\n", info->xfer_type);
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err = -EINVAL;
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goto return_error;
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}
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if (!omap2_nand_ecc_check(info)) {
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err = -EINVAL;
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goto return_error;
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}
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/*
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* Bail out earlier to let NAND_ECC_SOFT code create its own
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* ooblayout instead of using ours.
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*/
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if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
|
||||
nand_chip->ecc.mode = NAND_ECC_SOFT;
|
||||
nand_chip->ecc.algo = NAND_ECC_HAMMING;
|
||||
goto scan_tail;
|
||||
}
|
||||
|
||||
/* populate MTD interface based on ECC scheme */
|
||||
switch (info->ecc_opt) {
|
||||
case OMAP_ECC_HAM1_CODE_HW:
|
||||
pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.bytes = 3;
|
||||
nand_chip->ecc.size = 512;
|
||||
nand_chip->ecc.strength = 1;
|
||||
nand_chip->ecc.calculate = omap_calculate_ecc;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc;
|
||||
nand_chip->ecc.correct = omap_correct_data;
|
||||
mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
|
||||
oobbytes_per_step = nand_chip->ecc.bytes;
|
||||
|
||||
if (!(nand_chip->options & NAND_BUSWIDTH_16))
|
||||
min_oobbytes = 1;
|
||||
|
||||
break;
|
||||
|
||||
case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
|
||||
pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.size = 512;
|
||||
nand_chip->ecc.bytes = 7;
|
||||
nand_chip->ecc.strength = 4;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
|
||||
nand_chip->ecc.correct = nand_bch_correct_data;
|
||||
nand_chip->ecc.calculate = omap_calculate_ecc_bch_sw;
|
||||
mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
|
||||
/* Reserve one byte for the OMAP marker */
|
||||
oobbytes_per_step = nand_chip->ecc.bytes + 1;
|
||||
/* software bch library is used for locating errors */
|
||||
nand_chip->ecc.priv = nand_bch_init(mtd);
|
||||
if (!nand_chip->ecc.priv) {
|
||||
dev_err(&info->pdev->dev, "unable to use BCH library\n");
|
||||
err = -EINVAL;
|
||||
goto return_error;
|
||||
}
|
||||
break;
|
||||
|
||||
case OMAP_ECC_BCH4_CODE_HW:
|
||||
pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.size = 512;
|
||||
/* 14th bit is kept reserved for ROM-code compatibility */
|
||||
nand_chip->ecc.bytes = 7 + 1;
|
||||
nand_chip->ecc.strength = 4;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
|
||||
nand_chip->ecc.correct = omap_elm_correct_data;
|
||||
nand_chip->ecc.read_page = omap_read_page_bch;
|
||||
nand_chip->ecc.write_page = omap_write_page_bch;
|
||||
nand_chip->ecc.write_subpage = omap_write_subpage_bch;
|
||||
mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
|
||||
oobbytes_per_step = nand_chip->ecc.bytes;
|
||||
|
||||
err = elm_config(info->elm_dev, BCH4_ECC,
|
||||
mtd->writesize / nand_chip->ecc.size,
|
||||
nand_chip->ecc.size, nand_chip->ecc.bytes);
|
||||
if (err < 0)
|
||||
goto return_error;
|
||||
break;
|
||||
|
||||
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
|
||||
pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.size = 512;
|
||||
nand_chip->ecc.bytes = 13;
|
||||
nand_chip->ecc.strength = 8;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
|
||||
nand_chip->ecc.correct = nand_bch_correct_data;
|
||||
nand_chip->ecc.calculate = omap_calculate_ecc_bch_sw;
|
||||
mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops);
|
||||
/* Reserve one byte for the OMAP marker */
|
||||
oobbytes_per_step = nand_chip->ecc.bytes + 1;
|
||||
/* software bch library is used for locating errors */
|
||||
nand_chip->ecc.priv = nand_bch_init(mtd);
|
||||
if (!nand_chip->ecc.priv) {
|
||||
dev_err(&info->pdev->dev, "unable to use BCH library\n");
|
||||
err = -EINVAL;
|
||||
goto return_error;
|
||||
}
|
||||
break;
|
||||
|
||||
case OMAP_ECC_BCH8_CODE_HW:
|
||||
pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.size = 512;
|
||||
/* 14th bit is kept reserved for ROM-code compatibility */
|
||||
nand_chip->ecc.bytes = 13 + 1;
|
||||
nand_chip->ecc.strength = 8;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
|
||||
nand_chip->ecc.correct = omap_elm_correct_data;
|
||||
nand_chip->ecc.read_page = omap_read_page_bch;
|
||||
nand_chip->ecc.write_page = omap_write_page_bch;
|
||||
nand_chip->ecc.write_subpage = omap_write_subpage_bch;
|
||||
mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
|
||||
oobbytes_per_step = nand_chip->ecc.bytes;
|
||||
|
||||
err = elm_config(info->elm_dev, BCH8_ECC,
|
||||
mtd->writesize / nand_chip->ecc.size,
|
||||
nand_chip->ecc.size, nand_chip->ecc.bytes);
|
||||
if (err < 0)
|
||||
goto return_error;
|
||||
|
||||
break;
|
||||
|
||||
case OMAP_ECC_BCH16_CODE_HW:
|
||||
pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
|
||||
nand_chip->ecc.mode = NAND_ECC_HW;
|
||||
nand_chip->ecc.size = 512;
|
||||
nand_chip->ecc.bytes = 26;
|
||||
nand_chip->ecc.strength = 16;
|
||||
nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
|
||||
nand_chip->ecc.correct = omap_elm_correct_data;
|
||||
nand_chip->ecc.read_page = omap_read_page_bch;
|
||||
nand_chip->ecc.write_page = omap_write_page_bch;
|
||||
nand_chip->ecc.write_subpage = omap_write_subpage_bch;
|
||||
mtd_set_ooblayout(mtd, &omap_ooblayout_ops);
|
||||
oobbytes_per_step = nand_chip->ecc.bytes;
|
||||
|
||||
err = elm_config(info->elm_dev, BCH16_ECC,
|
||||
mtd->writesize / nand_chip->ecc.size,
|
||||
nand_chip->ecc.size, nand_chip->ecc.bytes);
|
||||
if (err < 0)
|
||||
goto return_error;
|
||||
|
||||
break;
|
||||
default:
|
||||
dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
|
||||
err = -EINVAL;
|
||||
goto return_error;
|
||||
}
|
||||
|
||||
/* check if NAND device's OOB is enough to store ECC signatures */
|
||||
min_oobbytes += (oobbytes_per_step *
|
||||
(mtd->writesize / nand_chip->ecc.size));
|
||||
if (mtd->oobsize < min_oobbytes) {
|
||||
dev_err(&info->pdev->dev,
|
||||
"not enough OOB bytes required = %d, available=%d\n",
|
||||
min_oobbytes, mtd->oobsize);
|
||||
err = -EINVAL;
|
||||
goto return_error;
|
||||
}
|
||||
|
||||
scan_tail:
|
||||
/* second phase scan */
|
||||
err = nand_scan_tail(mtd);
|
||||
err = nand_scan(mtd, 1);
|
||||
if (err)
|
||||
goto return_error;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user