net/mlx5e: RX, Avoid possible data corruption when relaxed ordering and LRO combined
When HW aggregates packets for an LRO session, it writes the payload of two consecutive packets of a flow contiguously, so that they usually share a cacheline. The first byte of a packet's payload is written immediately after the last byte of the preceding packet. In this flow, there are two consecutive write requests to the shared cacheline: 1. Regular write for the earlier packet. 2. Read-modify-write for the following packet. In case of relaxed-ordering on, these two writes might be re-ordered. Using the end padding optimization (to avoid partial write for the last cacheline of a packet) becomes problematic if the two writes occur out-of-order, as the padding would overwrite payload that belongs to the following packet, causing data corruption. Avoid this by disabling the end padding optimization when both LRO and relaxed-ordering are enabled. Fixes: 17347d5430c4 ("net/mlx5e: Add support for PCI relaxed ordering") Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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@ -471,6 +471,15 @@ static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev,
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param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
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}
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static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
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{
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bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) &&
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MLX5_CAP_GEN(mdev, relaxed_ordering_write);
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return ro && params->lro_en ?
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MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN;
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}
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int mlx5e_build_rq_param(struct mlx5_core_dev *mdev,
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struct mlx5e_params *params,
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struct mlx5e_xsk_param *xsk,
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@ -508,7 +517,7 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev,
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}
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MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
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MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
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MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params));
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MLX5_SET(wq, wq, log_wq_stride,
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mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
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MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn);
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