Merge patch series "riscv: cbo.zero fixes"
Samuel Holland <samuel.holland@sifive.com> says: This series fixes a couple of issues related to using the cbo.zero instruction in userspace. The first patch fixes a bug where the wrong enable bit gets set if the kernel is running in M-mode. The remaining patches fix a bug where the enable bit gets reset to its default value after a nonretentive idle state. I have hardware which reproduces this: Before this series: $ tools/testing/selftests/riscv/hwprobe/cbo TAP version 13 1..3 ok 1 Zicboz block size # Zicboz block size: 64 Illegal instruction After applying this series: $ tools/testing/selftests/riscv/hwprobe/cbo TAP version 13 1..3 ok 1 Zicboz block size # Zicboz block size: 64 ok 2 cbo.zero ok 3 cbo.zero check # Totals: pass:3 fail:0 xfail:0 xpass:0 skip:0 error:0 * b4-shazam-merge: riscv: Save/restore envcfg CSR during CPU suspend riscv: Add a custom ISA extension for the [ms]envcfg CSR riscv: Fix enabling cbo.zero when running in M-mode Link: https://lore.kernel.org/r/20240228065559.3434837-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -424,6 +424,7 @@
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# define CSR_STATUS CSR_MSTATUS
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# define CSR_IE CSR_MIE
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# define CSR_TVEC CSR_MTVEC
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# define CSR_ENVCFG CSR_MENVCFG
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# define CSR_SCRATCH CSR_MSCRATCH
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# define CSR_EPC CSR_MEPC
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# define CSR_CAUSE CSR_MCAUSE
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@ -448,6 +449,7 @@
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# define CSR_STATUS CSR_SSTATUS
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# define CSR_IE CSR_SIE
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# define CSR_TVEC CSR_STVEC
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# define CSR_ENVCFG CSR_SENVCFG
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# define CSR_SCRATCH CSR_SSCRATCH
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# define CSR_EPC CSR_SEPC
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# define CSR_CAUSE CSR_SCAUSE
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@ -81,6 +81,8 @@
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#define RISCV_ISA_EXT_ZTSO 72
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#define RISCV_ISA_EXT_ZACAS 73
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#define RISCV_ISA_EXT_XLINUXENVCFG 127
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#define RISCV_ISA_EXT_MAX 128
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#define RISCV_ISA_EXT_INVALID U32_MAX
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@ -14,6 +14,7 @@ struct suspend_context {
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struct pt_regs regs;
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/* Saved and restored by high-level functions */
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unsigned long scratch;
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unsigned long envcfg;
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unsigned long tvec;
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unsigned long ie;
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#ifdef CONFIG_MMU
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@ -202,6 +202,16 @@ static const unsigned int riscv_zvbb_exts[] = {
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RISCV_ISA_EXT_ZVKB
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};
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/*
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* While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
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* privileged ISA, the existence of the CSRs is implied by any extension which
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* specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
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* existence of the CSR, and treat it as a subset of those other extensions.
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*/
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static const unsigned int riscv_xlinuxenvcfg_exts[] = {
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RISCV_ISA_EXT_XLINUXENVCFG
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};
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/*
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* The canonical order of ISA extension names in the ISA string is defined in
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* chapter 27 of the unprivileged specification.
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@ -251,8 +261,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
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__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
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__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
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__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
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__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
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__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
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__RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),
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__RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts),
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__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
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__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
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__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
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@ -965,7 +975,7 @@ arch_initcall(check_unaligned_access_all_cpus);
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void riscv_user_isa_enable(void)
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{
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if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
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csr_set(CSR_SENVCFG, ENVCFG_CBZE);
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csr_set(CSR_ENVCFG, ENVCFG_CBZE);
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}
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#ifdef CONFIG_RISCV_ALTERNATIVE
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@ -15,6 +15,8 @@
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void suspend_save_csrs(struct suspend_context *context)
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{
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context->scratch = csr_read(CSR_SCRATCH);
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if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
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context->envcfg = csr_read(CSR_ENVCFG);
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context->tvec = csr_read(CSR_TVEC);
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context->ie = csr_read(CSR_IE);
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@ -36,6 +38,8 @@ void suspend_save_csrs(struct suspend_context *context)
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void suspend_restore_csrs(struct suspend_context *context)
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{
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csr_write(CSR_SCRATCH, context->scratch);
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if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
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csr_write(CSR_ENVCFG, context->envcfg);
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csr_write(CSR_TVEC, context->tvec);
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csr_write(CSR_IE, context->ie);
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