drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon
This patch adds registers for getting DSC encoder capability for a HDMI2.1 PCon. It also addes helper functions to configure DSC between the PCON and HDMI2.1 sink. v2: Corrected offset for DSC encoder bpc and minor changes. Also added helper functions for getting pcon dsc encoder capabilities as suggested by Uma Shankar. v3: Only setting the DSC bits for the Protocol Converter control registers, avoiding overwritining color conversion bits. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> (v2) [Jani: Fixed checkpatch BLOCK_COMMENT_STYLE.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201218103723.30844-7-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal
Jani Nikula
parent
3ce98018c8
commit
e2e16da398
@ -2898,3 +2898,206 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
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}
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}
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EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
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/*
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* drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
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* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
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*
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* Returns true is PCON encoder is DSC 1.2 else returns false.
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*/
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bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
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{
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u8 buf;
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u8 major_v, minor_v;
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buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
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major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
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minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
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if (major_v == 1 && minor_v == 2)
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return true;
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return false;
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}
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EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
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/*
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* drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
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* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
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*
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* Returns maximum no. of slices supported by the PCON DSC Encoder.
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*/
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int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
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{
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u8 slice_cap1, slice_cap2;
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slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
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slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
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if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
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return 24;
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if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
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return 20;
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if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
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return 16;
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if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
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return 12;
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if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
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return 10;
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if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
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return 8;
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if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
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return 6;
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if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
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return 4;
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if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
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return 2;
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if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
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/*
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* drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
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* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
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*
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* Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
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*/
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int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
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{
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u8 buf;
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buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
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return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
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}
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EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
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/*
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* drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
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* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
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*
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* Returns the bpp precision supported by the PCON encoder.
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*/
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int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
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{
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u8 buf;
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buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
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switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
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case DP_PCON_DSC_ONE_16TH_BPP:
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return 16;
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case DP_PCON_DSC_ONE_8TH_BPP:
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return 8;
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case DP_PCON_DSC_ONE_4TH_BPP:
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return 4;
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case DP_PCON_DSC_ONE_HALF_BPP:
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return 2;
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case DP_PCON_DSC_ONE_BPP:
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
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static
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int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
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{
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u8 buf;
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int ret;
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ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
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if (ret < 0)
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return ret;
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buf |= DP_PCON_ENABLE_DSC_ENCODER;
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if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
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buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
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buf |= pps_buf_config << 2;
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}
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ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
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if (ret < 0)
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return ret;
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return 0;
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}
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/**
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* drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
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* for DSC1.2 between PCON & HDMI2.1 sink
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* @aux: DisplayPort AUX channel
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*
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* Returns 0 on success, else returns negative error code.
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*/
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int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
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{
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int ret;
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ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
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if (ret < 0)
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_pcon_pps_default);
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/**
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* drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
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* HDMI sink
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* @aux: DisplayPort AUX channel
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* @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
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*
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* Returns 0 on success, else returns negative error code.
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*/
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int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
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{
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int ret;
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ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
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if (ret < 0)
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return ret;
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ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
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if (ret < 0)
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
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/*
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* drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
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* override registers
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* @aux: DisplayPort AUX channel
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* @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
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* bits_per_pixel.
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*
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* Returns 0 on success, else returns negative error code.
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*/
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int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
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{
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int ret;
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ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
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if (ret < 0)
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return ret;
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ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
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if (ret < 0)
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return ret;
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ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
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if (ret < 0)
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return ret;
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ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
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if (ret < 0)
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
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@ -441,6 +441,84 @@ struct drm_device;
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# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
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# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
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/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
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#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
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#define DP_PCON_DSC_ENCODER 0x092
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# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
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# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
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/* DP-HDMI2.1 PCON DSC Version */
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#define DP_PCON_DSC_VERSION 0x093
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# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
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# define DP_PCON_DSC_MINOR_MASK (0xF << 4)
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# define DP_PCON_DSC_MAJOR_SHIFT 0
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# define DP_PCON_DSC_MINOR_SHIFT 4
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/* DP-HDMI2.1 PCON DSC RC Buffer block size */
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#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
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# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
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# define DP_PCON_DSC_RC_BUF_BLK_1KB 0
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# define DP_PCON_DSC_RC_BUF_BLK_4KB 1
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# define DP_PCON_DSC_RC_BUF_BLK_16KB 2
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# define DP_PCON_DSC_RC_BUF_BLK_64KB 3
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/* DP-HDMI2.1 PCON DSC RC Buffer size */
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#define DP_PCON_DSC_RC_BUF_SIZE 0x095
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/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
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#define DP_PCON_DSC_SLICE_CAP_1 0x096
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# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
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# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
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# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
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# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
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# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
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# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
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# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
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#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
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# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
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# define DP_PCON_DSC_DEPTH_9_BITS 0
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# define DP_PCON_DSC_DEPTH_10_BITS 1
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# define DP_PCON_DSC_DEPTH_11_BITS 2
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# define DP_PCON_DSC_DEPTH_12_BITS 3
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# define DP_PCON_DSC_DEPTH_13_BITS 4
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# define DP_PCON_DSC_DEPTH_14_BITS 5
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# define DP_PCON_DSC_DEPTH_15_BITS 6
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# define DP_PCON_DSC_DEPTH_16_BITS 7
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# define DP_PCON_DSC_DEPTH_8_BITS 8
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#define DP_PCON_DSC_BLOCK_PREDICTION 0x098
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# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
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#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
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# define DP_PCON_DSC_ENC_RGB (0x1 << 0)
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# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
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# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
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# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
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# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
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#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
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# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
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# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
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# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
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#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
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/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
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#define DP_PCON_DSC_SLICE_CAP_2 0x09C
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# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
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# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
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# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
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/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
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#define DP_PCON_DSC_BPP_INCR 0x09E
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# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
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# define DP_PCON_DSC_ONE_16TH_BPP 0
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# define DP_PCON_DSC_ONE_8TH_BPP 1
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# define DP_PCON_DSC_ONE_4TH_BPP 2
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# define DP_PCON_DSC_ONE_HALF_BPP 3
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# define DP_PCON_DSC_ONE_BPP 4
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/* DP Extended DSC Capabilities */
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#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
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#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
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@ -1124,6 +1202,12 @@ struct drm_device;
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# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
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#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
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# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
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# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
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# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
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# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
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# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
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# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
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/* PCON Downstream HDMI ERROR Status per Lane */
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#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
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@ -1135,6 +1219,29 @@ struct drm_device;
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# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
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# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
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/* PCON HDMI CONFIG PPS Override Buffer
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* Valid Offsets to be added to Base : 0-127
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*/
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#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
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/* PCON HDMI CONFIG PPS Override Parameter: Slice height
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* Offset-0 8LSBs of the Slice height.
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* Offset-1 8MSBs of the Slice height.
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*/
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#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
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/* PCON HDMI CONFIG PPS Override Parameter: Slice width
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* Offset-0 8LSBs of the Slice width.
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* Offset-1 8MSBs of the Slice width.
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*/
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#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
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/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
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* Offset-0 8LSBs of the bits_per_pixel.
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* Offset-1 2MSBs of the bits_per_pixel.
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*/
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#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
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/* HDCP 1.3 and HDCP 2.2 */
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#define DP_AUX_HDCP_BKSV 0x68000
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#define DP_AUX_HDCP_RI_PRIME 0x68005
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@ -2053,5 +2160,12 @@ bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
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int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
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void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
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struct drm_connector *connector);
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bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
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int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
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int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
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int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
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int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
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int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
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int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
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#endif /* _DRM_DP_HELPER_H_ */
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