drm/amdgpu: rework lock handling for flush_tlb v2
Instead of each implementation doing this more or less correctly move taking the reset lock at a higher level. v2: fix typo Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -596,8 +596,17 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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!adev->mman.buffer_funcs_enabled ||
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!adev->ib_pool_ready || amdgpu_in_reset(adev) ||
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!ring->sched.ready) {
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/*
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* A GPU reset should flush all TLBs anyway, so no need to do
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* this while one is ongoing.
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*/
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if (!down_read_trylock(&adev->reset_domain->sem))
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return;
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adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub,
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flush_type);
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up_read(&adev->reset_domain->sem);
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return;
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}
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@ -51,8 +51,6 @@
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#include "athub_v2_0.h"
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#include "athub_v2_1.h"
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#include "amdgpu_reset.h"
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static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned int type,
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@ -265,11 +263,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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* Directly use kiq to do the vm invalidation instead
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*/
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if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
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down_read_trylock(&adev->reset_domain->sem)) {
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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up_read(&adev->reset_domain->sem);
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return;
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}
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@ -33,7 +33,6 @@
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#include "amdgpu_ucode.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_gem.h"
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#include "amdgpu_reset.h"
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#include "bif/bif_4_1_d.h"
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#include "bif/bif_4_1_sh_mask.h"
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@ -430,9 +429,6 @@ static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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u32 mask = 0x0;
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int vmid;
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if (!down_read_trylock(&adev->reset_domain->sem))
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return;
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for (vmid = 1; vmid < 16; vmid++) {
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u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
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@ -443,7 +439,6 @@ static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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WREG32(mmVM_INVALIDATE_REQUEST, mask);
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RREG32(mmVM_INVALIDATE_RESPONSE);
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up_read(&adev->reset_domain->sem);
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}
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/*
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@ -31,7 +31,6 @@
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#include "amdgpu_ucode.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_gem.h"
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#include "amdgpu_reset.h"
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#include "gmc/gmc_8_1_d.h"
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#include "gmc/gmc_8_1_sh_mask.h"
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@ -620,9 +619,6 @@ static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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u32 mask = 0x0;
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int vmid;
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if (!down_read_trylock(&adev->reset_domain->sem))
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return;
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for (vmid = 1; vmid < 16; vmid++) {
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u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
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@ -633,7 +629,6 @@ static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
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WREG32(mmVM_INVALIDATE_REQUEST, mask);
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RREG32(mmVM_INVALIDATE_RESPONSE);
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up_read(&adev->reset_domain->sem);
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}
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/*
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@ -65,8 +65,6 @@
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#include "amdgpu_ras.h"
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#include "amdgpu_xgmi.h"
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#include "amdgpu_reset.h"
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/* add these here since we already include dce12 headers and these are for DCN */
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#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
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#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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@ -851,8 +849,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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* as GFXOFF under bare metal
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*/
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if (adev->gfx.kiq[0].ring.sched.ready &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
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down_read_trylock(&adev->reset_domain->sem)) {
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
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uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
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@ -862,7 +859,6 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack,
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inv_req2, 1 << vmid);
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up_read(&adev->reset_domain->sem);
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return;
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}
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