From fea2538025fefb8f0f9fea558154e293df2f7464 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Oct 2021 14:34:22 +0200 Subject: [PATCH 01/98] pinctrl: renesas: rza1: Fix kerneldoc function names make W=1: drivers/pinctrl/renesas/pinctrl-rza1.c:770: warning: expecting prototype for rza1_gpio_disable_free(). Prototype was for rza1_gpio_free() instead drivers/pinctrl/renesas/pinctrl-rza1.c:889: warning: expecting prototype for rza1_parse_pmx_function(). Prototype was for rza1_parse_pinmux_node() instead Fixes: 5a49b644b3075f88 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by: Geert Uytterhoeven Reviewed-by: Jacopo Mondi Link: https://lore.kernel.org/r/2188ede78110c64b8a3bfbfa794a085dac0e4cd2.1634645735.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rza1.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index 10020fe302b8..c1d6e9512c7a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -757,9 +757,9 @@ static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) } /** - * rza1_gpio_disable_free() - reset a pin + * rza1_gpio_free() - reset a pin * - * Surprisingly, disable_free a gpio, is equivalent to request it. + * Surprisingly, freeing a gpio is equivalent to requesting it. * Reset pin to port mode, with input buffer disabled. This overwrites all * port direction settings applied with set_direction * @@ -875,7 +875,7 @@ static int rza1_dt_node_pin_count(struct device_node *np) } /** - * rza1_parse_pmx_function() - parse a pin mux sub-node + * rza1_parse_pinmux_node() - parse a pin mux sub-node * * @rza1_pctl: RZ/A1 pin controller device * @np: of pmx sub-node From 7388fa8acfce2c3b41babc53c3f3d0b247b098af Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 27 Oct 2021 14:45:06 +0100 Subject: [PATCH 02/98] dt-bindings: pincfg-node: Add "output-impedance-ohms" property On RZ/G2L SoC for Group-B pins, output impedance can be configured. This patch documents "output-impedance-ohms" property in pincfg-node.yaml so that other platforms requiring such feature can make use of this property. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Acked-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20211027134509.5036-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index 71ed0a9def84..4b22a9e3a447 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -114,6 +114,9 @@ properties: description: enable output on a pin without actively driving it (such as enabling an output buffer) + output-impedance-ohms: + description: set the output impedance of a pin to at most X ohms + output-low: type: boolean description: set the pin to output mode with low level From 032816fbbfafe3198bb5c71fbbe4e8e5be33b352 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 27 Oct 2021 14:45:07 +0100 Subject: [PATCH 03/98] pinctrl: pinconf-generic: Add support for "output-impedance-ohms" to be extracted from DT files Add "output-impedance-ohms" property to generic options used for DT parsing files. This enables drivers, which use generic pin configurations, to get the value passed to this property. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20211027134509.5036-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/pinconf-generic.c | 2 ++ include/linux/pinctrl/pinconf-generic.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 22e8d4c4040e..f8edcc88ac01 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -46,6 +46,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true), PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), + PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), @@ -179,6 +180,7 @@ static const struct pinconf_generic_params dt_params[] = { { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 }, { "output-low", PIN_CONFIG_OUTPUT, 0, }, { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index eee0e3948537..2422211d6a5a 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -91,6 +91,8 @@ struct pinctrl_map; * configuration (eg. the currently selected mux function) drive values on * the line. Use argument 1 to enable output mode, argument 0 to disable * it. + * @PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: this will configure the output impedance + * of the pin with the value passed as argument. The argument is in ohms. * @PIN_CONFIG_PERSIST_STATE: retain pin state across sleep or controller reset * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells @@ -129,6 +131,7 @@ enum pin_config_param { PIN_CONFIG_MODE_PWM, PIN_CONFIG_OUTPUT, PIN_CONFIG_OUTPUT_ENABLE, + PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, PIN_CONFIG_PERSIST_STATE, PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SKEW_DELAY, From aa52b008441fb5a5df01c1d016e5172d2ebc6579 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:17 +0000 Subject: [PATCH 04/98] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add output-impedance-ohms property RZ/G2L SoC has two groups of pins, Group-A and Group-B. RZ/G2L SoC supports configuring Output Impedance for Group-B pins (valid values 33/50/66/100). Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211110224622.16022-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index ef68dabcf4dc..3a66fd214c17 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -73,6 +73,8 @@ additionalProperties: pins: true drive-strength: enum: [ 2, 4, 8, 12 ] + output-impedance-ohms: + enum: [ 33, 50, 66, 100 ] power-source: enum: [ 1800, 2500, 3300 ] slew-rate: true From c76629a63b9c7cc52bb661aa36081c0c87780c3b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:18 +0000 Subject: [PATCH 05/98] pinctrl: renesas: rzg2l: Rename RZG2L_SINGLE_PIN_GET_PORT macro Rename RZG2L_SINGLE_PIN_GET_PORT -> RZG2L_SINGLE_PIN_GET_PORT_OFFSET. Also, rename port -> port_offset in rzg2l_pinctrl_pinconf_set/get for readability. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211110224622.16022-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 20b2af889ca9..be9af717a497 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -77,7 +77,7 @@ #define RZG2L_SINGLE_PIN BIT(31) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24) +#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) @@ -432,10 +432,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; + u32 port_offset = 0, reg; unsigned int arg = 0; unsigned long flags; void __iomem *addr; - u32 port = 0, reg; u32 cfg = 0; u8 bit = 0; @@ -443,7 +443,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; if (*pin_data & RZG2L_SINGLE_PIN) { - port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } @@ -454,7 +454,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; spin_lock_irqsave(&pctrl->lock, flags); /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port); + addr = pctrl->base + IEN(port_offset); if (bit >= 4) { bit -= 4; addr += 4; @@ -502,9 +502,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; + u32 port_offset = 0, reg; unsigned long flags; void __iomem *addr; - u32 port = 0, reg; unsigned int i; u32 cfg = 0; u8 bit = 0; @@ -513,7 +513,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; if (*pin_data & RZG2L_SINGLE_PIN) { - port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } @@ -529,7 +529,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port); + addr = pctrl->base + IEN(port_offset); if (bit >= 4) { bit -= 4; addr += 4; From d1189991c823b50990291c8157b56fb141c47155 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:19 +0000 Subject: [PATCH 06/98] pinctrl: renesas: rzg2l: Add helper functions to read/write pin config Add helper functions to read/read modify write pin config. Switch to use helper functions for pins supporting PIN_CONFIG_INPUT_ENABLE capabilities. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211110224622.16022-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 61 +++++++++++++++---------- 1 file changed, 37 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index be9af717a497..4465402367f9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -424,6 +424,39 @@ done: return ret; } +static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, + u8 bit, u32 mask) +{ + void __iomem *addr = pctrl->base + offset; + + /* handle _L/_H for 32-bit register read/write */ + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + return (readl(addr) >> (bit * 8)) & mask; +} + +static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, + u8 bit, u32 mask, u32 val) +{ + void __iomem *addr = pctrl->base + offset; + unsigned long flags; + u32 reg; + + /* handle _L/_H for 32-bit register read/write */ + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + reg = readl(addr) & ~(mask << (bit * 8)); + writel(reg | (val << (bit * 8)), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -432,8 +465,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; - u32 port_offset = 0, reg; unsigned int arg = 0; + u32 port_offset = 0; unsigned long flags; void __iomem *addr; u32 cfg = 0; @@ -452,17 +485,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - spin_lock_irqsave(&pctrl->lock, flags); - /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port_offset); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - reg = readl(addr) & (IEN_MASK << (bit * 8)); - arg = (reg >> (bit * 8)) & 0x1; - spin_unlock_irqrestore(&pctrl->lock, flags); + arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); break; case PIN_CONFIG_POWER_SOURCE: { @@ -502,7 +525,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - u32 port_offset = 0, reg; + u32 port_offset = 0; unsigned long flags; void __iomem *addr; unsigned int i; @@ -528,17 +551,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - /* handle _L/_H for 32-bit register read/write */ - addr = pctrl->base + IEN(port_offset); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - spin_lock_irqsave(&pctrl->lock, flags); - reg = readl(addr) & ~(IEN_MASK << (bit * 8)); - writel(reg | (arg << (bit * 8)), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); + rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); break; } From 7f13a4297be04a1d5e6f025a44531d3c85c02524 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:20 +0000 Subject: [PATCH 07/98] pinctrl: renesas: rzg2l: Add support to get/set pin config for GPIO port pins Add support to get/set pin config for GPIO port pins. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211110224622.16022-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 36 +++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4465402367f9..a5c4bfb59692 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -106,6 +106,7 @@ #define PM_OUTPUT 0x2 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) +#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) struct rzg2l_dedicated_configs { @@ -424,6 +425,23 @@ done: return ret; } +static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, + u32 cfg, u32 port, u8 bit) +{ + u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); + u32 data; + + if (bit >= pincount || port >= pctrl->data->n_port_pins) + return -EINVAL; + + data = pctrl->data->port_pin_configs[port]; + if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) + return -EINVAL; + + return 0; +} + static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, u8 bit, u32 mask) { @@ -466,9 +484,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; - u32 port_offset = 0; unsigned long flags; void __iomem *addr; + u32 port_offset; u32 cfg = 0; u8 bit = 0; @@ -479,6 +497,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } else { + cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); + port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); + bit = RZG2L_PIN_ID_TO_PIN(_pin); + + if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) + return -EINVAL; } switch (param) { @@ -525,9 +550,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - u32 port_offset = 0; unsigned long flags; void __iomem *addr; + u32 port_offset; unsigned int i; u32 cfg = 0; u8 bit = 0; @@ -539,6 +564,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } else { + cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); + port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); + bit = RZG2L_PIN_ID_TO_PIN(_pin); + + if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) + return -EINVAL; } for (i = 0; i < num_configs; i++) { From 22972a2d5bc4bae3db9521580cea8971c96204bc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:21 +0000 Subject: [PATCH 08/98] pinctrl: renesas: rzg2l: Rename PIN_CFG_* macros to match HW manual Rename the below macros to match the HW manual (Rev.1.00): PIN_CFG_IOLH_SD0 -> PIN_CFG_IO_VMC_SD0 PIN_CFG_IOLH_SD1 -> PIN_CFG_IO_VMC_SD1 PIN_CFG_IOLH_QSPI -> PIN_CFG_IO_VMC_QSPI PIN_CFG_IOLH_ETH0 -> PIN_CFG_IO_VMC_ETH0 PIN_CFG_IOLH_ETH1 -> PIN_CFG_IO_VMC_ETH1 Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211110224622.16022-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 122 ++++++++++++------------ 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a5c4bfb59692..5ebb9034b572 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -39,11 +39,11 @@ #define PIN_CFG_SR BIT(1) #define PIN_CFG_IEN BIT(2) #define PIN_CFG_PUPD BIT(3) -#define PIN_CFG_IOLH_SD0 BIT(4) -#define PIN_CFG_IOLH_SD1 BIT(5) -#define PIN_CFG_IOLH_QSPI BIT(6) -#define PIN_CFG_IOLH_ETH0 BIT(7) -#define PIN_CFG_IOLH_ETH1 BIT(8) +#define PIN_CFG_IO_VMC_SD0 BIT(4) +#define PIN_CFG_IO_VMC_SD1 BIT(5) +#define PIN_CFG_IO_VMC_QSPI BIT(6) +#define PIN_CFG_IO_VMC_ETH0 BIT(7) +#define PIN_CFG_IO_VMC_ETH1 BIT(8) #define PIN_CFG_FILONOFF BIT(9) #define PIN_CFG_FILNUM BIT(10) #define PIN_CFG_FILCLKSEL BIT(11) @@ -516,11 +516,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_POWER_SOURCE: { u32 pwr_reg = 0x0; - if (cfg & PIN_CFG_IOLH_SD0) + if (cfg & PIN_CFG_IO_VMC_SD0) pwr_reg = SD_CH(0); - else if (cfg & PIN_CFG_IOLH_SD1) + else if (cfg & PIN_CFG_IO_VMC_SD1) pwr_reg = SD_CH(1); - else if (cfg & PIN_CFG_IOLH_QSPI) + else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else return -EINVAL; @@ -594,11 +594,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (mV != 1800 && mV != 3300) return -EINVAL; - if (cfg & PIN_CFG_IOLH_SD0) + if (cfg & PIN_CFG_IO_VMC_SD0) pwr_reg = SD_CH(0); - else if (cfg & PIN_CFG_IOLH_SD1) + else if (cfg & PIN_CFG_IO_VMC_SD1) pwr_reg = SD_CH(1); - else if (cfg & PIN_CFG_IOLH_QSPI) + else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else return -EINVAL; @@ -900,24 +900,24 @@ static const u32 rzg2l_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), - RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), @@ -941,68 +941,68 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))}, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1))}, { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, - { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) }, { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, From adb613f84a9e3638dfcc85975c7d58a4e80eef02 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Nov 2021 22:46:22 +0000 Subject: [PATCH 09/98] pinctrl: renesas: rzg2l: Add support to get/set drive-strength and output-impedance-ohms RZ/G2L supports two groups of pins Group-A and Group-B. For Group-A pins drive-strength can be configured and for Group-B output-impedance can be configured. This patch splits PIN_CFG_IOLH macro to PIN_CFG_IOLH_A/B and adds support to get/set drive-strength and output-impedance-ohms for the supported pins. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20211110224622.16022-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 159 +++++++++++++++++------- 1 file changed, 112 insertions(+), 47 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 5ebb9034b572..ccee9c9e2e22 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -35,20 +35,21 @@ #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) /* PIN capabilities */ -#define PIN_CFG_IOLH BIT(0) -#define PIN_CFG_SR BIT(1) -#define PIN_CFG_IEN BIT(2) -#define PIN_CFG_PUPD BIT(3) -#define PIN_CFG_IO_VMC_SD0 BIT(4) -#define PIN_CFG_IO_VMC_SD1 BIT(5) -#define PIN_CFG_IO_VMC_QSPI BIT(6) -#define PIN_CFG_IO_VMC_ETH0 BIT(7) -#define PIN_CFG_IO_VMC_ETH1 BIT(8) -#define PIN_CFG_FILONOFF BIT(9) -#define PIN_CFG_FILNUM BIT(10) -#define PIN_CFG_FILCLKSEL BIT(11) +#define PIN_CFG_IOLH_A BIT(0) +#define PIN_CFG_IOLH_B BIT(1) +#define PIN_CFG_SR BIT(2) +#define PIN_CFG_IEN BIT(3) +#define PIN_CFG_PUPD BIT(4) +#define PIN_CFG_IO_VMC_SD0 BIT(5) +#define PIN_CFG_IO_VMC_SD1 BIT(6) +#define PIN_CFG_IO_VMC_QSPI BIT(7) +#define PIN_CFG_IO_VMC_ETH0 BIT(8) +#define PIN_CFG_IO_VMC_ETH1 BIT(9) +#define PIN_CFG_FILONOFF BIT(10) +#define PIN_CFG_FILNUM BIT(11) +#define PIN_CFG_FILCLKSEL BIT(12) -#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \ +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ PIN_CFG_PUPD | \ PIN_CFG_FILONOFF | \ @@ -86,6 +87,7 @@ #define PMC(n) (0x0200 + 0x10 + (n)) #define PFC(n) (0x0400 + 0x40 + (n) * 4) #define PIN(n) (0x0800 + 0x10 + (n)) +#define IOLH(n) (0x1000 + (n) * 8) #define IEN(n) (0x1800 + (n) * 8) #define PWPR (0x3014) #define SD_CH(n) (0x3000 + (n) * 4) @@ -101,6 +103,7 @@ #define PVDD_MASK 0x01 #define PFC_MASK 0x07 #define IEN_MASK 0x01 +#define IOLH_MASK 0x03 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -138,6 +141,9 @@ struct rzg2l_pinctrl { spinlock_t lock; }; +static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; +static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 port, u8 pin, u8 func) { @@ -532,6 +538,28 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; } + case PIN_CONFIG_DRIVE_STRENGTH: { + unsigned int index; + + if (!(cfg & PIN_CFG_IOLH_A)) + return -EINVAL; + + index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + arg = iolh_groupa_mA[index]; + break; + } + + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { + unsigned int index; + + if (!(cfg & PIN_CFG_IOLH_B)) + return -EINVAL; + + index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + arg = iolh_groupb_oi[index]; + break; + } + default: return -ENOTSUPP; } @@ -609,6 +637,43 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, spin_unlock_irqrestore(&pctrl->lock, flags); break; } + + case PIN_CONFIG_DRIVE_STRENGTH: { + unsigned int arg = pinconf_to_config_argument(_configs[i]); + unsigned int index; + + if (!(cfg & PIN_CFG_IOLH_A)) + return -EINVAL; + + for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { + if (arg == iolh_groupa_mA[index]) + break; + } + if (index >= ARRAY_SIZE(iolh_groupa_mA)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + break; + } + + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { + unsigned int arg = pinconf_to_config_argument(_configs[i]); + unsigned int index; + + if (!(cfg & PIN_CFG_IOLH_B)) + return -EINVAL; + + for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { + if (arg == iolh_groupb_oi[index]) + break; + } + if (index >= ARRAY_SIZE(iolh_groupb_oi)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + break; + } + default: return -EOPNOTSUPP; } @@ -935,75 +1000,75 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, - (PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) }, + (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) }, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1))}, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, - (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, From 1e6a58ad39a638f29f9d3e8c8128a2ab355ad1ac Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 1 Nov 2021 00:15:11 +0100 Subject: [PATCH 10/98] dt-bindings: pinctrl: samsung: Document Exynos7885 Document compatible string for Exynos7885 SoC. Signed-off-by: David Virag Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211031231511.46856-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index b8b475967ff9..9e70edceb21b 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller. - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. From b0ef7b1a7a07dde54c5849e0ca94070a1ed08d04 Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 1 Nov 2021 00:17:19 +0100 Subject: [PATCH 11/98] pinctrl: samsung: Add Exynos7885 SoC specific data Add Samsung Exynos7885 SoC specific data to enable pinctrl support for all platforms based on Exynos7885. Signed-off-by: David Virag Link: https://lore.kernel.org/r/20211031231720.46994-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 81 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 84 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 6b77fd24571e..b174796081ef 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -441,6 +441,87 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; +/* pin banks of exynos7885 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), + EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), +}; + +/* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos7885 pin-controller 2 (FSYS) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), +}; + +/* pin banks of exynos7885 pin-controller 3 (TOP) */ +static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), + EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), + EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), + EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), + EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), + EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), + EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), + EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), + EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), + EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), +}; + +const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos7885_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 DISPAUD data */ + .pin_banks = exynos7885_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), + }, { + /* pin-controller instance 2 FSYS data */ + .pin_banks = exynos7885_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 TOP data */ + .pin_banks = exynos7885_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { + .ctrl = exynos7885_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), +}; + /* pin banks of exynos850 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 23f355ae9ca0..8941f658e7f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos7885-pinctrl", + .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 547968a31aed..1f8d30ba05af 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; From 418e0a3551bbef5b221705b0e5b8412cdc0afd39 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:24 +0200 Subject: [PATCH 12/98] lib/string_helpers: Introduce kasprintf_strarray() We have a few users already that basically want to have array of sequential strings to be allocated and filled. Provide a helper for them (basically adjusted version from gpio-mockup.c). Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- include/linux/string_helpers.h | 1 + lib/string_helpers.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h index 4ba39e1403b2..f67a94013c87 100644 --- a/include/linux/string_helpers.h +++ b/include/linux/string_helpers.h @@ -100,6 +100,7 @@ char *kstrdup_quotable(const char *src, gfp_t gfp); char *kstrdup_quotable_cmdline(struct task_struct *task, gfp_t gfp); char *kstrdup_quotable_file(struct file *file, gfp_t gfp); +char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n); void kfree_strarray(char **array, size_t n); #endif diff --git a/lib/string_helpers.c b/lib/string_helpers.c index d5d008f5b1d9..9758997c465e 100644 --- a/lib/string_helpers.c +++ b/lib/string_helpers.c @@ -674,6 +674,39 @@ char *kstrdup_quotable_file(struct file *file, gfp_t gfp) } EXPORT_SYMBOL_GPL(kstrdup_quotable_file); +/** + * kasprintf_strarray - allocate and fill array of sequential strings + * @gfp: flags for the slab allocator + * @prefix: prefix to be used + * @n: amount of lines to be allocated and filled + * + * Allocates and fills @n strings using pattern "%s-%zu", where prefix + * is provided by caller. The caller is responsible to free them with + * kfree_strarray() after use. + * + * Returns array of strings or NULL when memory can't be allocated. + */ +char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n) +{ + char **names; + size_t i; + + names = kcalloc(n + 1, sizeof(char *), gfp); + if (!names) + return NULL; + + for (i = 0; i < n; i++) { + names[i] = kasprintf(gfp, "%s-%zu", prefix, i); + if (!names[i]) { + kfree_strarray(names, i); + return NULL; + } + } + + return names; +} +EXPORT_SYMBOL_GPL(kasprintf_strarray); + /** * kfree_strarray - free a number of dynamically allocated strings contained * in an array and the array itself From acdb89b6c87a2d7b5c48a82756e6f5c6f599f60a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:25 +0200 Subject: [PATCH 13/98] lib/string_helpers: Introduce managed variant of kasprintf_strarray() Some of the users want to have easy way to allocate array of strings that will be automatically cleaned when associated device is gone. Introduce managed variant of kasprintf_strarray() for such use cases. Signed-off-by: Andy Shevchenko --- include/linux/string_helpers.h | 3 +++ lib/string_helpers.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h index f67a94013c87..7a22921c9db7 100644 --- a/include/linux/string_helpers.h +++ b/include/linux/string_helpers.h @@ -7,6 +7,7 @@ #include #include +struct device; struct file; struct task_struct; @@ -103,4 +104,6 @@ char *kstrdup_quotable_file(struct file *file, gfp_t gfp); char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n); void kfree_strarray(char **array, size_t n); +char **devm_kasprintf_strarray(struct device *dev, const char *prefix, size_t n); + #endif diff --git a/lib/string_helpers.c b/lib/string_helpers.c index 9758997c465e..90f9f1b7afec 100644 --- a/lib/string_helpers.c +++ b/lib/string_helpers.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -730,6 +731,36 @@ void kfree_strarray(char **array, size_t n) } EXPORT_SYMBOL_GPL(kfree_strarray); +struct strarray { + char **array; + size_t n; +}; + +static void devm_kfree_strarray(struct device *dev, void *res) +{ + struct strarray *array = res; + + kfree_strarray(array->array, array->n); +} + +char **devm_kasprintf_strarray(struct device *dev, const char *prefix, size_t n) +{ + struct strarray *ptr; + + ptr = devres_alloc(devm_kfree_strarray, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + ptr->array = kasprintf_strarray(GFP_KERNEL, prefix, n); + if (!ptr->array) { + devres_free(ptr); + return ERR_PTR(-ENOMEM); + } + + return ptr->array; +} +EXPORT_SYMBOL_GPL(devm_kasprintf_strarray); + /** * strscpy_pad() - Copy a C-string into a sized buffer * @dest: Where to copy the string to From 5a83227b3d4f9dd1c66beba13f53f31e981efd48 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:26 +0200 Subject: [PATCH 14/98] pinctrl/rockchip: Drop wrong kernel doc annotation Kernel doc validator is not happy: .../pinctrl-rockchip.c:45: warning: This comment starts with '/**', but isn't a kernel-doc comment. Drop it as it's indeed not a kernel doc comment. Signed-off-by: Andy Shevchenko Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5ce260f152ce..6031d98d9849 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -39,7 +39,7 @@ #include "pinconf.h" #include "pinctrl-rockchip.h" -/** +/* * Generate a bitmask for setting a value (v) with a write mask bit in hiword * register 31:16 area. */ From e4dd7fd5ff0acb3f3ed290f52afe20fd840d22b0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:27 +0200 Subject: [PATCH 15/98] pinctrl/rockchip: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 116 +++++++++++++---------------- 1 file changed, 53 insertions(+), 63 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 6031d98d9849..ae80c95bae87 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -285,6 +285,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, { struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct rockchip_pin_group *grp; + struct device *dev = info->dev; struct pinctrl_map *new_map; struct device_node *parent; int map_num = 1; @@ -296,8 +297,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, */ grp = pinctrl_name_to_group(info, np->name); if (!grp) { - dev_err(info->dev, "unable to find group for node %pOFn\n", - np); + dev_err(dev, "unable to find group for node %pOFn\n", np); return -EINVAL; } @@ -331,7 +331,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, new_map[i].data.configs.num_configs = grp->data[i].nconfigs; } - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + dev_dbg(dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group, map_num); return 0; @@ -872,20 +872,20 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + struct device *dev = info->dev; int iomux_num = (pin / 8); if (iomux_num > 3) return -EINVAL; if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { - dev_err(info->dev, "pin %d is unrouted\n", pin); + dev_err(dev, "pin %d is unrouted\n", pin); return -EINVAL; } if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { if (mux != RK_FUNC_GPIO) { - dev_err(info->dev, - "pin %d only supports a gpio mux\n", pin); + dev_err(dev, "pin %d only supports a gpio mux\n", pin); return -ENOTSUPP; } } @@ -909,6 +909,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + struct device *dev = info->dev; int iomux_num = (pin / 8); struct regmap *regmap; int reg, ret, mask, mux_type; @@ -922,8 +923,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return 0; - dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", - bank->bank_num, pin, mux); + dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? info->regmap_pmu : info->regmap_base; @@ -1575,6 +1575,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret; u32 data, temp, rmask_bits; @@ -1620,7 +1621,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, bit -= 16; break; default: - dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", + dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type); return -EINVAL; } @@ -1632,8 +1633,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3288_DRV_BITS_PER_PIN; break; default: - dev_err(info->dev, "unsupported pinctrl drive type: %d\n", - drv_type); + dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } @@ -1652,13 +1652,14 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, i; u32 data, rmask, rmask_bits, temp; u8 bit; int drv_type = bank->drv[pin_num / 8].drv_type; - dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", + dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength); ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); @@ -1680,8 +1681,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, } if (ret < 0) { - dev_err(info->dev, "unsupported driver strength %d\n", - strength); + dev_err(dev, "unsupported driver strength %d\n", strength); return ret; } @@ -1720,7 +1720,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, bit -= 16; break; default: - dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", + dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type); return -EINVAL; } @@ -1731,8 +1731,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3288_DRV_BITS_PER_PIN; break; default: - dev_err(info->dev, "unsupported pinctrl drive type: %d\n", - drv_type); + dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } @@ -1766,6 +1765,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, pull_type; u8 bit; @@ -1800,7 +1800,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) return rockchip_pull_list[pull_type][data]; default: - dev_err(info->dev, "unsupported pinctrl type\n"); + dev_err(dev, "unsupported pinctrl type\n"); return -EINVAL; }; } @@ -1810,13 +1810,13 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, i, pull_type; u8 bit; u32 data, rmask; - dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", - bank->bank_num, pin_num, pull); + dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); /* rk3066b does support any pulls */ if (ctrl->type == RK3066B) @@ -1859,8 +1859,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, } if (ret < 0) { - dev_err(info->dev, "unsupported pull setting %d\n", - pull); + dev_err(dev, "unsupported pull setting %d\n", pull); return ret; } @@ -1872,7 +1871,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, ret = regmap_update_bits(regmap, reg, rmask, data); break; default: - dev_err(info->dev, "unsupported pinctrl type\n"); + dev_err(dev, "unsupported pinctrl type\n"); return -EINVAL; } @@ -1963,12 +1962,13 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret; u8 bit; u32 data, rmask; - dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", + dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, pin_num, enable); ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); @@ -2028,10 +2028,11 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins = info->groups[group].pins; const struct rockchip_pin_config *data = info->groups[group].data; + struct device *dev = info->dev; struct rockchip_pin_bank *bank; int cnt, ret = 0; - dev_dbg(info->dev, "enable function %s group %s\n", + dev_dbg(dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); /* @@ -2310,6 +2311,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, struct rockchip_pinctrl *info, u32 index) { + struct device *dev = info->dev; struct rockchip_pin_bank *bank; int size; const __be32 *list; @@ -2317,7 +2319,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, int i, j; int ret; - dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); + dev_dbg(dev, "group(%d): %pOFn\n", index, np); /* Initialise group */ grp->name = np->name; @@ -2330,18 +2332,14 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, /* we do not check return since it's safe node passed down */ size /= sizeof(*list); if (!size || size % 4) { - dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); + dev_err(dev, "wrong pins number or pins and configs should be by 4\n"); return -EINVAL; } grp->npins = size / 4; - grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), - GFP_KERNEL); - grp->data = devm_kcalloc(info->dev, - grp->npins, - sizeof(struct rockchip_pin_config), - GFP_KERNEL); + grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); + grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); if (!grp->pins || !grp->data) return -ENOMEM; @@ -2375,6 +2373,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, struct rockchip_pinctrl *info, u32 index) { + struct device *dev = info->dev; struct device_node *child; struct rockchip_pmx_func *func; struct rockchip_pin_group *grp; @@ -2382,7 +2381,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, static u32 grp_index; u32 i = 0; - dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); + dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); func = &info->functions[index]; @@ -2392,8 +2391,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, if (func->ngroups <= 0) return 0; - func->groups = devm_kcalloc(info->dev, - func->ngroups, sizeof(char *), GFP_KERNEL); + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); if (!func->groups) return -ENOMEM; @@ -2421,20 +2419,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, rockchip_pinctrl_child_count(info, np); - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); + dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); + dev_dbg(dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kcalloc(dev, - info->nfunctions, - sizeof(struct rockchip_pmx_func), - GFP_KERNEL); + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); if (!info->functions) return -ENOMEM; - info->groups = devm_kcalloc(dev, - info->ngroups, - sizeof(struct rockchip_pin_group), - GFP_KERNEL); + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); if (!info->groups) return -ENOMEM; @@ -2446,7 +2438,7 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, ret = rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); + dev_err(dev, "failed to parse function\n"); of_node_put(child); return ret; } @@ -2461,6 +2453,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, struct pinctrl_desc *ctrldesc = &info->pctl; struct pinctrl_pin_desc *pindesc, *pdesc; struct rockchip_pin_bank *pin_bank; + struct device *dev = &pdev->dev; int pin, bank, ret; int k; @@ -2470,9 +2463,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, ctrldesc->pmxops = &rockchip_pmx_ops; ctrldesc->confops = &rockchip_pinconf_ops; - pindesc = devm_kcalloc(&pdev->dev, - info->ctrl->nr_pins, sizeof(*pindesc), - GFP_KERNEL); + pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); if (!pindesc) return -ENOMEM; @@ -2497,9 +2488,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, if (ret) return ret; - info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); + info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); if (IS_ERR(info->pctl_dev)) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); + dev_err(dev, "could not register pinctrl driver\n"); return PTR_ERR(info->pctl_dev); } @@ -2513,8 +2504,9 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pinctrl *d, struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; const struct of_device_id *match; - struct device_node *node = pdev->dev.of_node; struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; @@ -2566,7 +2558,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( drv_pmu_offs : drv_grf_offs; } - dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", + dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", i, j, iom->offset, drv->offset); /* @@ -2675,8 +2667,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node, *node; struct rockchip_pin_ctrl *ctrl; - struct device_node *np = pdev->dev.of_node, *node; struct resource *res; void __iomem *base; int ret; @@ -2712,8 +2704,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) rockchip_regmap_config.max_register = resource_size(res) - 4; rockchip_regmap_config.name = "rockchip,pinctrl"; - info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, - &rockchip_regmap_config); + info->regmap_base = + devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); /* to check for the old dt-bindings */ info->reg_size = resource_size(res); @@ -2725,12 +2717,10 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - rockchip_regmap_config.max_register = - resource_size(res) - 4; + rockchip_regmap_config.max_register = resource_size(res) - 4; rockchip_regmap_config.name = "rockchip,pinctrl-pull"; - info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, - base, - &rockchip_regmap_config); + info->regmap_pull = + devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); } } @@ -2750,7 +2740,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL); if (ret) { - dev_err(&pdev->dev, "failed to register gpio device\n"); + dev_err(dev, "failed to register gpio device\n"); return ret; } From fb17dcd73fa9c772188724b63cbf5a3fdbb4e605 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:28 +0200 Subject: [PATCH 16/98] pinctrl/rockchip: Make use of the devm_platform_get_and_ioremap_resource() Use the devm_platform_get_and_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Andy Shevchenko Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ae80c95bae87..7206ee30a6b2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2697,8 +2697,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(info->regmap_base)) return PTR_ERR(info->regmap_base); } else { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); @@ -2712,8 +2711,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* Honor the old binding, with pull registers as 2nd resource */ if (ctrl->type == RK3188 && info->reg_size < 0x200) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); if (IS_ERR(base)) return PTR_ERR(base); From 0045028f318b58595596d7e53a88157923e83b0b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:29 +0200 Subject: [PATCH 17/98] pinctrl/rockchip: Convert to use dev_err_probe() It's fine to call dev_err_probe() in ->probe() when error code is known. Convert the driver to use dev_err_probe(). Signed-off-by: Andy Shevchenko Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7206ee30a6b2..929c96ea621a 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2331,10 +2331,8 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, list = of_get_property(np, "rockchip,pins", &size); /* we do not check return since it's safe node passed down */ size /= sizeof(*list); - if (!size || size % 4) { - dev_err(dev, "wrong pins number or pins and configs should be by 4\n"); - return -EINVAL; - } + if (!size || size % 4) + return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); grp->npins = size / 4; @@ -2489,10 +2487,8 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, return ret; info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); - if (IS_ERR(info->pctl_dev)) { - dev_err(dev, "could not register pinctrl driver\n"); - return PTR_ERR(info->pctl_dev); - } + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); return 0; } @@ -2673,10 +2669,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) void __iomem *base; int ret; - if (!dev->of_node) { - dev_err(dev, "device tree node not found\n"); - return -ENODEV; - } + if (!dev->of_node) + return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -2685,10 +2679,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) info->dev = dev; ctrl = rockchip_pinctrl_get_soc_data(info, pdev); - if (!ctrl) { - dev_err(dev, "driver data not available\n"); - return -EINVAL; - } + if (!ctrl) + return dev_err_probe(dev, -EINVAL, "driver data not available\n"); info->ctrl = ctrl; node = of_parse_phandle(np, "rockchip,grf", 0); @@ -2737,10 +2729,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, info); ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL); - if (ret) { - dev_err(dev, "failed to register gpio device\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to register gpio device\n"); return 0; } From 069d7796c95be726655319ec2639aa0d75809add Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:30 +0200 Subject: [PATCH 18/98] pinctrl/rockchip: Switch to use devm_kasprintf_strarray() Since we have a generic helper, switch the module to use it. As a side effect, add check for the memory allocation failures and cleanup it either in error case or when driver is unloading. Signed-off-by: Andy Shevchenko Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 929c96ea621a..438808a867cf 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -33,6 +33,8 @@ #include #include #include +#include + #include #include "core.h" @@ -2452,6 +2454,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, struct pinctrl_pin_desc *pindesc, *pdesc; struct rockchip_pin_bank *pin_bank; struct device *dev = &pdev->dev; + char **pin_names; int pin, bank, ret; int k; @@ -2471,10 +2474,14 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, pdesc = pindesc; for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { pin_bank = &info->ctrl->pin_banks[bank]; + + pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", - pin_bank->name, pin); + pdesc->name = pin_names[pin]; pdesc++; } From a6d93da40fe917582100fa0dafb8a59f402a34f9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:31 +0200 Subject: [PATCH 19/98] pinctrl: armada-37xx: Fix function name in the kernel doc Kernel doc validator is not happy: .../pinctrl-armada-37xx.c:926: warning: expecting prototype for armada_37xx_fill_funcs(). Prototype was for armada_37xx_fill_func() instead Fix this by updating function name in the kernel doc. Signed-off-by: Andy Shevchenko Reviewed-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5cb018f98800..5615cb7a1209 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -913,7 +913,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) } /** - * armada_37xx_fill_funcs() - complete the funcs array + * armada_37xx_fill_func() - complete the funcs array * @info: info driver instance * * Based on the data available from the armada_37xx_pin_group array From 50cf2ed284e49028a885aa56c3ea50714c635879 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:32 +0200 Subject: [PATCH 20/98] pinctrl: armada-37xx: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko Reviewed-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 56 +++++++++------------ 1 file changed, 23 insertions(+), 33 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5615cb7a1209..37f92dc54d7a 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -341,12 +341,12 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, struct armada_37xx_pin_group *grp) { struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = info->dev; unsigned int reg = SELECTION; unsigned int mask = grp->reg_mask; int func, val; - dev_dbg(info->dev, "enable function %s group %s\n", - name, grp->name); + dev_dbg(dev, "enable function %s group %s\n", name, grp->name); func = match_string(grp->funcs, NB_FUNCS, name); if (func < 0) @@ -722,16 +722,16 @@ static unsigned int armada_37xx_irq_startup(struct irq_data *d) static int armada_37xx_irqchip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { - struct device_node *np = info->dev->of_node; struct gpio_chip *gc = &info->gpio_chip; struct irq_chip *irqchip = &info->irq_chip; struct gpio_irq_chip *girq = &gc->irq; struct device *dev = &pdev->dev; + struct device_node *np; struct resource res; int ret = -ENODEV, i, nr_irq_parent; /* Check if we have at least one gpio-controller child node */ - for_each_child_of_node(info->dev->of_node, np) { + for_each_child_of_node(dev->of_node, np) { if (of_property_read_bool(np, "gpio-controller")) { ret = 0; break; @@ -750,12 +750,12 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, return 0; } - if (of_address_to_resource(info->dev->of_node, 1, &res)) { + if (of_address_to_resource(dev->of_node, 1, &res)) { dev_err(dev, "cannot find IO resource\n"); return -ENOENT; } - info->base = devm_ioremap_resource(info->dev, &res); + info->base = devm_ioremap_resource(dev, &res); if (IS_ERR(info->base)) return PTR_ERR(info->base); @@ -774,8 +774,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, * the chained irq with all of them. */ girq->num_parents = nr_irq_parent; - girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, - sizeof(*girq->parents), GFP_KERNEL); + girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; for (i = 0; i < nr_irq_parent; i++) { @@ -794,11 +793,12 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, static int armada_37xx_gpiochip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { + struct device *dev = &pdev->dev; struct device_node *np; struct gpio_chip *gc; int ret = -ENODEV; - for_each_child_of_node(info->dev->of_node, np) { + for_each_child_of_node(dev->of_node, np) { if (of_find_property(np, "gpio-controller", NULL)) { ret = 0; break; @@ -811,19 +811,16 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, gc = &info->gpio_chip; gc->ngpio = info->data->nr_pins; - gc->parent = &pdev->dev; + gc->parent = dev; gc->base = -1; gc->of_node = np; gc->label = info->data->name; ret = armada_37xx_irqchip_register(pdev, info); - if (ret) - return ret; - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret; - return 0; + return devm_gpiochip_add_data(dev, gc, info); } /** @@ -874,13 +871,13 @@ static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) { int n, num = 0, funcsize = info->data->nr_pins; + struct device *dev = info->dev; for (n = 0; n < info->ngroups; n++) { struct armada_37xx_pin_group *grp = &info->groups[n]; int i, j, f; - grp->pins = devm_kcalloc(info->dev, - grp->npins + grp->extra_npins, + grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, sizeof(*grp->pins), GFP_KERNEL); if (!grp->pins) @@ -898,8 +895,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) ret = armada_37xx_add_function(info->funcs, &funcsize, grp->funcs[f]); if (ret == -EOVERFLOW) - dev_err(info->dev, - "More functions than pins(%d)\n", + dev_err(dev, "More functions than pins(%d)\n", info->data->nr_pins); if (ret < 0) continue; @@ -925,6 +921,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) { struct armada_37xx_pmx_func *funcs = info->funcs; + struct device *dev = info->dev; int n; for (n = 0; n < info->nfuncs; n++) { @@ -932,8 +929,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) const char **groups; int g; - funcs[n].groups = devm_kcalloc(info->dev, - funcs[n].ngroups, + funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, sizeof(*(funcs[n].groups)), GFP_KERNEL); if (!funcs[n].groups) @@ -962,6 +958,7 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, const struct armada_37xx_pin_data *pin_data = info->data; struct pinctrl_desc *ctrldesc = &info->pctl; struct pinctrl_pin_desc *pindesc, *pdesc; + struct device *dev = &pdev->dev; int pin, ret; info->groups = pin_data->groups; @@ -973,9 +970,7 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, ctrldesc->pmxops = &armada_37xx_pmx_ops; ctrldesc->confops = &armada_37xx_pinconf_ops; - pindesc = devm_kcalloc(&pdev->dev, - pin_data->nr_pins, sizeof(*pindesc), - GFP_KERNEL); + pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); if (!pindesc) return -ENOMEM; @@ -994,14 +989,10 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, * we allocate functions for number of pins and hope there are * fewer unique functions than pins available */ - info->funcs = devm_kcalloc(&pdev->dev, - pin_data->nr_pins, - sizeof(struct armada_37xx_pmx_func), - GFP_KERNEL); + info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); if (!info->funcs) return -ENOMEM; - ret = armada_37xx_fill_group(info); if (ret) return ret; @@ -1010,9 +1001,9 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, if (ret) return ret; - info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); + info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); if (IS_ERR(info->pctl_dev)) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); + dev_err(dev, "could not register pinctrl driver\n"); return PTR_ERR(info->pctl_dev); } @@ -1143,8 +1134,7 @@ static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) struct regmap *regmap; int ret; - info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl), - GFP_KERNEL); + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; @@ -1152,7 +1142,7 @@ static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) regmap = syscon_node_to_regmap(np); if (IS_ERR(regmap)) { - dev_err(&pdev->dev, "cannot get regmap\n"); + dev_err(dev, "cannot get regmap\n"); return PTR_ERR(regmap); } info->regmap = regmap; From 49bdef501728acbfadc7eeafafb4f6c3fea415eb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:33 +0200 Subject: [PATCH 21/98] pinctrl: armada-37xx: Make use of the devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling of_address_to_resource() and devm_ioremap_resource() separately. Signed-off-by: Andy Shevchenko Reviewed-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 37f92dc54d7a..282b3fac3bec 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -727,7 +727,6 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, struct gpio_irq_chip *girq = &gc->irq; struct device *dev = &pdev->dev; struct device_node *np; - struct resource res; int ret = -ENODEV, i, nr_irq_parent; /* Check if we have at least one gpio-controller child node */ @@ -750,12 +749,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, return 0; } - if (of_address_to_resource(dev->of_node, 1, &res)) { - dev_err(dev, "cannot find IO resource\n"); - return -ENOENT; - } - - info->base = devm_ioremap_resource(dev, &res); + info->base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(info->base)) return PTR_ERR(info->base); From 06cb10ea0cd5c5f4db9627a33ab47fec32cb5960 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:34 +0200 Subject: [PATCH 22/98] pinctrl: armada-37xx: Convert to use dev_err_probe() It's fine to call dev_err_probe() in ->probe() when error code is known. Convert the driver to use dev_err_probe(). Signed-off-by: Andy Shevchenko Reviewed-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 282b3fac3bec..f48745c43419 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -736,10 +736,8 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, break; } } - if (ret) { - dev_err(dev, "no gpio-controller child node\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "no gpio-controller child node\n"); nr_irq_parent = of_irq_count(np); spin_lock_init(&info->irq_lock); @@ -996,10 +994,8 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, return ret; info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); - if (IS_ERR(info->pctl_dev)) { - dev_err(dev, "could not register pinctrl driver\n"); - return PTR_ERR(info->pctl_dev); - } + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); return 0; } @@ -1135,10 +1131,8 @@ static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) info->dev = dev; regmap = syscon_node_to_regmap(np); - if (IS_ERR(regmap)) { - dev_err(dev, "cannot get regmap\n"); - return PTR_ERR(regmap); - } + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n"); info->regmap = regmap; info->data = of_device_get_match_data(dev); From b32b195d7f021f4c66a3de7b34ee648e56b824cd Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:35 +0200 Subject: [PATCH 23/98] pinctrl: armada-37xx: Switch to use devm_kasprintf_strarray() Since we have a generic helper, switch the module to use it. As a side effect, add check for the memory allocation failures and cleanup it either in error case or when driver is unloading. Signed-off-by: Andy Shevchenko Reviewed-by: Gregory CLEMENT --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index f48745c43419..08cad14042e2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "../pinctrl-utils.h" @@ -951,6 +952,7 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, struct pinctrl_desc *ctrldesc = &info->pctl; struct pinctrl_pin_desc *pindesc, *pdesc; struct device *dev = &pdev->dev; + char **pin_names; int pin, ret; info->groups = pin_data->groups; @@ -969,11 +971,14 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, ctrldesc->pins = pindesc; ctrldesc->npins = pin_data->nr_pins; + pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + pdesc = pindesc; for (pin = 0; pin < pin_data->nr_pins; pin++) { pdesc->number = pin; - pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", - pin_data->name, pin); + pdesc->name = pin_names[pin]; pdesc++; } From e803ab971b5b2d8f8626a0b75fa40197a237440f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:36 +0200 Subject: [PATCH 24/98] pinctrl: st: Drop wrong kernel doc annotations Kernel doc validator is not happy: .../pinctrl-st.c:59: warning: This comment starts with '/**', but isn't a kernel-doc comment. .../pinctrl-st.c:73: warning: This comment starts with '/**', but isn't a kernel-doc comment. Drop them as they are indeed not a kernel doc comments. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1482a01dfec7..ae8783b34ed2 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -55,7 +55,7 @@ #define ST_GPIO_DIRECTION_OUT 0x2 #define ST_GPIO_DIRECTION_IN 0x4 -/** +/* * Packed style retime configuration. * There are two registers cfg0 and cfg1 in this style for each bank. * Each field in this register is 8 bit corresponding to 8 pins in the bank. @@ -69,7 +69,7 @@ #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) -/** +/* * Dedicated style retime Configuration register * each register is dedicated per pin. */ From f972707662dbaf066d055a507c0654e4bb6e659e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:37 +0200 Subject: [PATCH 25/98] pinctrl: st: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-st.c | 73 +++++++++++++++++------------------- 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index ae8783b34ed2..f592e9ad93fc 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -814,26 +814,25 @@ static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, { struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct st_pctl_group *grp; + struct device *dev = info->dev; struct pinctrl_map *new_map; struct device_node *parent; int map_num, i; grp = st_pctl_find_group_by_name(info, np->name); if (!grp) { - dev_err(info->dev, "unable to find group for node %pOFn\n", - np); + dev_err(dev, "unable to find group for node %pOFn\n", np); return -EINVAL; } map_num = grp->npins + 1; - new_map = devm_kcalloc(pctldev->dev, - map_num, sizeof(*new_map), GFP_KERNEL); + new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; parent = of_get_parent(np); if (!parent) { - devm_kfree(pctldev->dev, new_map); + devm_kfree(dev, new_map); return -EINVAL; } @@ -853,7 +852,7 @@ static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, new_map[i].data.configs.configs = &grp->pin_conf[i].config; new_map[i].data.configs.num_configs = 1; } - dev_info(pctldev->dev, "maps: function %s group %s num %d\n", + dev_info(dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, grp->name, map_num); return 0; @@ -1173,6 +1172,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np, /* bank pad direction val altfunction */ const __be32 *list; struct property *pp; + struct device *dev = info->dev; struct st_pinconf *conf; struct device_node *pins; int i = 0, npins = 0, nr_props, ret = 0; @@ -1197,9 +1197,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np, grp->npins = npins; grp->name = np->name; - grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); - grp->pin_conf = devm_kcalloc(info->dev, - npins, sizeof(*conf), GFP_KERNEL); + grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); + grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); if (!grp->pins || !grp->pin_conf) { ret = -ENOMEM; @@ -1247,6 +1246,7 @@ out_put_node: static int st_pctl_parse_functions(struct device_node *np, struct st_pinctrl *info, u32 index, int *grp_index) { + struct device *dev = info->dev; struct device_node *child; struct st_pmx_func *func; struct st_pctl_group *grp; @@ -1256,11 +1256,10 @@ static int st_pctl_parse_functions(struct device_node *np, func->name = np->name; func->ngroups = of_get_child_count(np); if (func->ngroups == 0) { - dev_err(info->dev, "No groups defined\n"); + dev_err(dev, "No groups defined\n"); return -EINVAL; } - func->groups = devm_kcalloc(info->dev, - func->ngroups, sizeof(char *), GFP_KERNEL); + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); if (!func->groups) return -ENOMEM; @@ -1275,8 +1274,7 @@ static int st_pctl_parse_functions(struct device_node *np, return ret; } } - dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", - index, func->name, func->ngroups); + dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); return 0; } @@ -1577,10 +1575,11 @@ static const struct of_device_id st_pctl_of_match[] = { static int st_pctl_probe_dt(struct platform_device *pdev, struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) { + struct device *dev = &pdev->dev; int ret = 0; int i = 0, j = 0, k = 0, bank; struct pinctrl_pin_desc *pdesc; - struct device_node *np = pdev->dev.of_node; + struct device_node *np = dev->of_node; struct device_node *child; int grp_index = 0; int irq = 0; @@ -1588,30 +1587,26 @@ static int st_pctl_probe_dt(struct platform_device *pdev, st_pctl_dt_child_count(info, np); if (!info->nbanks) { - dev_err(&pdev->dev, "you need at least one gpio bank\n"); + dev_err(dev, "you need at least one gpio bank\n"); return -EINVAL; } - dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); - dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); + dev_info(dev, "nbanks = %d\n", info->nbanks); + dev_info(dev, "nfunctions = %d\n", info->nfunctions); + dev_info(dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kcalloc(&pdev->dev, - info->nfunctions, sizeof(*info->functions), GFP_KERNEL); + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); - info->groups = devm_kcalloc(&pdev->dev, - info->ngroups, sizeof(*info->groups), - GFP_KERNEL); + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); - info->banks = devm_kcalloc(&pdev->dev, - info->nbanks, sizeof(*info->banks), GFP_KERNEL); + info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); if (!info->functions || !info->groups || !info->banks) return -ENOMEM; info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); if (IS_ERR(info->regmap)) { - dev_err(info->dev, "No syscfg phandle specified\n"); + dev_err(dev, "No syscfg phandle specified\n"); return PTR_ERR(info->regmap); } info->data = of_match_node(st_pctl_of_match, np)->data; @@ -1621,7 +1616,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev, if (irq > 0) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "irqmux"); - info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); + info->irqmux_base = devm_ioremap_resource(dev, res); if (IS_ERR(info->irqmux_base)) return PTR_ERR(info->irqmux_base); @@ -1632,8 +1627,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev, } pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; - pdesc = devm_kcalloc(&pdev->dev, - pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); + pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); if (!pdesc) return -ENOMEM; @@ -1663,7 +1657,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev, ret = st_pctl_parse_functions(child, info, i++, &grp_index); if (ret) { - dev_err(&pdev->dev, "No functions found.\n"); + dev_err(dev, "No functions found.\n"); of_node_put(child); return ret; } @@ -1675,24 +1669,25 @@ static int st_pctl_probe_dt(struct platform_device *pdev, static int st_pctl_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct st_pinctrl *info; struct pinctrl_desc *pctl_desc; int ret, i; - if (!pdev->dev.of_node) { - dev_err(&pdev->dev, "device node not found.\n"); + if (!dev->of_node) { + dev_err(dev, "device node not found.\n"); return -EINVAL; } - pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); + pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); if (!pctl_desc) return -ENOMEM; - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; - info->dev = &pdev->dev; + info->dev = dev; platform_set_drvdata(pdev, info); ret = st_pctl_probe_dt(pdev, pctl_desc, info); if (ret) @@ -1702,11 +1697,11 @@ static int st_pctl_probe(struct platform_device *pdev) pctl_desc->pctlops = &st_pctlops; pctl_desc->pmxops = &st_pmxops; pctl_desc->confops = &st_confops; - pctl_desc->name = dev_name(&pdev->dev); + pctl_desc->name = dev_name(dev); - info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); + info->pctl = devm_pinctrl_register(dev, pctl_desc, info); if (IS_ERR(info->pctl)) { - dev_err(&pdev->dev, "Failed pinctrl registration\n"); + dev_err(dev, "Failed pinctrl registration\n"); return PTR_ERR(info->pctl); } From 3809671d95a1c400ecf8235d1dc3e5b352aee242 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:38 +0200 Subject: [PATCH 26/98] pinctrl: st: Make use of the devm_platform_ioremap_resource_byname() Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index f592e9ad93fc..bccde0b8f012 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1583,7 +1583,6 @@ static int st_pctl_probe_dt(struct platform_device *pdev, struct device_node *child; int grp_index = 0; int irq = 0; - struct resource *res; st_pctl_dt_child_count(info, np); if (!info->nbanks) { @@ -1614,16 +1613,12 @@ static int st_pctl_probe_dt(struct platform_device *pdev, irq = platform_get_irq(pdev, 0); if (irq > 0) { - res = platform_get_resource_byname(pdev, - IORESOURCE_MEM, "irqmux"); - info->irqmux_base = devm_ioremap_resource(dev, res); - + info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); if (IS_ERR(info->irqmux_base)) return PTR_ERR(info->irqmux_base); irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, info); - } pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; From 3d4d3e0a7d67a9d49fb661c6ea3b51fc3696030f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:39 +0200 Subject: [PATCH 27/98] pinctrl: st: Convert to use dev_err_probe() It's fine to call dev_err_probe() in ->probe() when error code is known. Convert the driver to use dev_err_probe(). Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index bccde0b8f012..9cb0da88b098 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1255,10 +1255,8 @@ static int st_pctl_parse_functions(struct device_node *np, func = &info->functions[index]; func->name = np->name; func->ngroups = of_get_child_count(np); - if (func->ngroups == 0) { - dev_err(dev, "No groups defined\n"); - return -EINVAL; - } + if (func->ngroups == 0) + return dev_err_probe(dev, -EINVAL, "No groups defined\n"); func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); if (!func->groups) return -ENOMEM; @@ -1555,10 +1553,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, skip_irq: err = gpiochip_add_data(&bank->gpio_chip, bank); - if (err) { - dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); dev_info(dev, "%s bank added.\n", range->name); return 0; @@ -1585,10 +1581,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, int irq = 0; st_pctl_dt_child_count(info, np); - if (!info->nbanks) { - dev_err(dev, "you need at least one gpio bank\n"); - return -EINVAL; - } + if (!info->nbanks) + return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); dev_info(dev, "nbanks = %d\n", info->nbanks); dev_info(dev, "nfunctions = %d\n", info->nfunctions); @@ -1604,10 +1598,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, return -ENOMEM; info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); - if (IS_ERR(info->regmap)) { - dev_err(dev, "No syscfg phandle specified\n"); - return PTR_ERR(info->regmap); - } + if (IS_ERR(info->regmap)) + return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); info->data = of_match_node(st_pctl_of_match, np)->data; irq = platform_get_irq(pdev, 0); @@ -1695,10 +1687,8 @@ static int st_pctl_probe(struct platform_device *pdev) pctl_desc->name = dev_name(dev); info->pctl = devm_pinctrl_register(dev, pctl_desc, info); - if (IS_ERR(info->pctl)) { - dev_err(dev, "Failed pinctrl registration\n"); - return PTR_ERR(info->pctl); - } + if (IS_ERR(info->pctl)) + return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); for (i = 0; i < info->nbanks; i++) pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); From 3956d6c85f26b5dd59cc6d3bf85a6a7341c68518 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:40 +0200 Subject: [PATCH 28/98] pinctrl: st: Switch to use devm_kasprintf_strarray() Since we have a generic helper, switch the module to use it. As a side effect, add check for the memory allocation failures and cleanup it either in error case or when driver is unloading. Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 9cb0da88b098..0fea71fd9a00 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1624,6 +1624,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, for_each_child_of_node(np, child) { if (of_property_read_bool(child, "gpio-controller")) { const char *bank_name = NULL; + char **pin_names; + ret = st_gpiolib_register_bank(info, bank, child); if (ret) { of_node_put(child); @@ -1632,10 +1634,16 @@ static int st_pctl_probe_dt(struct platform_device *pdev, k = info->banks[bank].range.pin_base; bank_name = info->banks[bank].range.name; + + pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); + if (IS_ERR(pin_names)) { + of_node_put(child); + return PTR_ERR(pin_names); + } + for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", - bank_name, j); + pdesc->name = pin_names[j]; pdesc++; } st_parse_syscfgs(info, bank, child); From 54784ff24971ed5bd3f1056edce998148709d0a7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:41 +0200 Subject: [PATCH 29/98] pinctrl: zynqmp: Unify pin naming Since we have devm_kasprintf_strarray() helper, which is used in the rest of pin control drivers, it makes sense to switch this driver to it. The pin names are not part of any ABI and hence there will be no regression based on that. Otherwise all generated pin names will follow the same schema in the pin control subsystem. Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-zynqmp.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index e14012209992..42da6bd399ee 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -809,6 +809,7 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, unsigned int *npins) { struct pinctrl_pin_desc *pins, *pin; + char **pin_names; int ret; int i; @@ -820,13 +821,14 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, if (!pins) return -ENOMEM; + pin_names = devm_kasprintf_strarray(dev, ZYNQMP_PIN_PREFIX, *npins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (i = 0; i < *npins; i++) { pin = &pins[i]; pin->number = i; - pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", - ZYNQMP_PIN_PREFIX, i); - if (!pin->name) - return -ENOMEM; + pin->name = pin_names[i]; } *zynqmp_pins = pins; From f7c151d86487eec720f52843133bce270b07fecc Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 5 Nov 2021 14:42:42 +0200 Subject: [PATCH 30/98] gpio: mockup: Switch to use kasprintf_strarray() Since we have a generic helper, switch the module to use it. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mockup.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c index d26bff29157b..8943cea92764 100644 --- a/drivers/gpio/gpio-mockup.c +++ b/drivers/gpio/gpio-mockup.c @@ -491,27 +491,6 @@ static void gpio_mockup_unregister_pdevs(void) } } -static __init char **gpio_mockup_make_line_names(const char *label, - unsigned int num_lines) -{ - unsigned int i; - char **names; - - names = kcalloc(num_lines + 1, sizeof(char *), GFP_KERNEL); - if (!names) - return NULL; - - for (i = 0; i < num_lines; i++) { - names[i] = kasprintf(GFP_KERNEL, "%s-%u", label, i); - if (!names[i]) { - kfree_strarray(names, i); - return NULL; - } - } - - return names; -} - static int __init gpio_mockup_register_chip(int idx) { struct property_entry properties[GPIO_MOCKUP_MAX_PROP]; @@ -538,7 +517,7 @@ static int __init gpio_mockup_register_chip(int idx) properties[prop++] = PROPERTY_ENTRY_U16("nr-gpios", ngpio); if (gpio_mockup_named_lines) { - line_names = gpio_mockup_make_line_names(chip_label, ngpio); + line_names = kasprintf_strarray(GFP_KERNEL, chip_label, ngpio); if (!line_names) return -ENOMEM; From 7c50a407b8687ae3589c740d2347d9ae73887889 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 17 Nov 2021 10:59:32 +0100 Subject: [PATCH 31/98] pinctrl: renesas: Remove unneeded locking around sh_pfc_read() calls There is no need to acquire the spinlock when reading from a pin controller register: 1. Reading a single MMIO register is an atomic operation, 2. While sh_pfc_phys_to_virt() inside sh_pfc_read() has to traverse all mapped windows to find the appropriate virtual address, this does not need any locking, as the window mappings are never changed. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/2008ca99f0079fd5d4e640b7ef78710c98cc9f77.1637143108.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index f3eecb20c086..96b9de974246 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -504,7 +504,6 @@ static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, unsigned int pin) { - unsigned long flags; unsigned int offset; unsigned int size; u32 reg; @@ -514,11 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, if (!reg) return -EINVAL; - spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read(pfc, reg); - spin_unlock_irqrestore(&pfc->lock, flags); - - val = (val >> offset) & GENMASK(size - 1, 0); + val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0); /* Convert the value to mA based on a full drive strength value of 24mA. * We can make the full value configurable later if needed. @@ -648,9 +643,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; - spin_lock_irqsave(&pfc->lock, flags); val = sh_pfc_read(pfc, pocctrl); - spin_unlock_irqrestore(&pfc->lock, flags); lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ? 2500 : 1800; From 463201a784c45cd5413ecd0dfbe80224489b7ea5 Mon Sep 17 00:00:00 2001 From: Kavyasree Kotagiri Date: Thu, 18 Nov 2021 16:55:47 +0530 Subject: [PATCH 32/98] dt-bindings: pinctrl: ocelot: add lan966x SoC support Add documentation for the compatible designated for lan966x. Signed-off-by: Kavyasree Kotagiri Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211118112548.14582-2-kavyasree.kotagiri@microchip.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index db99bd95d423..3bb76487669f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,7 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl" or "mscc,serval-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl" or + "microchip,lan966x-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From 531d6ab36571c2ffe698702e1f5748a7cfaa2c5d Mon Sep 17 00:00:00 2001 From: Kavyasree Kotagiri Date: Thu, 18 Nov 2021 16:55:48 +0530 Subject: [PATCH 33/98] pinctrl: ocelot: Extend support for lan966x This patch extends pinctrl-ocelot driver to support also the lan966x. Register layout is same as ocelot. It has 78 GPIOs. Requires 3 registers ALT0, ALT1, ALT2 to configure ALT mode. Signed-off-by: Kavyasree Kotagiri Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20211118112548.14582-3-kavyasree.kotagiri@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 416 +++++++++++++++++++++++++++++++ 1 file changed, 416 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 0a36ec8775a3..875e3f319d7b 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -57,16 +57,71 @@ enum { #define OCELOT_FUNC_PER_PIN 4 enum { + FUNC_CAN0_a, + FUNC_CAN0_b, + FUNC_CAN1, FUNC_NONE, + FUNC_FC0_a, + FUNC_FC0_b, + FUNC_FC0_c, + FUNC_FC1_a, + FUNC_FC1_b, + FUNC_FC1_c, + FUNC_FC2_a, + FUNC_FC2_b, + FUNC_FC3_a, + FUNC_FC3_b, + FUNC_FC3_c, + FUNC_FC4_a, + FUNC_FC4_b, + FUNC_FC4_c, + FUNC_FC_SHRD0, + FUNC_FC_SHRD1, + FUNC_FC_SHRD2, + FUNC_FC_SHRD3, + FUNC_FC_SHRD4, + FUNC_FC_SHRD5, + FUNC_FC_SHRD6, + FUNC_FC_SHRD7, + FUNC_FC_SHRD8, + FUNC_FC_SHRD9, + FUNC_FC_SHRD10, + FUNC_FC_SHRD11, + FUNC_FC_SHRD12, + FUNC_FC_SHRD13, + FUNC_FC_SHRD14, + FUNC_FC_SHRD15, + FUNC_FC_SHRD16, + FUNC_FC_SHRD17, + FUNC_FC_SHRD18, + FUNC_FC_SHRD19, + FUNC_FC_SHRD20, FUNC_GPIO, + FUNC_IB_TRG_a, + FUNC_IB_TRG_b, + FUNC_IB_TRG_c, FUNC_IRQ0, + FUNC_IRQ_IN_a, + FUNC_IRQ_IN_b, + FUNC_IRQ_IN_c, FUNC_IRQ0_IN, + FUNC_IRQ_OUT_a, + FUNC_IRQ_OUT_b, + FUNC_IRQ_OUT_c, FUNC_IRQ0_OUT, FUNC_IRQ1, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, FUNC_EXT_IRQ, FUNC_MIIM, + FUNC_MIIM_a, + FUNC_MIIM_b, + FUNC_MIIM_c, + FUNC_MIIM_Sa, + FUNC_MIIM_Sb, + FUNC_OB_TRG, + FUNC_OB_TRG_a, + FUNC_OB_TRG_b, FUNC_PHY_LED, FUNC_PCI_WAKE, FUNC_MD, @@ -74,65 +129,174 @@ enum { FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, + FUNC_PTPSYNC_1, + FUNC_PTPSYNC_2, + FUNC_PTPSYNC_3, + FUNC_PTPSYNC_4, + FUNC_PTPSYNC_5, + FUNC_PTPSYNC_6, + FUNC_PTPSYNC_7, FUNC_PWM, + FUNC_QSPI1, + FUNC_QSPI2, + FUNC_R, + FUNC_RECO_a, + FUNC_RECO_b, FUNC_RECO_CLK, + FUNC_SD, FUNC_SFP, + FUNC_SFP_SD, FUNC_SG0, FUNC_SG1, FUNC_SG2, + FUNC_SGPIO_a, + FUNC_SGPIO_b, FUNC_SI, FUNC_SI2, FUNC_TACHO, + FUNC_TACHO_a, + FUNC_TACHO_b, FUNC_TWI, FUNC_TWI2, FUNC_TWI3, FUNC_TWI_SCL_M, + FUNC_TWI_SLC_GATE, + FUNC_TWI_SLC_GATE_AD, FUNC_UART, FUNC_UART2, FUNC_UART3, + FUNC_USB_H_a, + FUNC_USB_H_b, + FUNC_USB_H_c, + FUNC_USB_S_a, + FUNC_USB_S_b, + FUNC_USB_S_c, FUNC_PLL_STAT, FUNC_EMMC, + FUNC_EMMC_SD, FUNC_REF_CLK, FUNC_RCVRD_CLK, FUNC_MAX }; static const char *const ocelot_function_names[] = { + [FUNC_CAN0_a] = "can0_a", + [FUNC_CAN0_b] = "can0_b", + [FUNC_CAN1] = "can1", [FUNC_NONE] = "none", + [FUNC_FC0_a] = "fc0_a", + [FUNC_FC0_b] = "fc0_b", + [FUNC_FC0_c] = "fc0_c", + [FUNC_FC1_a] = "fc1_a", + [FUNC_FC1_b] = "fc1_b", + [FUNC_FC1_c] = "fc1_c", + [FUNC_FC2_a] = "fc2_a", + [FUNC_FC2_b] = "fc2_b", + [FUNC_FC3_a] = "fc3_a", + [FUNC_FC3_b] = "fc3_b", + [FUNC_FC3_c] = "fc3_c", + [FUNC_FC4_a] = "fc4_a", + [FUNC_FC4_b] = "fc4_b", + [FUNC_FC4_c] = "fc4_c", + [FUNC_FC_SHRD0] = "fc_shrd0", + [FUNC_FC_SHRD1] = "fc_shrd1", + [FUNC_FC_SHRD2] = "fc_shrd2", + [FUNC_FC_SHRD3] = "fc_shrd3", + [FUNC_FC_SHRD4] = "fc_shrd4", + [FUNC_FC_SHRD5] = "fc_shrd5", + [FUNC_FC_SHRD6] = "fc_shrd6", + [FUNC_FC_SHRD7] = "fc_shrd7", + [FUNC_FC_SHRD8] = "fc_shrd8", + [FUNC_FC_SHRD9] = "fc_shrd9", + [FUNC_FC_SHRD10] = "fc_shrd10", + [FUNC_FC_SHRD11] = "fc_shrd11", + [FUNC_FC_SHRD12] = "fc_shrd12", + [FUNC_FC_SHRD13] = "fc_shrd13", + [FUNC_FC_SHRD14] = "fc_shrd14", + [FUNC_FC_SHRD15] = "fc_shrd15", + [FUNC_FC_SHRD16] = "fc_shrd16", + [FUNC_FC_SHRD17] = "fc_shrd17", + [FUNC_FC_SHRD18] = "fc_shrd18", + [FUNC_FC_SHRD19] = "fc_shrd19", + [FUNC_FC_SHRD20] = "fc_shrd20", [FUNC_GPIO] = "gpio", + [FUNC_IB_TRG_a] = "ib_trig_a", + [FUNC_IB_TRG_b] = "ib_trig_b", + [FUNC_IB_TRG_c] = "ib_trig_c", [FUNC_IRQ0] = "irq0", + [FUNC_IRQ_IN_a] = "irq_in_a", + [FUNC_IRQ_IN_b] = "irq_in_b", + [FUNC_IRQ_IN_c] = "irq_in_c", [FUNC_IRQ0_IN] = "irq0_in", + [FUNC_IRQ_OUT_a] = "irq_out_a", + [FUNC_IRQ_OUT_b] = "irq_out_b", + [FUNC_IRQ_OUT_c] = "irq_out_c", [FUNC_IRQ0_OUT] = "irq0_out", [FUNC_IRQ1] = "irq1", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", [FUNC_EXT_IRQ] = "ext_irq", [FUNC_MIIM] = "miim", + [FUNC_MIIM_a] = "miim_a", + [FUNC_MIIM_b] = "miim_b", + [FUNC_MIIM_c] = "miim_c", + [FUNC_MIIM_Sa] = "miim_slave_a", + [FUNC_MIIM_Sb] = "miim_slave_b", [FUNC_PHY_LED] = "phy_led", [FUNC_PCI_WAKE] = "pci_wake", [FUNC_MD] = "md", + [FUNC_OB_TRG] = "ob_trig", + [FUNC_OB_TRG_a] = "ob_trig_a", + [FUNC_OB_TRG_b] = "ob_trig_b", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", + [FUNC_PTPSYNC_1] = "ptpsync_1", + [FUNC_PTPSYNC_2] = "ptpsync_2", + [FUNC_PTPSYNC_3] = "ptpsync_3", + [FUNC_PTPSYNC_4] = "ptpsync_4", + [FUNC_PTPSYNC_5] = "ptpsync_5", + [FUNC_PTPSYNC_6] = "ptpsync_6", + [FUNC_PTPSYNC_7] = "ptpsync_7", [FUNC_PWM] = "pwm", + [FUNC_QSPI1] = "qspi1", + [FUNC_QSPI2] = "qspi2", + [FUNC_R] = "reserved", + [FUNC_RECO_a] = "reco_a", + [FUNC_RECO_b] = "reco_b", [FUNC_RECO_CLK] = "reco_clk", + [FUNC_SD] = "sd", [FUNC_SFP] = "sfp", + [FUNC_SFP_SD] = "sfp_sd", [FUNC_SG0] = "sg0", [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", + [FUNC_SGPIO_a] = "sgpio_a", + [FUNC_SGPIO_b] = "sgpio_b", [FUNC_SI] = "si", [FUNC_SI2] = "si2", [FUNC_TACHO] = "tacho", + [FUNC_TACHO_a] = "tacho_a", + [FUNC_TACHO_b] = "tacho_b", [FUNC_TWI] = "twi", [FUNC_TWI2] = "twi2", [FUNC_TWI3] = "twi3", [FUNC_TWI_SCL_M] = "twi_scl_m", + [FUNC_TWI_SLC_GATE] = "twi_slc_gate", + [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", + [FUNC_USB_H_a] = "usb_host_a", + [FUNC_USB_H_b] = "usb_host_b", + [FUNC_USB_H_c] = "usb_host_c", + [FUNC_USB_S_a] = "usb_slave_a", + [FUNC_USB_S_b] = "usb_slave_b", + [FUNC_USB_S_c] = "usb_slave_c", [FUNC_UART] = "uart", [FUNC_UART2] = "uart2", [FUNC_UART3] = "uart3", [FUNC_PLL_STAT] = "pll_stat", [FUNC_EMMC] = "emmc", + [FUNC_EMMC_SD] = "emmc_sd", [FUNC_REF_CLK] = "ref_clk", [FUNC_RCVRD_CLK] = "rcvrd_clk", }; @@ -145,6 +309,7 @@ struct ocelot_pmx_func { struct ocelot_pin_caps { unsigned int pin; unsigned char functions[OCELOT_FUNC_PER_PIN]; + unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ }; struct ocelot_pinctrl { @@ -676,6 +841,187 @@ static const struct pinctrl_pin_desc sparx5_pins[] = { SPARX5_PIN(63), }; +#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ +static struct ocelot_pin_caps lan966x_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3 \ + }, \ + .a_functions = { \ + FUNC_##f4, FUNC_##f5, FUNC_##f6, \ + FUNC_##f7 \ + }, \ +} + +/* Pinmuxing table taken from data sheet */ +/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ +LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); +LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); +LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); +LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); +LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); +LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); +LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); +LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); +LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); +LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); +LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); +LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); +LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); +LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); +LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); +LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); +LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); +LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); +LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); +LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); +LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); +LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); +LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); +LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); +LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); +LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); +LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); +LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); +LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); +LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); +LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); +LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); +LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); +LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); +LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); +LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); +LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); +LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); +LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); +LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); +LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); + +#define LAN966X_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &lan966x_pin_##n \ +} + +static const struct pinctrl_pin_desc lan966x_pins[] = { + LAN966X_PIN(0), + LAN966X_PIN(1), + LAN966X_PIN(2), + LAN966X_PIN(3), + LAN966X_PIN(4), + LAN966X_PIN(5), + LAN966X_PIN(6), + LAN966X_PIN(7), + LAN966X_PIN(8), + LAN966X_PIN(9), + LAN966X_PIN(10), + LAN966X_PIN(11), + LAN966X_PIN(12), + LAN966X_PIN(13), + LAN966X_PIN(14), + LAN966X_PIN(15), + LAN966X_PIN(16), + LAN966X_PIN(17), + LAN966X_PIN(18), + LAN966X_PIN(19), + LAN966X_PIN(20), + LAN966X_PIN(21), + LAN966X_PIN(22), + LAN966X_PIN(23), + LAN966X_PIN(24), + LAN966X_PIN(25), + LAN966X_PIN(26), + LAN966X_PIN(27), + LAN966X_PIN(28), + LAN966X_PIN(29), + LAN966X_PIN(30), + LAN966X_PIN(31), + LAN966X_PIN(32), + LAN966X_PIN(33), + LAN966X_PIN(34), + LAN966X_PIN(35), + LAN966X_PIN(36), + LAN966X_PIN(37), + LAN966X_PIN(38), + LAN966X_PIN(39), + LAN966X_PIN(40), + LAN966X_PIN(41), + LAN966X_PIN(42), + LAN966X_PIN(43), + LAN966X_PIN(44), + LAN966X_PIN(45), + LAN966X_PIN(46), + LAN966X_PIN(47), + LAN966X_PIN(48), + LAN966X_PIN(49), + LAN966X_PIN(50), + LAN966X_PIN(51), + LAN966X_PIN(52), + LAN966X_PIN(53), + LAN966X_PIN(54), + LAN966X_PIN(55), + LAN966X_PIN(56), + LAN966X_PIN(57), + LAN966X_PIN(58), + LAN966X_PIN(59), + LAN966X_PIN(60), + LAN966X_PIN(61), + LAN966X_PIN(62), + LAN966X_PIN(63), + LAN966X_PIN(64), + LAN966X_PIN(65), + LAN966X_PIN(66), + LAN966X_PIN(67), + LAN966X_PIN(68), + LAN966X_PIN(69), + LAN966X_PIN(70), + LAN966X_PIN(71), + LAN966X_PIN(72), + LAN966X_PIN(73), + LAN966X_PIN(74), + LAN966X_PIN(75), + LAN966X_PIN(76), + LAN966X_PIN(77), +}; + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(ocelot_function_names); @@ -709,6 +1055,9 @@ static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { if (function == p->functions[i]) return i; + + if (function == p->a_functions[i]) + return i + OCELOT_FUNC_PER_PIN; } return -1; @@ -744,6 +1093,36 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; + unsigned int p = pin->pin % 32; + int f; + + f = ocelot_pin_function_idx(info, group, selector); + if (f < 0) + return -EINVAL; + + /* + * f is encoded on three bits. + * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of + * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] + * This is racy because three registers can't be updated at the same time + * but it doesn't matter much for now. + * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets + */ + regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), + BIT(p), f << p); + regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), + BIT(p), (f >> 1) << p); + regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), + BIT(p), (f >> 2) << p); + + return 0; +} + #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -774,6 +1153,23 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } +static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + unsigned int p = offset % 32; + + regmap_update_bits(info->map, REG_ALT(0, info, offset), + BIT(p), 0); + regmap_update_bits(info->map, REG_ALT(1, info, offset), + BIT(p), 0); + regmap_update_bits(info->map, REG_ALT(2, info, offset), + BIT(p), 0); + + return 0; +} + static const struct pinmux_ops ocelot_pmx_ops = { .get_functions_count = ocelot_get_functions_count, .get_function_name = ocelot_get_function_name, @@ -783,6 +1179,15 @@ static const struct pinmux_ops ocelot_pmx_ops = { .gpio_request_enable = ocelot_gpio_request_enable, }; +static const struct pinmux_ops lan966x_pmx_ops = { + .get_functions_count = ocelot_get_functions_count, + .get_function_name = ocelot_get_function_name, + .get_function_groups = ocelot_get_function_groups, + .set_mux = lan966x_pinmux_set_mux, + .gpio_set_direction = ocelot_gpio_set_direction, + .gpio_request_enable = lan966x_gpio_request_enable, +}; + static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) { struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -1078,6 +1483,16 @@ static struct pinctrl_desc sparx5_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc lan966x_desc = { + .name = "lan966x-pinctrl", + .pins = lan966x_pins, + .npins = ARRAY_SIZE(lan966x_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &lan966x_pmx_ops, + .confops = &ocelot_confops, + .owner = THIS_MODULE, +}; + static int ocelot_create_group_func_map(struct device *dev, struct ocelot_pinctrl *info) { @@ -1337,6 +1752,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, + { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, }; From 3fe59cc4ff641b106cc24930204d4cd2c82f318f Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Lanka Date: Mon, 15 Nov 2021 23:39:45 -0800 Subject: [PATCH 34/98] dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings Add device tree binding Documentation details for Qualcomm SDX65 pinctrl driver. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/06234768890dc7572226f23d432e5a69a4d5b305.1637048107.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 195 ++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml new file mode 100644 index 000000000000..58dd34f4fcb5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX65 TLMM block + +maintainers: + - Vamsi krishna Lanka + +description: + This binding describes the Top Level Mode Multiplexer block found in the + SDX65 platform. + +properties: + compatible: + const: qcom,sdx65-tlmm + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '$-state': + oneOf: + - $ref: "#/$defs/qcom-sdx65-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sdx65-tlmm-state" +'$defs': + qcom-sdx65-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" + - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ] + minItems: 1 + maxItems: 150 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0x03000000 0xdc2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <2>; + bias-disable; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "blsp_uart1"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "blsp_uart1"; + bias-disable; + }; + }; + }; +... From bdbf104f8ee6e9b32e9819a8d3b4d8a3f8f4f1f2 Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Lanka Date: Mon, 15 Nov 2021 23:39:46 -0800 Subject: [PATCH 35/98] pinctrl: qcom: Add SDX65 pincontrol driver Add initial Qualcomm SDX65 pinctrl driver to support pin configuration with pinctrl framework for SDX65 SoC. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/13acb3cb36349487dee9745ab040d8f1344d2096.1637048107.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdx65.c | 967 +++++++++++++++++++++++++++ 3 files changed, 977 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sdx65.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index b9191f1abb1c..28a3ee987337 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -300,6 +300,15 @@ config PINCTRL_SM6350 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6350 platform. +config PINCTRL_SDX65 + tristate "Qualcomm Technologies Inc SDX65 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX65 platform. + config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 49b509080745..ecf20b5e615e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c new file mode 100644 index 000000000000..e793ea713965 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -0,0 +1,967 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx65_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "UFS_RESET"), + PINCTRL_PIN(109, "SDC1_RCLK"), + PINCTRL_PIN(110, "SDC1_CLK"), + PINCTRL_PIN(111, "SDC1_CMD"), + PINCTRL_PIN(112, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); + +static const unsigned int ufs_reset_pins[] = { 108 }; +static const unsigned int sdc1_rclk_pins[] = { 109 }; +static const unsigned int sdc1_clk_pins[] = { 110 }; +static const unsigned int sdc1_cmd_pins[] = { 111 }; +static const unsigned int sdc1_data_pins[] = { 112 }; + +enum sdx65_functions { + msm_mux_qlink0_wmss, + msm_mux_adsp_ext, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_char_exec, + msm_mux_coex_uart, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_ext_dbg, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mgpi_clk, + msm_mux_native_char, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pci_e, + msm_mux_pcie_clkreq, + msm_mux_pll_bist, + msm_mux_pll_ref, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_en, + msm_mux_qlink0_req, + msm_mux_qlink1_en, + msm_mux_qlink1_req, + msm_mux_qlink1_wmss, + msm_mux_qlink2_en, + msm_mux_qlink2_req, + msm_mux_qlink2_wmss, + msm_mux_sdc1_tb, + msm_mux_sec_mi2s, + msm_mux_spmi_coex, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", +}; +static const char * const uim2_data_groups[] = { + "gpio0", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80", + "gpio81", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; +static const char * const uim2_present_groups[] = { + "gpio1", +}; +static const char * const uim2_reset_groups[] = { + "gpio2", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", "gpio82", "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", + "gpio66", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", "gpio65", "gpio66", +}; +static const char * const char_exec_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_gpio_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ext_dbg_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ldo_en_groups[] = { + "gpio8", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const gcc_gp3_groups[] = { + "gpio11", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio12", +}; +static const char * const pri_mi2s_groups[] = { + "gpio13", "gpio14", "gpio15", +}; +static const char * const vsense_trigger_groups[] = { + "gpio13", +}; +static const char * const native_tsens_groups[] = { + "gpio14", +}; +static const char * const bimc_dte0_groups[] = { + "gpio14", "gpio59", +}; +static const char * const bimc_dte1_groups[] = { + "gpio15", "gpio61", +}; +static const char * const sec_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48", + "gpio49", +}; +static const char * const qdss_cti_groups[] = { + "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55", + "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66", + "gpio94", "gpio94", "gpio95", "gpio95", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", "gpio84", "gpio85", +}; +static const char * const gcc_gp1_groups[] = { + "gpio18", +}; +static const char * const jitter_bist_groups[] = { + "gpio19", +}; +static const char * const gcc_gp2_groups[] = { + "gpio19", +}; +static const char * const pll_bist_groups[] = { + "gpio22", +}; +static const char * const blsp_spi1_groups[] = { + "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const adsp_ext_groups[] = { + "gpio24", "gpio25", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio28", +}; +static const char * const native_tsense_groups[] = { + "gpio29", "gpio72", +}; +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", +}; +static const char * const pll_ref_groups[] = { + "gpio32", +}; +static const char * const pa_indicator_groups[] = { + "gpio33", +}; +static const char * const qlink0_en_groups[] = { + "gpio34", +}; +static const char * const qlink0_req_groups[] = { + "gpio35", +}; +static const char * const dbg_out_groups[] = { + "gpio35", +}; +static const char * const cri_trng_groups[] = { + "gpio36", +}; +static const char * const prng_rosc_groups[] = { + "gpio38", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const cri_trng1_groups[] = { + "gpio41", +}; +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; +static const char * const m_voc_groups[] = { + "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", +}; +static const char * const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; +static const char * const pci_e_groups[] = { + "gpio53", +}; +static const char * const tgu_ch0_groups[] = { + "gpio55", +}; +static const char * const pcie_clkreq_groups[] = { + "gpio56", +}; +static const char * const native_char_groups[] = { + "gpio26", "gpio29", "gpio33", "gpio42", "gpio57", +}; +static const char * const mgpi_clk_groups[] = { + "gpio61", "gpio71", +}; +static const char * const qlink2_wmss_groups[] = { + "gpio61", +}; +static const char * const i2s_mclk_groups[] = { + "gpio62", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const ldo_update_groups[] = { + "gpio62", +}; +static const char * const atest_char_groups[] = { + "gpio63", +}; +static const char * const atest_char3_groups[] = { + "gpio64", +}; +static const char * const atest_char2_groups[] = { + "gpio65", +}; +static const char * const atest_char1_groups[] = { + "gpio66", +}; +static const char * const uim1_data_groups[] = { + "gpio67", +}; +static const char * const atest_char0_groups[] = { + "gpio67", +}; +static const char * const uim1_present_groups[] = { + "gpio68", +}; +static const char * const uim1_reset_groups[] = { + "gpio69", +}; +static const char * const uim1_clk_groups[] = { + "gpio70", +}; +static const char * const qlink2_en_groups[] = { + "gpio71", +}; +static const char * const qlink1_en_groups[] = { + "gpio72", +}; +static const char * const qlink1_req_groups[] = { + "gpio73", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio74", +}; +static const char * const coex_uart2_groups[] = { + "gpio75", "gpio76", "gpio102", "gpio103", +}; +static const char * const spmi_coex_groups[] = { + "gpio75", "gpio76", +}; +static const char * const qlink2_req_groups[] = { + "gpio77", +}; +static const char * const spmi_vgi_groups[] = { + "gpio78", "gpio79", +}; +static const char * const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio84", "gpio85", "gpio90", +}; +static const char * const ebi2_a_groups[] = { + "gpio89", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio93", +}; +static const char * const sdc1_tb_groups[] = { + "gpio106", +}; + +static const struct msm_function sdx65_functions[] = { + FUNCTION(qlink0_wmss), + FUNCTION(adsp_ext), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(audio_ref), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(char_exec), + FUNCTION(coex_uart), + FUNCTION(coex_uart2), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ebi0_wrcdc), + FUNCTION(ebi2_a), + FUNCTION(ebi2_lcd), + FUNCTION(ext_dbg), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_plltest), + FUNCTION(gpio), + FUNCTION(i2s_mclk), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(m_voc), + FUNCTION(mgpi_clk), + FUNCTION(native_char), + FUNCTION(native_tsens), + FUNCTION(native_tsense), + FUNCTION(nav_gpio), + FUNCTION(pa_indicator), + FUNCTION(pci_e), + FUNCTION(pcie_clkreq), + FUNCTION(pll_bist), + FUNCTION(pll_ref), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qlink0_en), + FUNCTION(qlink0_req), + FUNCTION(qlink1_en), + FUNCTION(qlink1_req), + FUNCTION(qlink1_wmss), + FUNCTION(qlink2_en), + FUNCTION(qlink2_req), + FUNCTION(qlink2_wmss), + FUNCTION(sdc1_tb), + FUNCTION(sec_mi2s), + FUNCTION(spmi_coex), + FUNCTION(spmi_vgi), + FUNCTION(tgu_ch0), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdx65_groups[] = { + [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _), + [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _), + [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _), + [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _), + [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _), + [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _), + [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _), + [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _), + [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _), + [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _), + [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _), + [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _), + [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _), + [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _), + [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _), + [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), + [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _), + [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), + [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), + [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _), + [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _), + [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _), + [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _), + [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _), + [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _), + [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _), + [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _), + [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _), + [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), + [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), + [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), + [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [108] = UFS_RESET(ufs_reset, 0x0), + [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = { + {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25}, + {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31}, + {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70}, + {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45}, + {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53}, + {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59}, + {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67}, + {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74}, + {99, 75}, {103, 78}, {104, 79} +}; + +static const struct msm_pinctrl_soc_data sdx65_pinctrl = { + .pins = sdx65_pins, + .npins = ARRAY_SIZE(sdx65_pins), + .functions = sdx65_functions, + .nfunctions = ARRAY_SIZE(sdx65_functions), + .groups = sdx65_groups, + .ngroups = ARRAY_SIZE(sdx65_groups), + .ngpios = 109, + .wakeirq_map = sdx65_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map), +}; + +static int sdx65_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdx65_pinctrl); +} + +static const struct of_device_id sdx65_pinctrl_of_match[] = { + { .compatible = "qcom,sdx65-tlmm", }, + { }, +}; + +static struct platform_driver sdx65_pinctrl_driver = { + .driver = { + .name = "sdx65-tlmm", + .of_match_table = sdx65_pinctrl_of_match, + }, + .probe = sdx65_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx65_pinctrl_init(void) +{ + return platform_driver_register(&sdx65_pinctrl_driver); +} +arch_initcall(sdx65_pinctrl_init); + +static void __exit sdx65_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx65_pinctrl_driver); +} +module_exit(sdx65_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); From e3da3323dabf27c4aa9a51c7832e7f976fe072f4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 12 Nov 2021 12:53:40 +0100 Subject: [PATCH 36/98] dt-bindings: pinctrl: qcom,pmic-gpio: Add compatible for PM8019 Add pmic-gpio compatible string for pm8019 pmic. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211112115342.17100-1-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 8952b4cc1262..55a46dec56b6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -26,6 +26,7 @@ properties: - qcom,pm8005-gpio - qcom,pm8008-gpio - qcom,pm8018-gpio + - qcom,pm8019-gpio - qcom,pm8038-gpio - qcom,pm8058-gpio - qcom,pm8150-gpio From f347438356e1c69799b21bed7dc8654f58124592 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 12 Nov 2021 12:53:41 +0100 Subject: [PATCH 37/98] pinctrl: qcom-pmic-gpio: Add support for pm8019 PM8019 provides 6 GPIOs. Add a compatible to support that. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211112115342.17100-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 5283d5e9e8bc..1ae3895a7ff3 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1151,6 +1151,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, + { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 }, From bebc49c1e5f64641831758d72a26a8dd2c61d38a Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Tue, 16 Nov 2021 11:08:03 +0530 Subject: [PATCH 38/98] pinctrl: qcom: Add egpio feature support egpio is a scheme which allows special power Island Domain IOs (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. With this scheme, an IO can be controlled both by the cpu running linux and the Island processor. This provides great flexibility to re-purpose the Island IOs for regular TLMM usecases. 2 new bits are added to ctl_reg, egpio_present is a read only bit which shows if egpio feature is available or not on a given gpio. egpio_enable is the read/write bit and only effective if egpio_present is 1. Once its set, the Island IO is controlled from Chip TLMM. egpio_enable when set to 0 means the GPIO is used as Island Domain IO. To support this we add a new function 'egpio' which can be used to set the egpio_enable to 0, for any other TLMM controlled functions we set the egpio_enable to 1. Signed-off-by: Prasad Sodagudi Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1637041084-3299-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 15 +++++++++++++-- drivers/pinctrl/qcom/pinctrl-msm.h | 10 ++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 8476a8ac4451..ae09e2dd8a50 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -185,6 +185,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int irq = irq_find_mapping(gc->irq.domain, group); struct irq_data *d = irq_get_irq_data(irq); unsigned int gpio_func = pctrl->soc->gpio_func; + unsigned int egpio_func = pctrl->soc->egpio_func; const struct msm_pingroup *g; unsigned long flags; u32 val, mask; @@ -218,8 +219,18 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_ctl(pctrl, g); - val &= ~mask; - val |= i << g->mux_bit; + + if (egpio_func && i == egpio_func) { + if (val & BIT(g->egpio_present)) + val &= ~BIT(g->egpio_enable); + } else { + val &= ~mask; + val |= i << g->mux_bit; + /* Claim ownership of pin if egpio capable */ + if (egpio_func && val & BIT(g->egpio_present)) + val |= BIT(g->egpio_enable); + } + msm_writel_ctl(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index e31a5167c91e..dd0d949f7a9e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -77,6 +77,8 @@ struct msm_pingroup { unsigned drv_bit:5; unsigned od_bit:5; + unsigned egpio_enable:5; + unsigned egpio_present:5; unsigned oe_bit:5; unsigned in_bit:5; unsigned out_bit:5; @@ -119,6 +121,13 @@ struct msm_gpio_wakeirq_map { * to be aware that their parent can't handle dual * edge interrupts. * @gpio_func: Which function number is GPIO (usually 0). + * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in + * hardware this is a mux 1-level above the TLMM, we'll treat + * it as if this is just another mux state of the TLMM. Since + * it doesn't really map to hardware, we'll allocate a virtual + * function number for eGPIO and any time we see that function + * number used we'll treat it as a request to mux away from + * our TLMM towards another owner. */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -136,6 +145,7 @@ struct msm_pinctrl_soc_data { unsigned int nwakeirq_map; bool wakeirq_dual_edge_errata; unsigned int gpio_func; + unsigned int egpio_func; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; From 5277525edfd80ab65503bc13f9655509cfc463af Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 16 Nov 2021 11:08:04 +0530 Subject: [PATCH 39/98] pinctrl: qcom: sc7280: Add egpio support sc7280 supports the egpio feature, GPIOs ranging from 144 to 174 (31 GPIOs) support it, we define gpio_func to 9, which is an unused function for all these pins on sc7280. Signed-off-by: Rajendra Nayak Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637041084-3299-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-sc7280.c | 75 ++++++++++++++++----------- 1 file changed, 44 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 9017ede409c9..31df55c79cb3 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -43,6 +43,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -520,6 +522,7 @@ enum sc7280_functions { msm_mux_dp_lcd, msm_mux_edp_hot, msm_mux_edp_lcd, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -658,6 +661,14 @@ static const char * const gpio_groups[] = { "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", }; +static const char * const egpio_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", +}; static const char * const atest_char_groups[] = { "gpio81", }; @@ -1150,6 +1161,7 @@ static const struct msm_function sc7280_functions[] = { FUNCTION(dp_lcd), FUNCTION(edp_hot), FUNCTION(edp_lcd), + FUNCTION(egpio), FUNCTION(gcc_gp1), FUNCTION(gcc_gp2), FUNCTION(gcc_gp3), @@ -1408,37 +1420,37 @@ static const struct msm_pingroup sc7280_groups[] = { [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), - [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), - [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), - [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), - [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), - [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), - [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), - [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, _), - [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, _), - [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, _), - [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, _), - [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _), - [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _), - [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, _), - [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, _), - [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _), - [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _), - [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _), - [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _), - [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _), - [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _), - [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, egpio), [175] = UFS_RESET(ufs_reset, 0xbe000), [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6), [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6), @@ -1481,6 +1493,7 @@ static const struct msm_pinctrl_soc_data sc7280_pinctrl = { .ngpios = 176, .wakeirq_map = sc7280_pdc_map, .nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map), + .egpio_func = 9, }; static int sc7280_pinctrl_probe(struct platform_device *pdev) From ef874e03a67dd3d07c0a135e32eaf84ab0445273 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 16 Nov 2021 16:35:14 +0100 Subject: [PATCH 40/98] pinctrl: spmi-gpio: Add support for PM2250 PM2250, commonly combined with QCM2290, provides ten SPMI GPIOs. Signed-off-by: Loic Poulain Link: https://lore.kernel.org/r/1637076915-3280-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 1ae3895a7ff3..f2eac3b05d67 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1141,6 +1141,7 @@ static int pmic_gpio_remove(struct platform_device *pdev) } static const struct of_device_id pmic_gpio_of_match[] = { + { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 }, /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ From f35172c030dba5a1ff9dfe47cbeb123be45d75c7 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 16 Nov 2021 16:35:15 +0100 Subject: [PATCH 41/98] dt-bindings: qcom,pmic-gpio: Add pm2250 compatible string Add compatible strings for pm2250 SPMI GPIO to documentation. Signed-off-by: Loic Poulain Link: https://lore.kernel.org/r/1637076915-3280-2-git-send-email-loic.poulain@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 55a46dec56b6..3e02b695b0c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -17,6 +17,7 @@ properties: compatible: items: - enum: + - qcom,pm2250-gpio - qcom,pm660-gpio - qcom,pm660l-gpio - qcom,pm6150-gpio From 1dd19cae155208065277f01dc61fe8897b6d2a29 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Tue, 9 Nov 2021 09:11:39 +0900 Subject: [PATCH 42/98] dt-bindings: pinctrl: uniphier: Add child node definitions to describe pin mux and configuration In arch/arm/boot/dts/uniphier-pinctrl.dtsi, there are child nodes of pinctrl that defines pinmux and pincfg, however, there are no rules about that in dt-bindings. 'make dtbs_check' results an error with the following message: pinctrl: 'ain1', 'ain2', 'ainiec1', 'aout', 'aout1', 'aout2', ... ... 'usb2', 'usb3' do not match any of the regexes: 'pinctrl-[0-9]+' To avoid the issue, add the rules of pinmux and pincfg in each child node and grandchild node. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1636416699-21033-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Linus Walleij --- .../pinctrl/socionext,uniphier-pinctrl.yaml | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml index a804d9bc1602..27c5762b9cf8 100644 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -26,11 +26,45 @@ properties: - socionext,uniphier-pxs3-pinctrl - socionext,uniphier-nx1-pinctrl +additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + phandle: true + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + phandle: true + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + unevaluatedProperties: false + required: - compatible -additionalProperties: false - examples: - | // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. From ad96111e658a959e55894863a758e6c2cf31bb5e Mon Sep 17 00:00:00 2001 From: Colin Foster Date: Fri, 19 Nov 2021 11:59:25 -0800 Subject: [PATCH 43/98] pinctrl: ocelot: combine get resource and ioremap into single call Simple cleanup to make two function calls only one. Signed-off-by: Colin Foster Link: https://lore.kernel.org/r/20211119195928.2498441-2-colin.foster@in-advantage.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 875e3f319d7b..25cb62e21e50 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1761,7 +1761,6 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; void __iomem *base; - struct resource *res; int ret; struct regmap_config regmap_config = { .reg_bits = 32, @@ -1794,8 +1793,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) /* Pinconf registers */ if (info->desc->confops) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - base = devm_ioremap_resource(dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); else From a159c2b4cb7517fe11f3ce698f792126e964fc7a Mon Sep 17 00:00:00 2001 From: Colin Foster Date: Fri, 19 Nov 2021 11:59:26 -0800 Subject: [PATCH 44/98] pinctrl: ocelot: update pinctrl to automatic base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit struct gpio_chip recommends passing -1 as base to gpiolib. Doing so avoids conflicts when the chip is external and gpiochip0 already exists. Signed-off-by: Colin Foster Tested-by: Clément Léger Link: https://lore.kernel.org/r/20211119195928.2498441-3-colin.foster@in-advantage.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 25cb62e21e50..d59d684d3496 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1723,7 +1723,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc = &info->gpio_chip; gc->ngpio = info->desc->npins; gc->parent = &pdev->dev; - gc->base = 0; + gc->base = -1; gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; From 076d9e71bcf8a80c94bf1d46c424977472c97078 Mon Sep 17 00:00:00 2001 From: Colin Foster Date: Fri, 19 Nov 2021 11:59:27 -0800 Subject: [PATCH 45/98] pinctrl: ocelot: convert pinctrl to regmap In order to allow external control via SPI, memory-mapped areas must be changed to use the generic regmap interface. This is step 1, and is followed by an implementation that allows a custom regmap. Signed-off-by: Colin Foster Link: https://lore.kernel.org/r/20211119195928.2498441-4-colin.foster@in-advantage.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 65 +++++++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index d59d684d3496..42aab9ba049a 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -317,7 +317,7 @@ struct ocelot_pinctrl { struct pinctrl_dev *pctl; struct gpio_chip gpio_chip; struct regmap *map; - void __iomem *pincfg; + struct regmap *pincfg; struct pinctrl_desc *desc; struct ocelot_pmx_func func[FUNC_MAX]; u8 stride; @@ -1224,7 +1224,11 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info, int ret = -EOPNOTSUPP; if (info->pincfg) { - u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); + u32 regcfg; + + ret = regmap_read(info->pincfg, pin, ®cfg); + if (ret) + return ret; ret = 0; switch (reg) { @@ -1248,6 +1252,24 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info, return ret; } +static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, + u32 clrbits, u32 setbits) +{ + u32 val; + int ret; + + ret = regmap_read(info->pincfg, regaddr, &val); + if (ret) + return ret; + + val &= ~clrbits; + val |= setbits; + + ret = regmap_write(info->pincfg, regaddr, val); + + return ret; +} + static int ocelot_hw_set_value(struct ocelot_pinctrl *info, unsigned int pin, unsigned int reg, @@ -1256,21 +1278,23 @@ static int ocelot_hw_set_value(struct ocelot_pinctrl *info, int ret = -EOPNOTSUPP; if (info->pincfg) { - void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); ret = 0; switch (reg) { case PINCONF_BIAS: - ocelot_clrsetbits(regaddr, BIAS_BITS, val); + ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, + val); break; case PINCONF_SCHMITT: - ocelot_clrsetbits(regaddr, SCHMITT_BIT, val); + ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, + val); break; case PINCONF_DRIVE_STRENGTH: if (val <= 3) - ocelot_clrsetbits(regaddr, DRIVE_BITS, val); + ret = ocelot_pincfg_clrsetbits(info, pin, + DRIVE_BITS, val); else ret = -EINVAL; break; @@ -1756,10 +1780,31 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { {}, }; +static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) +{ + void __iomem *base; + + const struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 32, + }; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); + return NULL; + } + + return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); +} + static int ocelot_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; + struct regmap *pincfg; void __iomem *base; int ret; struct regmap_config regmap_config = { @@ -1793,11 +1838,11 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) /* Pinconf registers */ if (info->desc->confops) { - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); + pincfg = ocelot_pinctrl_create_pincfg(pdev); + if (IS_ERR(pincfg)) + dev_dbg(dev, "Failed to create pincfg regmap\n"); else - info->pincfg = base; + info->pincfg = pincfg; } ret = ocelot_pinctrl_register(pdev, info); From 2afbbab45c261abf5a03584b164a526933995efd Mon Sep 17 00:00:00 2001 From: Colin Foster Date: Fri, 19 Nov 2021 11:59:28 -0800 Subject: [PATCH 46/98] pinctrl: microchip-sgpio: update to support regmap Adopt regmap instead of a direct memory map so that custom regmaps and other interfaces can be supported. Signed-off-by: Colin Foster Link: https://lore.kernel.org/r/20211119195928.2498441-5-colin.foster@in-advantage.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-microchip-sgpio.c | 47 +++++++++++++++++------ 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 78765faa245a..8e081c90bdb2 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "core.h" @@ -113,7 +114,7 @@ struct sgpio_priv { u32 bitcount; u32 ports; u32 clock; - u32 __iomem *regs; + struct regmap *regs; const struct sgpio_properties *properties; }; @@ -134,31 +135,42 @@ static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) return bit + port * priv->bitcount; } -static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) +static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; - - return readl(reg); + return priv->properties->regoff[rno] + off; } -static inline void sgpio_writel(struct sgpio_priv *priv, +static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) +{ + u32 addr = sgpio_get_addr(priv, rno, off); + u32 val = 0; + int ret; + + ret = regmap_read(priv->regs, addr, &val); + WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); + + return val; +} + +static void sgpio_writel(struct sgpio_priv *priv, u32 val, u32 rno, u32 off) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + u32 addr = sgpio_get_addr(priv, rno, off); + int ret; - writel(val, reg); + ret = regmap_write(priv->regs, addr, val); + WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); } static inline void sgpio_clrsetbits(struct sgpio_priv *priv, u32 rno, u32 off, u32 clear, u32 set) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; - u32 val = readl(reg); + u32 val = sgpio_readl(priv, rno, off); val &= ~clear; val |= set; - writel(val, reg); + sgpio_writel(priv, val, rno, off); } static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) @@ -807,7 +819,13 @@ static int microchip_sgpio_probe(struct platform_device *pdev) struct reset_control *reset; struct sgpio_priv *priv; struct clk *clk; + u32 __iomem *regs; u32 val; + struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -832,9 +850,14 @@ static int microchip_sgpio_probe(struct platform_device *pdev) return -EINVAL; } - priv->regs = devm_platform_ioremap_resource(pdev, 0); + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); + priv->properties = device_get_match_data(dev); priv->in.is_input = true; From 16dd3bb5c190654854c0846ee433076139f71c6a Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Tue, 23 Nov 2021 08:36:17 +0000 Subject: [PATCH 47/98] pinctrl: samsung: Make symbol 'exynos7885_pin_ctrl' static The sparse tool complains as follows: drivers/pinctrl/samsung/pinctrl-exynos-arm64.c:490:31: warning: symbol 'exynos7885_pin_ctrl' was not declared. Should it be static? This symbol is not used outside of pinctrl-exynos-arm64.c, so marks it static. Fixes: b0ef7b1a7a07 ("pinctrl: samsung: Add Exynos7885 SoC specific data") Signed-off-by: Wei Yongjun Link: https://lore.kernel.org/r/20211123083617.2366756-1-weiyongjun1@huawei.com Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b174796081ef..2e490e7696f4 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -487,7 +487,7 @@ static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), }; -const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { +static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { { /* pin-controller instance 0 Alive data */ .pin_banks = exynos7885_pin_banks0, From 6b4542664c2d1fc7a770f0a4182ef5e36672d313 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 22 Nov 2021 23:04:23 +0100 Subject: [PATCH 48/98] pinctrl: baytrail: Set IRQCHIP_SET_TYPE_MASKED flag on the irqchip The byt_irq_type function ends with the IRQ masked, this means that calls to irq_set_irq_type() while the IRQ is enabled end up masking it, which is wrong. Add the IRQCHIP_SET_TYPE_MASKED flag to fix this. This will make the IRQ core call mask() + unmask() on the IRQ around a set_type() call when the IRQ is enabled at the type of the call. Note in practice irq_set_irq_type() getting called while the IRQ is enabled almost never happens. I hit this with a buggy DSDT where a wrongly active (_STA returns 0xf) I2C ACPI devices point to an IRQ already in use by an _AEI handler, leading to the irq_set_irq_type() call in acpi_dev_gpio_irq_get_by() getting called while the IRQ is enabled. Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-baytrail.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 8f23d126c6a7..4c01333e1406 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1577,7 +1577,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) vg->irqchip.irq_mask = byt_irq_mask, vg->irqchip.irq_unmask = byt_irq_unmask, vg->irqchip.irq_set_type = byt_irq_type, - vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE, + vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED, girq = &gc->irq; girq->chip = &vg->irqchip; From deee705a1c9cce9c7eb699d529f1c0b3c80d339d Mon Sep 17 00:00:00 2001 From: Dominik Kobinski Date: Thu, 25 Nov 2021 22:56:26 +0100 Subject: [PATCH 49/98] dt-bindings: pinctrl: qcom: pmic-gpio: Document pm8226 compatible Suggested-by: Ivaylo Ivanov Signed-off-by: Dominik Kobinski Link: https://lore.kernel.org/r/20211125215626.62447-1-dominikkobinski314@gmail.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 3e02b695b0c3..9400b665a46f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -32,6 +32,7 @@ properties: - qcom,pm8058-gpio - qcom,pm8150-gpio - qcom,pm8150b-gpio + - qcom,pm8226-gpio - qcom,pm8350-gpio - qcom,pm8350b-gpio - qcom,pm8350c-gpio From bdfbef2d29dcdc79e2abf3085d4be6a844a06e34 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Nov 2021 11:56:48 +0100 Subject: [PATCH 50/98] pinctrl: cherryview: Don't use selection 0 to mark an interrupt line as unused The selection 0 is a perfectly valid, so stop using it to have the special meaning of interrupt line not used in the intr_lines. Instead introduce a special CHV_INVALID_HWIRQ value, derived from INVALID_HWIRQ. which is never a valid selection and use that to indicate unused interrupt lines. Cc: Yauhen Kharuzhy Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 980099028cf8..978eddd89ea2 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -73,6 +73,8 @@ struct intel_pad_context { u32 padctrl1; }; +#define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ) + /** * struct intel_community_context - community context for Cherryview * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) @@ -812,7 +814,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, /* Reset the interrupt mapping */ for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { if (cctx->intr_lines[i] == offset) { - cctx->intr_lines[i] = 0; + cctx->intr_lines[i] = CHV_INVALID_HWIRQ; break; } } @@ -1319,7 +1321,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) else handler = handle_edge_irq; - if (!cctx->intr_lines[intsel]) { + if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { irq_set_handler_locked(d, handler); cctx->intr_lines[intsel] = pin; } @@ -1412,6 +1414,12 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) unsigned int offset; offset = cctx->intr_lines[intr_line]; + if (offset == CHV_INVALID_HWIRQ) { + dev_err(pctrl->dev, "interrupt on unused interrupt line %u\n", + intr_line); + continue; + } + generic_handle_domain_irq(gc->irq.domain, offset); } @@ -1617,11 +1625,13 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function, static int chv_pinctrl_probe(struct platform_device *pdev) { const struct intel_pinctrl_soc_data *soc_data; + struct intel_community_context *cctx; struct intel_community *community; struct device *dev = &pdev->dev; struct acpi_device *adev = ACPI_COMPANION(dev); struct intel_pinctrl *pctrl; acpi_status status; + unsigned int i; int ret, irq; soc_data = intel_pinctrl_get_soc_data(pdev); @@ -1663,6 +1673,10 @@ static int chv_pinctrl_probe(struct platform_device *pdev) if (!pctrl->context.communities) return -ENOMEM; + cctx = &pctrl->context.communities[0]; + for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) + cctx->intr_lines[i] = CHV_INVALID_HWIRQ; + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From 07199dbf8cae36c973a89552fee83dd4e0a75972 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Nov 2021 11:56:49 +0100 Subject: [PATCH 51/98] pinctrl: cherryview: Do not allow the same interrupt line to be used by 2 pins It is impossible to use the same interrupt line for 2 pins, this will result in the interrupts only being delivered to the IRQ handler for the pin for which chv_gpio_irq_type() was called last. The pinctrl-cherryview.c code relies on the BIOS to correctly setup the interrupt line, but there is a BIOS bug on at least the Medion Akoya E1239T and the GPD win models where both INT33FF:02 pin 8, used by the powerbutton and INT33FF:02 pin 21 used as IRQ input for the accelerometer are mapped to interrupt line 0. This causes 2 problems: 1. The accelerometer IRQ does not work, since the power button is probed later taking over the intr_lines[0] slot. 2. Since the accelerometer IRQ is not marked as wakeup, interrupt line 0 gets masked on suspend, causing the power button to not work to wake the system from suspend. Likewise on the Lenovo Yogabook, which has a touchscreen as keyboard and the keyboard half of the tablet also has a Wacom digitizer, the BIOS by default assigns the same interrupt line to the GPIOs used for their interrupts. Fix these problems by adding a check for this and assigning a new interrupt line to the 2nd pin for which chv_gpio_irq_type() gets called. With this fix in place the following 2 messages show up in dmesg on the Medion Akoya E1239T and the GPD win: cherryview-pinctrl INT33FF:02: interrupt line 0 is used by both pin 21 and pin 8 cherryview-pinctrl INT33FF:02: changing the interrupt line for pin 8 to 15 And the following gets logged on the Lenovo Yogabook: cherryview-pinctrl INT33FF:01: interrupt-line 0 is used by both pin 49 and pin 56 cherryview-pinctrl INT33FF:01: changing the interrupt line for pin 56 to 7 Note commit 9747070c11d6 ("Input: axp20x-pek - always register interrupt handlers") was added as a work around for the power button not being able to wakeup the system. This relies on using the PMIC's connection to the power button but that only works on systems with the AXP288 PMIC. Once this fix has been merged that workaround can be removed. Cc: Yauhen Kharuzhy Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 69 +++++++++++++++++++--- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 978eddd89ea2..b60a3e456ca4 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1323,6 +1323,8 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { irq_set_handler_locked(d, handler); + dev_dbg(pctrl->dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n", + intsel, pin); cctx->intr_lines[intsel] = pin; } raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -1332,17 +1334,73 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) return 0; } +static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) +{ + struct intel_community_context *cctx = &pctrl->context.communities[0]; + const struct intel_community *community = &pctrl->communities[0]; + u32 value, intsel; + int i; + + value = chv_readl(pctrl, pin, CHV_PADCTRL0); + intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT; + + if (cctx->intr_lines[intsel] == pin) + return 0; + + if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { + dev_dbg(pctrl->dev, "using interrupt line %u for pin %u\n", intsel, pin); + cctx->intr_lines[intsel] = pin; + return 0; + } + + /* + * The interrupt line selected by the BIOS is already in use by + * another pin, this is a known BIOS bug found on several models. + * But this may also be caused by Linux deciding to use a pin as + * IRQ which was not expected to be used as such by the BIOS authors, + * so log this at info level only. + */ + dev_info(pctrl->dev, "interrupt line %u is used by both pin %u and pin %u\n", + intsel, cctx->intr_lines[intsel], pin); + + if (chv_pad_locked(pctrl, pin)) + return -EBUSY; + + /* + * The BIOS fills the interrupt lines from 0 counting up, start at + * the other end to find a free interrupt line to workaround this. + */ + for (i = community->nirqs - 1; i >= 0; i--) { + if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ) + break; + } + if (i < 0) + return -EBUSY; + + dev_info(pctrl->dev, "changing the interrupt line for pin %u to %d\n", pin, i); + + value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); + chv_writel(pctrl, pin, CHV_PADCTRL0, value); + cctx->intr_lines[i] = pin; + + return 0; +} + static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); - struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); unsigned long flags; u32 value; + int ret; raw_spin_lock_irqsave(&chv_lock, flags); + ret = chv_gpio_set_intr_line(pctrl, pin); + if (ret) + goto out_unlock; + /* * Pins which can be used as shared interrupt are configured in * BIOS. Driver trusts BIOS configurations and assigns different @@ -1377,20 +1435,15 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) chv_writel(pctrl, pin, CHV_PADCTRL1, value); } - value = chv_readl(pctrl, pin, CHV_PADCTRL0); - value &= CHV_PADCTRL0_INTSEL_MASK; - value >>= CHV_PADCTRL0_INTSEL_SHIFT; - - cctx->intr_lines[value] = pin; - if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); else if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); +out_unlock: raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; + return ret; } static void chv_gpio_irq_handler(struct irq_desc *desc) From db1b2a8caf5b4954aa62ead5b0580948656eac43 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 26 Nov 2021 22:35:42 +0200 Subject: [PATCH 52/98] pinctrl: cherryview: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 57 +++++++++++----------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index b60a3e456ca4..abffda1fd51e 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -711,6 +711,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; const struct intel_pingroup *grp; unsigned long flags; int i; @@ -722,9 +723,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, /* Check first that the pad is not locked */ for (i = 0; i < grp->npins; i++) { if (chv_pad_locked(pctrl, grp->pins[i])) { - dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", - grp->pins[i]); raw_spin_unlock_irqrestore(&chv_lock, flags); + dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]); return -EBUSY; } } @@ -759,8 +759,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, value |= CHV_PADCTRL1_INVRXTX_TXENABLE; chv_writel(pctrl, pin, CHV_PADCTRL1, value); - dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", - pin, mode, invert_oe ? "" : "not "); + dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode, + invert_oe ? "" : "not "); } raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -1060,6 +1060,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int nconfigs) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; enum pin_config_param param; int i, ret; u32 arg; @@ -1096,8 +1097,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, return -ENOTSUPP; } - dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, - param, arg); + dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg); } return 0; @@ -1304,6 +1304,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + struct device *dev = pctrl->dev; struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); irq_flow_handler_t handler; @@ -1323,7 +1324,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { irq_set_handler_locked(d, handler); - dev_dbg(pctrl->dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n", + dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n", intsel, pin); cctx->intr_lines[intsel] = pin; } @@ -1336,6 +1337,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) { + struct device *dev = pctrl->dev; struct intel_community_context *cctx = &pctrl->context.communities[0]; const struct intel_community *community = &pctrl->communities[0]; u32 value, intsel; @@ -1348,7 +1350,7 @@ static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) return 0; if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { - dev_dbg(pctrl->dev, "using interrupt line %u for pin %u\n", intsel, pin); + dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin); cctx->intr_lines[intsel] = pin; return 0; } @@ -1360,8 +1362,8 @@ static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) * IRQ which was not expected to be used as such by the BIOS authors, * so log this at info level only. */ - dev_info(pctrl->dev, "interrupt line %u is used by both pin %u and pin %u\n", - intsel, cctx->intr_lines[intsel], pin); + dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel, + cctx->intr_lines[intsel], pin); if (chv_pad_locked(pctrl, pin)) return -EBUSY; @@ -1377,7 +1379,7 @@ static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) if (i < 0) return -EBUSY; - dev_info(pctrl->dev, "changing the interrupt line for pin %u to %d\n", pin, i); + dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i); value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); chv_writel(pctrl, pin, CHV_PADCTRL0, value); @@ -1450,6 +1452,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + struct device *dev = pctrl->dev; const struct intel_community *community = &pctrl->communities[0]; struct intel_community_context *cctx = &pctrl->context.communities[0]; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -1468,8 +1471,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) offset = cctx->intr_lines[intr_line]; if (offset == CHV_INVALID_HWIRQ) { - dev_err(pctrl->dev, "interrupt on unused interrupt line %u\n", - intr_line); + dev_err(dev, "interrupt on unused interrupt line %u\n", intr_line); continue; } @@ -1573,17 +1575,16 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip) static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); + struct device *dev = pctrl->dev; const struct intel_community *community = &pctrl->communities[0]; const struct intel_padgroup *gpp; int ret, i; for (i = 0; i < community->ngpps; i++) { gpp = &community->gpps[i]; - ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), - gpp->base, gpp->base, - gpp->size); + ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); if (ret) { - dev_err(pctrl->dev, "failed to add GPIO pin range\n"); + dev_err(dev, "failed to add GPIO pin range\n"); return ret; } } @@ -1596,15 +1597,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) const struct intel_community *community = &pctrl->communities[0]; const struct intel_padgroup *gpp; struct gpio_chip *chip = &pctrl->chip; + struct device *dev = pctrl->dev; bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); int ret, i, irq_base; *chip = chv_gpio_chip; chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; - chip->label = dev_name(pctrl->dev); + chip->label = dev_name(dev); chip->add_pin_ranges = chv_gpio_add_pin_ranges; - chip->parent = pctrl->dev; + chip->parent = dev; chip->base = -1; pctrl->irq = irq; @@ -1626,17 +1628,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) if (need_valid_mask) { chip->irq.init_valid_mask = chv_init_irq_valid_mask; } else { - irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, - pctrl->soc->npins, NUMA_NO_NODE); + irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); if (irq_base < 0) { - dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); + dev_err(dev, "Failed to allocate IRQ numbers\n"); return irq_base; } } - ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); + ret = devm_gpiochip_add_data(dev, chip, pctrl); if (ret) { - dev_err(pctrl->dev, "Failed to register gpiochip\n"); + dev_err(dev, "Failed to register gpiochip\n"); return ret; } @@ -1834,15 +1835,15 @@ static int chv_pinctrl_resume_noirq(struct device *dev) val &= ~CHV_PADCTRL0_GPIORXSTATE; if (ctx->padctrl0 != val) { chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); - dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", - desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0)); + dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number, + chv_readl(pctrl, desc->number, CHV_PADCTRL0)); } val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); if (ctx->padctrl1 != val) { chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); - dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", - desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1)); + dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number, + chv_readl(pctrl, desc->number, CHV_PADCTRL1)); } } From 361856dd735ed3092c00143f2e8a73c0e1f42118 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:32 +0000 Subject: [PATCH 53/98] pinctrl: apple: fix some formatting issues Reflow some of the code now that the extra '_gpio' was removed. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-2-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 69 +++++++++++----------------- 1 file changed, 28 insertions(+), 41 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index a7861079a650..7299c7686f7f 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -75,13 +75,13 @@ struct regmap_config regmap_config = { // No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, - unsigned int pin, u32 mask, u32 value) + unsigned int pin, u32 mask, u32 value) { regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); } static uint32_t apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, - unsigned int pin) + unsigned int pin) { unsigned int val = 0; @@ -92,9 +92,9 @@ static uint32_t apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, /* Pin controller functions */ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *node, - struct pinctrl_map **map, - unsigned *num_maps) + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) { unsigned reserved_maps; struct apple_gpio_pinctrl *pctl; @@ -119,8 +119,7 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, num_pins = ret; - ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, - num_pins); + ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins); if (ret) return ret; @@ -138,11 +137,10 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, } group_name = pinctrl_generic_get_group_name(pctldev, pin); - function_name = - pinmux_generic_get_function_name(pctl->pctldev, func); + function_name = pinmux_generic_get_function_name(pctl->pctldev, func); ret = pinctrl_utils_add_map_mux(pctl->pctldev, map, - &reserved_maps, num_maps, - group_name, function_name); + &reserved_maps, num_maps, + group_name, function_name); if (ret) goto free_map; } @@ -165,7 +163,7 @@ static const struct pinctrl_ops apple_gpio_pinctrl_ops = { /* Pin multiplexer functions */ static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func, - unsigned group) + unsigned group) { struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -186,8 +184,7 @@ static const struct pinmux_ops apple_gpio_pinmux_ops = { /* GPIO chip functions */ -static int apple_gpio_get_direction(struct gpio_chip *chip, - unsigned int offset) +static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); unsigned int reg = apple_gpio_get_reg(pctl, offset); @@ -211,17 +208,14 @@ static int apple_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(reg & REG_GPIOx_DATA); } -static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); - apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, - value ? REG_GPIOx_DATA : 0); + apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0); } -static int apple_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) +static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); @@ -234,7 +228,7 @@ static int apple_gpio_direction_input(struct gpio_chip *chip, } static int apple_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) + unsigned int offset, int value) { struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); @@ -249,13 +243,10 @@ static int apple_gpio_direction_output(struct gpio_chip *chip, static void apple_gpio_irq_ack(struct irq_data *data) { - struct apple_gpio_pinctrl *pctl = - gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned int irqgrp = - FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); + struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); + unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); - writel(BIT(data->hwirq & 31), - pctl->base + REG_IRQ(irqgrp, data->hwirq)); + writel(BIT(data->hwirq & 31), pctl->base + REG_IRQ(irqgrp, data->hwirq)); } static unsigned int apple_gpio_irq_type(unsigned int type) @@ -278,20 +269,19 @@ static unsigned int apple_gpio_irq_type(unsigned int type) static void apple_gpio_irq_mask(struct irq_data *data) { - struct apple_gpio_pinctrl *pctl = - gpiochip_get_data(irq_data_get_irq_chip_data(data)); + struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); + apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); + FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); } static void apple_gpio_irq_unmask(struct irq_data *data) { - struct apple_gpio_pinctrl *pctl = - gpiochip_get_data(irq_data_get_irq_chip_data(data)); + struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data)); apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, irqtype)); + FIELD_PREP(REG_GPIOx_MODE, irqtype)); } static unsigned int apple_gpio_irq_startup(struct irq_data *data) @@ -300,7 +290,7 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data) struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP, - FIELD_PREP(REG_GPIOx_GRP, 0)); + FIELD_PREP(REG_GPIOx_GRP, 0)); apple_gpio_direction_input(chip, data->hwirq); apple_gpio_irq_unmask(data); @@ -308,18 +298,16 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data) return 0; } -static int apple_gpio_irq_set_type(struct irq_data *data, - unsigned int type) +static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type) { - struct apple_gpio_pinctrl *pctl = - gpiochip_get_data(irq_data_get_irq_chip_data(data)); + struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); unsigned int irqtype = apple_gpio_irq_type(type); if (irqtype == REG_GPIOx_IN_IRQ_OFF) return -EINVAL; apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, irqtype)); + FIELD_PREP(REG_GPIOx_MODE, irqtype)); if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(data, handle_level_irq); @@ -402,8 +390,7 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) } for (i = 0; i < girq->num_parents; i++) { - ret = platform_get_irq(to_platform_device(pctl->dev), - i); + ret = platform_get_irq(to_platform_device(pctl->dev), i); if (ret < 0) goto out; From 5ad6973d9ae8c020c2919b408f7a697983547f86 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:33 +0000 Subject: [PATCH 54/98] pinctrl: apple: add missing comma Add a missing comma at the end of the regmap initialisation. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-3-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 7299c7686f7f..60d46ce26115 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -70,7 +70,7 @@ struct regmap_config regmap_config = { .cache_type = REGCACHE_FLAT, .max_register = 512 * sizeof(u32), .num_reg_defaults_raw = 512, - .use_relaxed_mmio = true + .use_relaxed_mmio = true, }; // No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. From 67a6c2811ceff3d8c1225cf52a42f39f3addf477 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:34 +0000 Subject: [PATCH 55/98] pinctrl: apple: use C style comment This is the preferred comment style. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-4-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 60d46ce26115..102940058a11 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -73,7 +73,7 @@ struct regmap_config regmap_config = { .use_relaxed_mmio = true, }; -// No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. +/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */ static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, unsigned int pin, u32 mask, u32 value) { From 7c06f080ddee516499adf75fe934ee06c0f6116c Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:35 +0000 Subject: [PATCH 56/98] pinctrl: apple: add missing bits.h header This is needed for the BIT(n) macro. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-5-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 102940058a11..cce95367c156 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include From 3605f104111e4adeac71edc89d867ec56147786d Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:36 +0000 Subject: [PATCH 57/98] pinctrl: apple: handle regmap_read errors Explicitly return 0 if the regmap_read fails. Also change a uint32_t to a u32. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-6-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index cce95367c156..bd7f28150ac0 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -81,12 +81,16 @@ static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); } -static uint32_t apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, +static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, unsigned int pin) { - unsigned int val = 0; + int ret; + u32 val; + + ret = regmap_read(pctl->map, REG_GPIO(pin), &val); + if (ret) + return 0; - regmap_read(pctl->map, REG_GPIO(pin), &val); return val; } From 7d2649172908c83c820a957e97d0baf9901b9c95 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:37 +0000 Subject: [PATCH 58/98] pinctrl: apple: make apple_gpio_get_direction more readable Try to make this more readable by not using a long line with a ternary operator. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-7-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index bd7f28150ac0..fba2d4ec383c 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -194,8 +194,9 @@ static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); unsigned int reg = apple_gpio_get_reg(pctl, offset); - return (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) ? - GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; + if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) + return GPIO_LINE_DIRECTION_OUT; + return GPIO_LINE_DIRECTION_IN; } static int apple_gpio_get(struct gpio_chip *chip, unsigned offset) From a8888e64eec8f8e50917f9e616f45ff2ad01be66 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:38 +0000 Subject: [PATCH 59/98] pinctrl: apple: give error label a specific name Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-8-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index fba2d4ec383c..fb34cbe189ce 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -392,13 +392,13 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) GFP_KERNEL); if (!girq->parents || !irq_data) { ret = -ENOMEM; - goto out; + goto out_free_irq_data; } for (i = 0; i < girq->num_parents; i++) { ret = platform_get_irq(to_platform_device(pctl->dev), i); if (ret < 0) - goto out; + goto out_free_irq_data; girq->parents[i] = ret; pctl->irqgrps[i] = i; @@ -412,7 +412,8 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) } ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); -out: + +out_free_irq_data: kfree(girq->parents); kfree(irq_data); From 391aad396238037c13074b5e5cd02ae15a2fab91 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:39 +0000 Subject: [PATCH 60/98] pinctrl: apple: remove gpio-controller check Having this missing, but everything else valid shouldn't result in a failure. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-9-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index fb34cbe189ce..471d3abf9d99 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -360,10 +360,6 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) void **irq_data = NULL; int ret; - if (!of_property_read_bool(pctl->dev->of_node, "gpio-controller")) - return dev_err_probe(pctl->dev, -ENODEV, - "No gpio-controller property\n"); - pctl->irq_chip = apple_gpio_irqchip; pctl->gpio_chip.label = dev_name(pctl->dev); From 44bddfad97e7f6290c8d578e79aa608cfb97e65f Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:40 +0000 Subject: [PATCH 61/98] pinctrl: apple: don't set gpio_chip.of_node The gpio core code sets of_node, so no need to do it here. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-10-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 471d3abf9d99..8e794ebb47da 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -373,7 +373,6 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl) pctl->gpio_chip.base = -1; pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins; pctl->gpio_chip.parent = pctl->dev; - pctl->gpio_chip.of_node = pctl->dev->of_node; if (girq->num_parents) { int i; From 077db34c2b007a086baa3ee87bc72794a25d0329 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:41 +0000 Subject: [PATCH 62/98] pinctrl: apple: use modulo rather than bitwise and This expresses the intention clearer. Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-11-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 8e794ebb47da..8a58c862c33a 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -252,7 +252,7 @@ static void apple_gpio_irq_ack(struct irq_data *data) struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data)); unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq)); - writel(BIT(data->hwirq & 31), pctl->base + REG_IRQ(irqgrp, data->hwirq)); + writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq)); } static unsigned int apple_gpio_irq_type(unsigned int type) From 839930ca1bd0c79cdf370d11462ef4a81b664e44 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Sun, 21 Nov 2021 16:56:42 +0000 Subject: [PATCH 63/98] pinctrl: apple: return an error if pinmux is missing in the DT If of_property_count_u32_elems returned 0, return -EINVAL to indicate a failure. Previously this would return 0. Fixes: a0f160ffcb83 ("pinctrl: add pinctrl/GPIO driver for Apple SoCs") Signed-off-by: Joey Gouly Suggested-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211121165642.27883-12-joey.gouly@arm.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 8a58c862c33a..89602aa14c6a 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -119,7 +119,7 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, dev_err(pctl->dev, "missing or empty pinmux property in node %pOFn.\n", node); - return ret; + return ret ? ret : -EINVAL; } num_pins = ret; From 72f902d8b1870dd0c7824f0e7ce2915d564ca802 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 27 Nov 2021 01:06:34 +0100 Subject: [PATCH 64/98] Revert "dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings" This reverts commit 3fe59cc4ff641b106cc24930204d4cd2c82f318f. The bindings were not properly reviewed and were also causing errors in the automatic checkers once applied. Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 195 ------------------ 1 file changed, 195 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml deleted file mode 100644 index 58dd34f4fcb5..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml +++ /dev/null @@ -1,195 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Technologies, Inc. SDX65 TLMM block - -maintainers: - - Vamsi krishna Lanka - -description: - This binding describes the Top Level Mode Multiplexer block found in the - SDX65 platform. - -properties: - compatible: - const: qcom,sdx65-tlmm - - reg: - description: Specifies the base address and size of the TLMM register space - maxItems: 1 - - interrupts: - description: Specifies the TLMM summary IRQ - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - description: Specifies the PIN numbers and Flags, as defined in - include/dt-bindings/interrupt-controller/irq.h - const: 2 - - gpio-controller: true - - '#gpio-cells': - description: Specifying the pin number and flags, as defined in - include/dt-bindings/gpio/gpio.h - const: 2 - - gpio-ranges: - maxItems: 1 - - gpio-reserved-ranges: - maxItems: 1 - -#PIN CONFIGURATION NODES -patternProperties: - '$-state': - oneOf: - - $ref: "#/$defs/qcom-sdx65-tlmm-state" - - patternProperties: - ".*": - $ref: "#/$defs/qcom-sdx65-tlmm-state" -'$defs': - qcom-sdx65-tlmm-state: - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - - properties: - pins: - description: - List of gpio pins affected by the properties specified in this subnode. - items: - oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" - - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ] - minItems: 1 - maxItems: 150 - - function: - description: - Specify the alternative function to be configured for the specified - pins. Functions are only valid for gpio pins. - enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, - bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, - qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, - dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, - blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, - mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, - atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, - cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, - pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, - qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, - qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, - atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, - atest_usb20, atest_char0, dac_calib10, qdss_stm10, - qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, - blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, - qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, - qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, - dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, - qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, - dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, - dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, - dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, - dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, - sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, - qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, - uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, - blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, - qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, - blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, - cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, - blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, - qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, - isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, - qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, - sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, - gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, - qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, - tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, - qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, - sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, - sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, - ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, - blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, - pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, - qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, - qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, - gpio ] - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - required: - - pins - - function - - additionalProperties: false - -required: - - compatible - - reg - - interrupts - - interrupt-controller - - '#interrupt-cells' - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - tlmm: pinctrl@f100000 { - compatible = "qcom,sdx65-tlmm"; - reg = <0x03000000 0xdc2000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 109>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - - serial-pins { - pins = "gpio8", "gpio9"; - function = "blsp_uart3"; - drive-strength = <2>; - bias-disable; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio4"; - function = "blsp_uart1"; - bias-pull-up; - }; - - tx { - pins = "gpio5"; - function = "blsp_uart1"; - bias-disable; - }; - }; - }; -... From bceb6732f3fd2a55d8f2e518cced1c7555e216b6 Mon Sep 17 00:00:00 2001 From: John Keeping Date: Fri, 26 Nov 2021 15:13:52 +0000 Subject: [PATCH 65/98] pinctrl/rockchip: fix gpio device creation GPIO nodes are not themselves busses, so passing rockchip_bank_match here is wrong. Passing NULL instead uses the standard bus match table which is more appropriate. devm_of_platform_populate() shows that this is the normal way to call of_platform_populate() from a device driver, so in order to match that more closely also add the pinctrl device as the parent for the newly created GPIO controllers. Specifically, using the wrong match here can break dynamic GPIO hogs as marking the GPIO bank as a bus means that of_platform_notify() will set OF_POPULATED on new child nodes and if this happens before of_gpio_notify() is called then the new hog will be skipped as OF_POPULATED is already set. Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") Signed-off-by: John Keeping Link: https://lore.kernel.org/r/20211126151352.1509583-1-john@metanate.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 438808a867cf..d8dd8415fa81 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2735,7 +2735,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, info); - ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL); + ret = of_platform_populate(np, NULL, NULL, &pdev->dev); if (ret) return dev_err_probe(dev, ret, "failed to register gpio device\n"); From 96028326dfb9a660f65526c514b7bffc34c1adb3 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Thu, 25 Nov 2021 16:14:32 -0500 Subject: [PATCH 66/98] dt-bindings: pinctrl: add i.MXRT1050 pinctrl binding doc Add i.MXRT1050 pinctrl binding doc Cc: Giulio Benetti Signed-off-by: Jesse Taube Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211125211443.1150135-3-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imxrt1050.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml new file mode 100644 index 000000000000..1278f7293560 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMXRT1050 IOMUX Controller + +maintainers: + - Giulio Benetti + - Jesse Taube + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imxrt1050-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MXRT1050 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = + <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, + <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>; + }; + }; From debc8b0b469d1b0a0745df2c0992eb268f7994fa Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 25 Nov 2021 16:14:34 -0500 Subject: [PATCH 67/98] pinctrl: freescale: Add i.MXRT1050 pinctrl driver support Add the pinctrl driver support for i.MXRT1050. Signed-off-by: Giulio Benetti Signed-off-by: Jesse Taube Reviewed-by: Fabio Estevam Link: https://lore.kernel.org/r/20211125211443.1150135-5-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 349 ++++++++++++++++++ 3 files changed, 357 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imxrt1050.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 21fa21c6547b..8bdafaf40b29 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -173,6 +173,13 @@ config PINCTRL_IMX8ULP help Say Y here to enable the imx8ulp pinctrl driver +config PINCTRL_IMXRT1050 + bool "IMXRT1050 pinctrl driver" + depends on ARCH_MXC + select PINCTRL_IMX + help + Say Y here to enable the imxrt1050 pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index c44930b1b362..565a0350bf09 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o +obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c new file mode 100644 index 000000000000..11f31c90ad30 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imxrt1050_pads { + IMXRT1050_PAD_RESERVE0 = 0, + IMXRT1050_PAD_RESERVE1 = 1, + IMXRT1050_PAD_RESERVE2 = 2, + IMXRT1050_PAD_RESERVE3 = 3, + IMXRT1050_PAD_RESERVE4 = 4, + IMXRT1050_PAD_RESERVE5 = 5, + IMXRT1050_PAD_RESERVE6 = 6, + IMXRT1050_PAD_RESERVE7 = 7, + IMXRT1050_PAD_RESERVE8 = 8, + IMXRT1050_PAD_RESERVE9 = 9, + IMXRT1050_IOMUXC_GPIO1_IO00 = 10, + IMXRT1050_IOMUXC_GPIO1_IO01 = 11, + IMXRT1050_IOMUXC_GPIO1_IO02 = 12, + IMXRT1050_IOMUXC_GPIO1_IO03 = 13, + IMXRT1050_IOMUXC_GPIO1_IO04 = 14, + IMXRT1050_IOMUXC_GPIO1_IO05 = 15, + IMXRT1050_IOMUXC_GPIO1_IO06 = 16, + IMXRT1050_IOMUXC_GPIO1_IO07 = 17, + IMXRT1050_IOMUXC_GPIO1_IO08 = 18, + IMXRT1050_IOMUXC_GPIO1_IO09 = 19, + IMXRT1050_IOMUXC_GPIO1_IO10 = 20, + IMXRT1050_IOMUXC_GPIO1_IO11 = 21, + IMXRT1050_IOMUXC_GPIO1_IO12 = 22, + IMXRT1050_IOMUXC_GPIO1_IO13 = 23, + IMXRT1050_IOMUXC_GPIO1_IO14 = 24, + IMXRT1050_IOMUXC_GPIO1_IO15 = 25, + IMXRT1050_IOMUXC_ENET_MDC = 26, + IMXRT1050_IOMUXC_ENET_MDIO = 27, + IMXRT1050_IOMUXC_ENET_TD3 = 28, + IMXRT1050_IOMUXC_ENET_TD2 = 29, + IMXRT1050_IOMUXC_ENET_TD1 = 30, + IMXRT1050_IOMUXC_ENET_TD0 = 31, + IMXRT1050_IOMUXC_ENET_TX_CTL = 32, + IMXRT1050_IOMUXC_ENET_TXC = 33, + IMXRT1050_IOMUXC_ENET_RX_CTL = 34, + IMXRT1050_IOMUXC_ENET_RXC = 35, + IMXRT1050_IOMUXC_ENET_RD0 = 36, + IMXRT1050_IOMUXC_ENET_RD1 = 37, + IMXRT1050_IOMUXC_ENET_RD2 = 38, + IMXRT1050_IOMUXC_ENET_RD3 = 39, + IMXRT1050_IOMUXC_SD1_CLK = 40, + IMXRT1050_IOMUXC_SD1_CMD = 41, + IMXRT1050_IOMUXC_SD1_DATA0 = 42, + IMXRT1050_IOMUXC_SD1_DATA1 = 43, + IMXRT1050_IOMUXC_SD1_DATA2 = 44, + IMXRT1050_IOMUXC_SD1_DATA3 = 45, + IMXRT1050_IOMUXC_SD1_DATA4 = 46, + IMXRT1050_IOMUXC_SD1_DATA5 = 47, + IMXRT1050_IOMUXC_SD1_DATA6 = 48, + IMXRT1050_IOMUXC_SD1_DATA7 = 49, + IMXRT1050_IOMUXC_SD1_RESET_B = 50, + IMXRT1050_IOMUXC_SD1_STROBE = 51, + IMXRT1050_IOMUXC_SD2_CD_B = 52, + IMXRT1050_IOMUXC_SD2_CLK = 53, + IMXRT1050_IOMUXC_SD2_CMD = 54, + IMXRT1050_IOMUXC_SD2_DATA0 = 55, + IMXRT1050_IOMUXC_SD2_DATA1 = 56, + IMXRT1050_IOMUXC_SD2_DATA2 = 57, + IMXRT1050_IOMUXC_SD2_DATA3 = 58, + IMXRT1050_IOMUXC_SD2_RESET_B = 59, + IMXRT1050_IOMUXC_SD2_WP = 60, + IMXRT1050_IOMUXC_NAND_ALE = 61, + IMXRT1050_IOMUXC_NAND_CE0 = 62, + IMXRT1050_IOMUXC_NAND_CE1 = 63, + IMXRT1050_IOMUXC_NAND_CE2 = 64, + IMXRT1050_IOMUXC_NAND_CE3 = 65, + IMXRT1050_IOMUXC_NAND_CLE = 66, + IMXRT1050_IOMUXC_NAND_DATA00 = 67, + IMXRT1050_IOMUXC_NAND_DATA01 = 68, + IMXRT1050_IOMUXC_NAND_DATA02 = 69, + IMXRT1050_IOMUXC_NAND_DATA03 = 70, + IMXRT1050_IOMUXC_NAND_DATA04 = 71, + IMXRT1050_IOMUXC_NAND_DATA05 = 72, + IMXRT1050_IOMUXC_NAND_DATA06 = 73, + IMXRT1050_IOMUXC_NAND_DATA07 = 74, + IMXRT1050_IOMUXC_NAND_DQS = 75, + IMXRT1050_IOMUXC_NAND_RE_B = 76, + IMXRT1050_IOMUXC_NAND_READY_B = 77, + IMXRT1050_IOMUXC_NAND_WE_B = 78, + IMXRT1050_IOMUXC_NAND_WP_B = 79, + IMXRT1050_IOMUXC_SAI5_RXFS = 80, + IMXRT1050_IOMUXC_SAI5_RXC = 81, + IMXRT1050_IOMUXC_SAI5_RXD0 = 82, + IMXRT1050_IOMUXC_SAI5_RXD1 = 83, + IMXRT1050_IOMUXC_SAI5_RXD2 = 84, + IMXRT1050_IOMUXC_SAI5_RXD3 = 85, + IMXRT1050_IOMUXC_SAI5_MCLK = 86, + IMXRT1050_IOMUXC_SAI1_RXFS = 87, + IMXRT1050_IOMUXC_SAI1_RXC = 88, + IMXRT1050_IOMUXC_SAI1_RXD0 = 89, + IMXRT1050_IOMUXC_SAI1_RXD1 = 90, + IMXRT1050_IOMUXC_SAI1_RXD2 = 91, + IMXRT1050_IOMUXC_SAI1_RXD3 = 92, + IMXRT1050_IOMUXC_SAI1_RXD4 = 93, + IMXRT1050_IOMUXC_SAI1_RXD5 = 94, + IMXRT1050_IOMUXC_SAI1_RXD6 = 95, + IMXRT1050_IOMUXC_SAI1_RXD7 = 96, + IMXRT1050_IOMUXC_SAI1_TXFS = 97, + IMXRT1050_IOMUXC_SAI1_TXC = 98, + IMXRT1050_IOMUXC_SAI1_TXD0 = 99, + IMXRT1050_IOMUXC_SAI1_TXD1 = 100, + IMXRT1050_IOMUXC_SAI1_TXD2 = 101, + IMXRT1050_IOMUXC_SAI1_TXD3 = 102, + IMXRT1050_IOMUXC_SAI1_TXD4 = 103, + IMXRT1050_IOMUXC_SAI1_TXD5 = 104, + IMXRT1050_IOMUXC_SAI1_TXD6 = 105, + IMXRT1050_IOMUXC_SAI1_TXD7 = 106, + IMXRT1050_IOMUXC_SAI1_MCLK = 107, + IMXRT1050_IOMUXC_SAI2_RXFS = 108, + IMXRT1050_IOMUXC_SAI2_RXC = 109, + IMXRT1050_IOMUXC_SAI2_RXD0 = 110, + IMXRT1050_IOMUXC_SAI2_TXFS = 111, + IMXRT1050_IOMUXC_SAI2_TXC = 112, + IMXRT1050_IOMUXC_SAI2_TXD0 = 113, + IMXRT1050_IOMUXC_SAI2_MCLK = 114, + IMXRT1050_IOMUXC_SAI3_RXFS = 115, + IMXRT1050_IOMUXC_SAI3_RXC = 116, + IMXRT1050_IOMUXC_SAI3_RXD = 117, + IMXRT1050_IOMUXC_SAI3_TXFS = 118, + IMXRT1050_IOMUXC_SAI3_TXC = 119, + IMXRT1050_IOMUXC_SAI3_TXD = 120, + IMXRT1050_IOMUXC_SAI3_MCLK = 121, + IMXRT1050_IOMUXC_SPDIF_TX = 122, + IMXRT1050_IOMUXC_SPDIF_RX = 123, + IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124, + IMXRT1050_IOMUXC_ECSPI1_SCLK = 125, + IMXRT1050_IOMUXC_ECSPI1_MOSI = 126, + IMXRT1050_IOMUXC_ECSPI1_MISO = 127, + IMXRT1050_IOMUXC_ECSPI1_SS0 = 128, + IMXRT1050_IOMUXC_ECSPI2_SCLK = 129, + IMXRT1050_IOMUXC_ECSPI2_MOSI = 130, + IMXRT1050_IOMUXC_ECSPI2_MISO = 131, + IMXRT1050_IOMUXC_ECSPI2_SS0 = 132, + IMXRT1050_IOMUXC_I2C1_SCL = 133, + IMXRT1050_IOMUXC_I2C1_SDA = 134, + IMXRT1050_IOMUXC_I2C2_SCL = 135, + IMXRT1050_IOMUXC_I2C2_SDA = 136, + IMXRT1050_IOMUXC_I2C3_SCL = 137, + IMXRT1050_IOMUXC_I2C3_SDA = 138, + IMXRT1050_IOMUXC_I2C4_SCL = 139, + IMXRT1050_IOMUXC_I2C4_SDA = 140, + IMXRT1050_IOMUXC_UART1_RXD = 141, + IMXRT1050_IOMUXC_UART1_TXD = 142, + IMXRT1050_IOMUXC_UART2_RXD = 143, + IMXRT1050_IOMUXC_UART2_TXD = 144, + IMXRT1050_IOMUXC_UART3_RXD = 145, + IMXRT1050_IOMUXC_UART3_TXD = 146, + IMXRT1050_IOMUXC_UART4_RXD = 147, + IMXRT1050_IOMUXC_UART4_TXD = 148, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8), + IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD), + IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD), +}; + +static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = { + .pins = imxrt1050_pinctrl_pads, + .npins = ARRAY_SIZE(imxrt1050_pinctrl_pads), + .gpr_compatible = "fsl,imxrt1050-iomuxc-gpr", +}; + +static const struct of_device_id imxrt1050_pinctrl_of_match[] = { + { .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imxrt1050_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info); +} + +static struct platform_driver imxrt1050_pinctrl_driver = { + .driver = { + .name = "imxrt1050-pinctrl", + .of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imxrt1050_pinctrl_probe, +}; + +static int __init imxrt1050_pinctrl_init(void) +{ + return platform_driver_register(&imxrt1050_pinctrl_driver); +} +arch_initcall(imxrt1050_pinctrl_init); From 67bbbcb49b968a93251de7b23616d5aff5d3a726 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 27 Nov 2021 17:07:50 +0300 Subject: [PATCH 68/98] pinctrl: mediatek: uninitialized variable in mtk_pctrl_show_one_pin() The "try_all_type" variable is not set if (hw->soc->pull_type) is false leading to the following Smatch warning: drivers/pinctrl/mediatek/pinctrl-paris.c:599 mtk_pctrl_show_one_pin() error: uninitialized symbol 'try_all_type'. Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20211127140750.GA24002@kili Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index d4e02c5d74a8..4c6f6d967b18 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -581,7 +581,7 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, { int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1; const struct mtk_pin_desc *desc; - u32 try_all_type; + u32 try_all_type = 0; if (gpio >= hw->soc->npins) return -EINVAL; From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 27 Nov 2021 17:08:36 +0300 Subject: [PATCH 69/98] pinctrl: mediatek: add a check for error in mtk_pinconf_bias_get_rsel() All the other mtk_hw_get_value() calls have a check for "if (err)" so we can add one here as well. This silences a Smatch warning: drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel() error: uninitialized symbol 'pd'. Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20211127140836.GB24002@kili Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 91553b2fc160..bd5d7d63e877 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -811,6 +811,8 @@ static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw, goto out; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); + if (err) + goto out; if (pu == 0 && pd == 0) { *pullup = 0; From f3e3e63796cc599024b03fe67d788630a5923ae5 Mon Sep 17 00:00:00 2001 From: kernel test robot Date: Sat, 27 Nov 2021 19:01:04 +0100 Subject: [PATCH 70/98] pinctrl: apple-gpio: fix flexible_array.cocci warnings Zero-length and one-element arrays are deprecated, see Documentation/process/deprecated.rst Flexible-array members should be used instead. Generated by: scripts/coccinelle/misc/flexible_array.cocci CC: Joey Gouly Reported-by: kernel test robot Signed-off-by: kernel test robot Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2111271859250.2864@hadrien Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-apple-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 89602aa14c6a..72f4dd2466e1 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -37,7 +37,7 @@ struct apple_gpio_pinctrl { struct pinctrl_desc pinctrl_desc; struct gpio_chip gpio_chip; struct irq_chip irq_chip; - u8 irqgrps[0]; + u8 irqgrps[]; }; #define REG_GPIO(x) (4 * (x)) From 896568e5b9c8a170912ff83760dca51703e276f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 10 Nov 2021 17:57:19 +0100 Subject: [PATCH 71/98] dt-bindings: pinctrl: convert controller description to the json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This helps validating DTS and writing YAML files. Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211110165720.30242-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-bindings.txt | 41 +---------------- .../devicetree/bindings/pinctrl/pinctrl.yaml | 45 +++++++++++++++++++ 2 files changed, 46 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 9dae60acf950..6904072d3944 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -97,47 +97,8 @@ For example: }; == Pin controller devices == -Required properties: See the pin controller driver specific documentation -Optional properties: -#pinctrl-cells: Number of pin control cells in addition to the index within the - pin controller device instance - -pinctrl-use-default: Boolean. Indicates that the OS can use the boot default - pin configuration. This allows using an OS that does not have a - driver for the pin controller. This property can be set either - globally for the pin controller or in child nodes for individual - pin group control. - -Pin controller devices should contain the pin configuration nodes that client -devices reference. - -For example: - - pincontroller { - ... /* Standard DT properties for the device itself elided */ - - state_0_node_a { - ... - }; - state_1_node_a { - ... - }; - state_1_node_b { - ... - }; - } - -The contents of each of those pin configuration child nodes is defined -entirely by the binding for the individual pin controller device. There -exists no common standard for this content. The pinctrl framework only -provides generic helper bindings that the pin controller driver can use. - -The pin configuration nodes need not be direct children of the pin controller -device; they may be grandchildren, for example. Whether this is legal, and -whether there is any interaction between the child and intermediate parent -nodes, is again defined entirely by the binding for the individual pin -controller device. +See pinctrl.yaml == Generic pin multiplexing node content == diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml new file mode 100644 index 000000000000..d471563119a9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin controller device + +maintainers: + - Linus Walleij + - Rafał Miłecki + +description: | + Pin controller devices should contain the pin configuration nodes that client + devices reference. + + The contents of each of those pin configuration child nodes is defined + entirely by the binding for the individual pin controller device. There + exists no common standard for this content. The pinctrl framework only + provides generic helper bindings that the pin controller driver can use. + + The pin configuration nodes need not be direct children of the pin controller + device; they may be grandchildren, for example. Whether this is legal, and + whether there is any interaction between the child and intermediate parent + nodes, is again defined entirely by the binding for the individual pin + controller device. + +properties: + $nodename: + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" + + "#pinctrl-cells": + description: > + Number of pin control cells in addition to the index within the pin + controller device instance. + + pinctrl-use-default: + type: boolean + description: > + Indicates that the OS can use the boot default pin configuration. This + allows using an OS that does not have a driver for the pin controller. + This property can be set either globally for the pin controller or in + child nodes for individual pin group control. + +additionalProperties: true From d11db044a394e2f842bd6f31b904feb298a4699f Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:50 +0100 Subject: [PATCH 72/98] pinctrl: spear: spear: Convert to regmap Resources need to be shared between pinmux and plgpio. Use regmap (syscon) to access resources to allow an easy way to share resources. Signed-off-by: Herve Codina Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20211202095255.165797-2-herve.codina@bootlin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear.c | 10 +++++++--- drivers/pinctrl/spear/pinctrl-spear.h | 12 ++++++++---- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index 948f56abb9ae..e0543c1ad641 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -367,9 +368,12 @@ int spear_pinctrl_probe(struct platform_device *pdev, if (!pmx) return -ENOMEM; - pmx->vbase = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(pmx->vbase)) - return PTR_ERR(pmx->vbase); + pmx->regmap = device_node_to_regmap(np); + if (IS_ERR(pmx->regmap)) { + dev_err(&pdev->dev, "Init regmap failed (%pe).\n", + pmx->regmap); + return PTR_ERR(pmx->regmap); + } pmx->dev = &pdev->dev; pmx->machdata = machdata; diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h index db029b148c87..63a0b5ea56ef 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.h +++ b/drivers/pinctrl/spear/pinctrl-spear.h @@ -15,6 +15,7 @@ #include #include #include +#include #include struct platform_device; @@ -172,24 +173,27 @@ struct spear_pinctrl_machdata { * @dev: pointer to struct dev of platform_device registered * @pctl: pointer to struct pinctrl_dev * @machdata: pointer to SoC or machine specific structure - * @vbase: virtual base address of pinmux controller + * @regmap: regmap of pinmux controller */ struct spear_pmx { struct device *dev; struct pinctrl_dev *pctl; struct spear_pinctrl_machdata *machdata; - void __iomem *vbase; + struct regmap *regmap; }; /* exported routines */ static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) { - return readl_relaxed(pmx->vbase + reg); + u32 val; + + regmap_read(pmx->regmap, reg, &val); + return val; } static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) { - writel_relaxed(val, pmx->vbase + reg); + regmap_write(pmx->regmap, reg, val); } void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); From 7151cef59e83695adc79bd7c539f371dc674824b Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:51 +0100 Subject: [PATCH 73/98] pinctrl: spear: plgpio: Convert to regmap Resources need to be shared between pinmux and plgpio. Use regmap (syscon) to access resources to allow an easy way to share resources. Signed-off-by: Herve Codina Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20211202095255.165797-3-herve.codina@bootlin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-plgpio.c | 136 ++++++++++++++----------- 1 file changed, 76 insertions(+), 60 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 43bb334af1e1..28538ac99eed 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -14,11 +14,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #define MAX_GPIO_PER_REG 32 @@ -64,7 +66,7 @@ struct plgpio_regs { */ struct plgpio { spinlock_t lock; - void __iomem *base; + struct regmap *regmap; struct clk *clk; struct gpio_chip chip; int (*p2o)(int pin); /* pin_to_offset */ @@ -77,33 +79,38 @@ struct plgpio { }; /* register manipulation inline functions */ -static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) +static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg) { u32 offset = PIN_OFFSET(pin); - void __iomem *reg_off = REG_OFFSET(base, reg, pin); - u32 val = readl_relaxed(reg_off); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 val; + + regmap_read(regmap, reg_off, &val); return !!(val & (1 << offset)); } -static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) +static inline void plgpio_reg_set(struct regmap *regmap, u32 pin, u32 reg) { u32 offset = PIN_OFFSET(pin); - void __iomem *reg_off = REG_OFFSET(base, reg, pin); - u32 val = readl_relaxed(reg_off); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 mask; - writel_relaxed(val | (1 << offset), reg_off); + mask = 1 << offset; + regmap_update_bits(regmap, reg_off, mask, mask); } -static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) +static inline void plgpio_reg_reset(struct regmap *regmap, u32 pin, u32 reg) { u32 offset = PIN_OFFSET(pin); - void __iomem *reg_off = REG_OFFSET(base, reg, pin); - u32 val = readl_relaxed(reg_off); + u32 reg_off = REG_OFFSET(0, reg, pin); + u32 mask; - writel_relaxed(val & ~(1 << offset), reg_off); + mask = 1 << offset; + regmap_update_bits(regmap, reg_off, mask, 0); } + /* gpio framework specific routines */ static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) { @@ -118,7 +125,7 @@ static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) } spin_lock_irqsave(&plgpio->lock, flags); - plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.dir); spin_unlock_irqrestore(&plgpio->lock, flags); return 0; @@ -145,13 +152,13 @@ static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset, spin_lock_irqsave(&plgpio->lock, flags); if (value) - plgpio_reg_set(plgpio->base, wdata_offset, + plgpio_reg_set(plgpio->regmap, wdata_offset, plgpio->regs.wdata); else - plgpio_reg_reset(plgpio->base, wdata_offset, + plgpio_reg_reset(plgpio->regmap, wdata_offset, plgpio->regs.wdata); - plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir); + plgpio_reg_reset(plgpio->regmap, dir_offset, plgpio->regs.dir); spin_unlock_irqrestore(&plgpio->lock, flags); return 0; @@ -171,7 +178,7 @@ static int plgpio_get_value(struct gpio_chip *chip, unsigned offset) return -EINVAL; } - return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata); + return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata); } static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) @@ -189,9 +196,9 @@ static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) } if (value) - plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata); else - plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata); + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata); } static int plgpio_request(struct gpio_chip *chip, unsigned offset) @@ -234,7 +241,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset) } spin_lock_irqsave(&plgpio->lock, flags); - plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.enb); spin_unlock_irqrestore(&plgpio->lock, flags); return 0; @@ -266,7 +273,7 @@ static void plgpio_free(struct gpio_chip *chip, unsigned offset) } spin_lock_irqsave(&plgpio->lock, flags); - plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb); + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.enb); spin_unlock_irqrestore(&plgpio->lock, flags); disable_clk: @@ -292,7 +299,7 @@ static void plgpio_irq_disable(struct irq_data *d) } spin_lock_irqsave(&plgpio->lock, flags); - plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie); + plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie); spin_unlock_irqrestore(&plgpio->lock, flags); } @@ -311,7 +318,7 @@ static void plgpio_irq_enable(struct irq_data *d) } spin_lock_irqsave(&plgpio->lock, flags); - plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie); + plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie); spin_unlock_irqrestore(&plgpio->lock, flags); } @@ -320,7 +327,7 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct plgpio *plgpio = gpiochip_get_data(gc); int offset = d->hwirq; - void __iomem *reg_off; + u32 reg_off; unsigned int supported_type = 0, val; if (offset >= plgpio->chip.ngpio) @@ -337,14 +344,14 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) if (plgpio->regs.eit == -1) return 0; - reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); - val = readl_relaxed(reg_off); + reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); + regmap_read(plgpio->regmap, reg_off, &val); offset = PIN_OFFSET(offset); if (trigger & IRQ_TYPE_EDGE_RISING) - writel_relaxed(val | (1 << offset), reg_off); + regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); else - writel_relaxed(val & ~(1 << offset), reg_off); + regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset)); return 0; } @@ -362,7 +369,8 @@ static void plgpio_irq_handler(struct irq_desc *desc) struct plgpio *plgpio = gpiochip_get_data(gc); struct irq_chip *irqchip = irq_desc_get_chip(desc); int regs_count, count, pin, offset, i = 0; - unsigned long pending; + u32 pending; + unsigned long pendingl; count = plgpio->chip.ngpio; regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG); @@ -370,14 +378,14 @@ static void plgpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irqchip, desc); /* check all plgpio MIS registers for a possible interrupt */ for (; i < regs_count; i++) { - pending = readl_relaxed(plgpio->base + plgpio->regs.mis + - i * sizeof(int *)); + regmap_read(plgpio->regmap, plgpio->regs.mis + + i * sizeof(int *), &pending); if (!pending) continue; /* clear interrupts */ - writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + - i * sizeof(int *)); + regmap_write(plgpio->regmap, plgpio->regs.mis + + i * sizeof(int *), ~pending); /* * clear extra bits in last register having gpios < MAX/REG * ex: Suppose there are max 102 plgpios. then last register @@ -389,7 +397,8 @@ static void plgpio_irq_handler(struct irq_desc *desc) if (count < MAX_GPIO_PER_REG) pending &= (1 << count) - 1; - for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) { + pendingl = pending; + for_each_set_bit(offset, &pendingl, MAX_GPIO_PER_REG) { /* get correct pin for "offset" */ if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) { pin = plgpio->o2p(offset); @@ -511,6 +520,7 @@ static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio) end: return ret; } + static int plgpio_probe(struct platform_device *pdev) { struct plgpio *plgpio; @@ -520,9 +530,12 @@ static int plgpio_probe(struct platform_device *pdev) if (!plgpio) return -ENOMEM; - plgpio->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(plgpio->base)) - return PTR_ERR(plgpio->base); + plgpio->regmap = device_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(plgpio->regmap)) { + dev_err(&pdev->dev, "Init regmap failed (%pe)\n", + plgpio->regmap); + return PTR_ERR(plgpio->regmap); + } ret = plgpio_probe_dt(pdev, plgpio); if (ret) { @@ -607,22 +620,23 @@ static int plgpio_suspend(struct device *dev) { struct plgpio *plgpio = dev_get_drvdata(dev); int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); - void __iomem *off; + u32 off; for (i = 0; i < reg_count; i++) { - off = plgpio->base + i * sizeof(int *); + off = i * sizeof(int *); if (plgpio->regs.enb != -1) - plgpio->csave_regs[i].enb = - readl_relaxed(plgpio->regs.enb + off); + regmap_read(plgpio->regmap, plgpio->regs.enb + off, + &plgpio->csave_regs[i].enb); if (plgpio->regs.eit != -1) - plgpio->csave_regs[i].eit = - readl_relaxed(plgpio->regs.eit + off); - plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata + - off); - plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir + - off); - plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off); + regmap_read(plgpio->regmap, plgpio->regs.eit + off, + &plgpio->csave_regs[i].eit); + regmap_read(plgpio->regmap, plgpio->regs.wdata + off, + &plgpio->csave_regs[i].wdata); + regmap_read(plgpio->regmap, plgpio->regs.dir + off, + &plgpio->csave_regs[i].dir); + regmap_read(plgpio->regmap, plgpio->regs.ie + off, + &plgpio->csave_regs[i].ie); } return 0; @@ -636,7 +650,7 @@ static int plgpio_suspend(struct device *dev) */ #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ { \ - _tmp = readl_relaxed(plgpio->regs.__reg + _off); \ + regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \ _tmp &= ~_mask; \ plgpio->csave_regs[i].__reg = \ _tmp | (plgpio->csave_regs[i].__reg & _mask); \ @@ -646,11 +660,11 @@ static int plgpio_resume(struct device *dev) { struct plgpio *plgpio = dev_get_drvdata(dev); int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); - void __iomem *off; + u32 off; u32 mask, tmp; for (i = 0; i < reg_count; i++) { - off = plgpio->base + i * sizeof(int *); + off = i * sizeof(int *); if (i == reg_count - 1) { mask = (1 << (plgpio->chip.ngpio - i * @@ -667,20 +681,22 @@ static int plgpio_resume(struct device *dev) plgpio_prepare_reg(ie, off, mask, tmp); } - writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata + - off); - writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir + - off); + regmap_write(plgpio->regmap, plgpio->regs.wdata + off, + plgpio->csave_regs[i].wdata); + + regmap_write(plgpio->regmap, plgpio->regs.dir + off, + plgpio->csave_regs[i].dir); if (plgpio->regs.eit != -1) - writel_relaxed(plgpio->csave_regs[i].eit, - plgpio->regs.eit + off); + regmap_write(plgpio->regmap, plgpio->regs.eit + off, + plgpio->csave_regs[i].eit); - writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off); + regmap_write(plgpio->regmap, plgpio->regs.ie + off, + plgpio->csave_regs[i].ie); if (plgpio->regs.enb != -1) - writel_relaxed(plgpio->csave_regs[i].enb, - plgpio->regs.enb + off); + regmap_write(plgpio->regmap, plgpio->regs.enb + off, + plgpio->csave_regs[i].enb); } return 0; From 1288cadce4c7c2afafd13aeed64305b7fb4e280d Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Thu, 2 Dec 2021 10:52:52 +0100 Subject: [PATCH 74/98] pinctrl: spear: plgpio: Introduce regmap phandle Resources need to be shared between pinmux and plgpio. Introduce regmap phandle in order to retrieve the regmap from the phandle if the property is present. This allows to retrieve an external regmap (ie the one used by pinmux if the phandle references the pinmux node) from plgpio. Signed-off-by: Herve Codina Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20211202095255.165797-4-herve.codina@bootlin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-plgpio.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 28538ac99eed..b36449724f3f 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -523,6 +523,7 @@ end: static int plgpio_probe(struct platform_device *pdev) { + struct device_node *regmap_np; struct plgpio *plgpio; int ret, irq; @@ -530,11 +531,22 @@ static int plgpio_probe(struct platform_device *pdev) if (!plgpio) return -ENOMEM; - plgpio->regmap = device_node_to_regmap(pdev->dev.of_node); - if (IS_ERR(plgpio->regmap)) { - dev_err(&pdev->dev, "Init regmap failed (%pe)\n", - plgpio->regmap); - return PTR_ERR(plgpio->regmap); + regmap_np = of_parse_phandle(pdev->dev.of_node, "regmap", 0); + if (regmap_np) { + plgpio->regmap = device_node_to_regmap(regmap_np); + of_node_put(regmap_np); + if (IS_ERR(plgpio->regmap)) { + dev_err(&pdev->dev, "Retrieve regmap failed (%pe)\n", + plgpio->regmap); + return PTR_ERR(plgpio->regmap); + } + } else { + plgpio->regmap = device_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(plgpio->regmap)) { + dev_err(&pdev->dev, "Init regmap failed (%pe)\n", + plgpio->regmap); + return PTR_ERR(plgpio->regmap); + } } ret = plgpio_probe_dt(pdev, plgpio); From c09acbc499e883a31e44d7ead3441c495b17df33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 2 Dec 2021 07:32:16 +0100 Subject: [PATCH 75/98] dt-bindings: pinctrl: use pinctrl.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also fix some examples to avoid warnings like: brcm,ns-pinmux.example.dt.yaml: pin-controller@1800c1c0: $nodename:0: 'pin-controller@1800c1c0' does not match '^pinctrl|pinmux@[0-9a-f]+$' Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211202063216.24439-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml | 3 +++ .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/apple,pinctrl.yaml | 3 +++ .../bindings/pinctrl/aspeed,ast2400-pinctrl.yaml | 3 +++ .../bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 3 +++ .../bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml | 3 +++ .../bindings/pinctrl/brcm,bcm63268-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml | 3 ++- .../devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/cirrus,lochnagar.yaml | 3 +++ .../devicetree/bindings/pinctrl/cirrus,madera.yaml | 3 +++ .../devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/ingenic,pinctrl.yaml | 8 ++++---- .../devicetree/bindings/pinctrl/intel,lgm-io.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt6797-pinctrl.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 3 +++ .../bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/pinctrl-mt8192.yaml | 3 +++ .../devicetree/bindings/pinctrl/pinctrl-mt8195.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 3 +++ .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml | 1 + .../devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 3 +++ .../devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml | 3 +++ .../devicetree/bindings/pinctrl/renesas,pfc.yaml | 3 +++ .../devicetree/bindings/pinctrl/renesas,rza1-ports.yaml | 3 +++ .../devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml | 3 +++ .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 3 +++ .../bindings/pinctrl/socionext,uniphier-pinctrl.yaml | 6 +++--- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 3 +++ .../bindings/pinctrl/toshiba,visconti-pinctrl.yaml | 5 ++++- .../devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 3 +++ .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 3 +++ 58 files changed, 165 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml index 3f94f6944740..fb0f69ce9c16 100644 --- a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml @@ -184,6 +184,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index cce63c3cc463..bfce850c2035 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -147,6 +147,7 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - $ref: "pinctrl.yaml#" - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 07b00de79755..61fc05840eb3 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -67,6 +67,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index 100bb6dea3ec..c689bea7ce6e 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -50,6 +50,9 @@ patternProperties: TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 904697bc9415..d316cc082107 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -62,6 +62,9 @@ patternProperties: USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS, VGAVS, VPI24, VPO, WDTRST1, WDTRST2] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - aspeed,external-nodes diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index ad2866c99738..57b68d6c7c70 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -83,6 +83,9 @@ patternProperties: UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml index 08995a4f854b..ab019a1998e8 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml @@ -37,6 +37,9 @@ patternProperties: enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml index 58ffed44b3c4..8c9d4668c8c4 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml @@ -41,6 +41,9 @@ patternProperties: vdsl_phy_override_1_grp, vdsl_phy_override_2_grp, vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml index 0fd24f40afb1..a8e22ec02215 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml @@ -36,6 +36,9 @@ patternProperties: gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1, usb_port1 ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml index 0c3ce256aa78..35867355a47a 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml @@ -34,6 +34,9 @@ patternProperties: enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp, led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml index 6f68fee373bd..b584d4b27223 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml @@ -41,6 +41,9 @@ patternProperties: gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml index f4168b9f4460..229323d9237d 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml @@ -42,6 +42,9 @@ patternProperties: gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, uart1_grp ] +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml index fc39e3e9f71c..8d1e5b1cdd5f 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml @@ -53,6 +53,7 @@ patternProperties: additionalProperties: false allOf: + - $ref: "pinctrl.yaml#" - if: properties: compatible: @@ -77,7 +78,7 @@ additionalProperties: false examples: - | - pin-controller@1800c1c0 { + pinctrl@1800c1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1800c1c0 0x24>; reg-names = "cru_gpio_control"; diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml index 46fbc73ab26b..a44691d9c57d 100644 --- a/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml @@ -137,6 +137,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg @@ -151,9 +154,9 @@ examples: #include #include - fpioa: pinmux@502B0000 { + fpioa: pinmux@502b0000 { compatible = "canaan,k210-fpioa"; - reg = <0x502B0000 0x100>; + reg = <0x502b0000 0x100>; clocks = <&sysclk K210_CLK_FPIOA>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml index a07dd197176a..80020539c3bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml @@ -181,6 +181,9 @@ properties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - gpio-controller diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml index 4cb174bf31ff..e50d7ad5c229 100644 --- a/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml @@ -117,6 +117,9 @@ properties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - pinctrl-0 - pinctrl-names diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml index 6d7d162e6171..6717f163390b 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml @@ -58,6 +58,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml index 7131cfd1fc45..b1cdbb56d4e4 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml @@ -58,6 +58,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml index d474bc1f393b..4eed3a4e153a 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -58,6 +58,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml index 0af2b6c95c17..d4a8ea5551a5 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml @@ -58,6 +58,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml index 86622c4f374b..693398d88223 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml @@ -56,6 +56,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml index a12d0ceb7637..c2c370448b81 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml @@ -28,9 +28,6 @@ maintainers: - Paul Cercueil properties: - nodename: - pattern: "^pinctrl@[0-9a-f]+$" - compatible: oneOf: - enum: @@ -121,6 +118,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg @@ -169,7 +169,7 @@ additionalProperties: examples: - | - pin-controller@10010000 { + pinctrl@10010000 { compatible = "ingenic,jz4770-pinctrl"; reg = <0x10010000 0x600>; diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml index 2c0acb405e6c..b42548350188 100644 --- a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -47,6 +47,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index f8e6e138dc13..6953c958ff7c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -64,6 +64,9 @@ required: - gpio-controller - "#gpio-cells" +allOf: + - $ref: "pinctrl.yaml#" + patternProperties: '-[0-9]+$': type: object diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 152c151c27ad..e7601c0f5a69 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -59,6 +59,9 @@ properties: "#interrupt-cells": const: 2 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml index 76a6df75ed9c..d42215f59afd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml @@ -45,6 +45,9 @@ properties: "#interrupt-cells": const: 2 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 0feecd376c69..78a0175cecc7 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -42,6 +42,9 @@ properties: "#interrupt-cells": const: 2 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 7602b11e8bce..4eadea55df10 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -56,6 +56,9 @@ properties: "#interrupt-cells": const: 2 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index cc1509e9b981..2d13a57b8961 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -56,6 +56,9 @@ properties: "#interrupt-cells": const: 2 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index c4c071211611..3c84676a167d 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -108,6 +108,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 5e2bb2bf3a55..3cf74df12862 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -187,6 +187,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml index c64c93206817..b83c7f476e19 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -118,6 +118,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml index e47ebf934daf..5c5542f1627c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml @@ -103,6 +103,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml index 3b02dc6626ed..f7bd4be1739e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml @@ -14,6 +14,7 @@ description: | MDM9607 platform. allOf: + - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index 040d2ada3669..ab4a2b4cfda2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -97,6 +97,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index abe9f4c9b1e3..64c0a41ca0c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -133,6 +133,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml index 13f338619d77..206f4f238736 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml @@ -118,6 +118,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 7d6a2ab10eec..6c7c3f6a140e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -123,6 +123,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml index a82dab898395..86509172603d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml @@ -14,6 +14,7 @@ description: | SC8180X platform. allOf: + - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index 112dd59ce7ed..a38090b14aab 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -118,6 +118,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml index 8fc06f6a3ef4..cfcde405d30a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml @@ -121,6 +121,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml index 5f7adaa81f83..c8eec845ade9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml @@ -13,6 +13,7 @@ description: | in the SM6125 platform. allOf: + - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml index 554992a681f3..898608671c4b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml @@ -14,6 +14,7 @@ description: | in the SM6350 platform. allOf: + - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 8508c57522fd..cfa2c50fdb93 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -115,6 +115,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml index 4f2667ea2805..6b7789db2f75 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml @@ -14,6 +14,7 @@ description: | in the SM8350 platform. allOf: + - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index 3b37cf102d41..be8cb0ead62f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -51,6 +51,9 @@ properties: should not be accessed by the OS. Please see the ../gpio/gpio.txt for more information. +allOf: + - $ref: "pinctrl.yaml#" + required: - interrupts - interrupt-controller diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml index b32f2676cab5..f0c52feb24d7 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml @@ -44,6 +44,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index ac4e068aa03f..8548e3639b75 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -70,6 +70,9 @@ properties: power-domains: maxItems: 1 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml index 7f80578dc229..8ed4b98a1628 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -31,6 +31,9 @@ properties: reg: maxItems: 1 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml index ce1f7343788f..d761fddc2206 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -72,6 +72,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index ef68dabcf4dc..302785d7d771 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -90,6 +90,9 @@ additionalProperties: additionalProperties: $ref: "#/additionalProperties/anyOf/0" +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml index 4a43af0d6e02..70b1788ab594 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -31,6 +31,9 @@ properties: description: The bus clock, sometimes described as pclk, for register accesses. +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 07c0a98ef9c6..b0eae3a67ab1 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -67,6 +67,9 @@ properties: ranges: true +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - rockchip,grf diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml index 27c5762b9cf8..14a8c0215cc6 100644 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -10,9 +10,6 @@ maintainers: - Masahiro Yamada properties: - $nodename: - pattern: "pinctrl" - compatible: enum: - socionext,uniphier-ld4-pinctrl @@ -62,6 +59,9 @@ additionalProperties: unevaluatedProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index ac88e01ec430..83a18d0331b1 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -183,6 +183,9 @@ patternProperties: required: - pinmux +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - '#address-cells' diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml index 9f1dab0c2430..306524885a2b 100644 --- a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -20,6 +20,9 @@ properties: reg: maxItems: 1 +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg @@ -80,7 +83,7 @@ examples: #address-cells = <2>; #size-cells = <2>; - pmux: pmux@24190000 { + pmux: pinmux@24190000 { compatible = "toshiba,tmpv7708-pinctrl"; reg = <0 0x24190000 0 0x10000>; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml index ac97dbf6998e..cfd0cc549a7b 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml @@ -167,6 +167,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: "pinctrl.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 8ef0d07d35fe..2722dc7bb03d 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -290,6 +290,9 @@ patternProperties: additionalProperties: false +allOf: + - $ref: pinctrl.yaml# + required: - compatible From ea7e26ebe6a90fe7962823a70ac91f010df71239 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Dec 2021 14:22:55 +0100 Subject: [PATCH 76/98] pinctrl: renesas: r8a779a0: Align comments Align the CANFD4_TX and AVB2_MDC comments with all others. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/886ef84ea6b8314d348953792c9616b3e5dc28c0.1638537704.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779a0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index ad6532443a78..83580385c3ca 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -3835,7 +3835,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ - { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */ { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ } }, { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) { @@ -4305,7 +4305,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ - [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/ + [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */ [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ From 82dc44e7c650618c4fe26dbfe290372f4904bbe2 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:54:33 +0530 Subject: [PATCH 77/98] dt-bindings: pinctrl: qcom: Add SM8450 pinctrl bindings Add device tree binding Documentation details for Qualcomm SM8450 TLMM device Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211201072434.3968768-2-vkoul@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8450-pinctrl.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml new file mode 100644 index 000000000000..9c891246245b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8450 TLMM block + +maintainers: + - Vinod Koul + +description: | + This binding describes the Top Level Mode Multiplexer (TLMM) block found + in the SM8450 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8450-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sm8450-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sm8450-tlmm-state" + +$defs: + qcom-sm8450-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async, + cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, + mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, + mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, + mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn, + pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s, + prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request, + qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss, + qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, + qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, + qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2, + qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, + qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, + usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; + }; + }; +... From 4beb02f19c37e6fbe941d786119ed82ec0aca19a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:54:34 +0530 Subject: [PATCH 78/98] pinctrl: qcom: Add SM8450 pinctrl driver This adds pincontrol driver for tlmm block found in SM8450 SoC This patch is based on initial code downstream by Elliot Berman Signed-off-by: Vinod Koul Tested-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072434.3968768-3-vkoul@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8450.c | 1689 +++++++++++++++++++++++++ 3 files changed, 1699 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8450.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index d77637054a15..ca6f68a061a8 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -337,6 +337,15 @@ config PINCTRL_SM8350 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8350 platform. +config PINCTRL_SM8450 + tristate "Qualcomm Technologies Inc SM8450 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8450 platform. + config PINCTRL_LPASS_LPI tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" select PINMUX diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index ecf20b5e615e..709882f54d25 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -39,4 +39,5 @@ obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o +obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c new file mode 100644 index 000000000000..c6fa3dbc14a1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -0,0 +1,1689 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8450_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "UFS_RESET"), + PINCTRL_PIN(211, "SDC2_CLK"), + PINCTRL_PIN(212, "SDC2_CMD"), + PINCTRL_PIN(213, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); + +static const unsigned int ufs_reset_pins[] = { 210 }; +static const unsigned int sdc2_clk_pins[] = { 211 }; +static const unsigned int sdc2_cmd_pins[] = { 212 }; +static const unsigned int sdc2_data_pins[] = { 213 }; + +enum sm8450_functions { + msm_mux_gpio, + msm_mux_aon_cam, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + +static const char * const aon_cam_groups[] = { + "gpio108", +}; + +static const char * const atest_char_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", +}; + +static const char * const atest_usb_groups[] = { + "gpio37", "gpio39", "gpio55", "gpio148", "gpio149", +}; + +static const char * const audio_ref_groups[] = { + "gpio124", +}; + +static const char * const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const cci_async_groups[] = { + "gpio109", "gpio119", "gpio120", +}; + +static const char * const cci_i2c_groups[] = { + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio208", "gpio209", +}; + +static const char * const cci_timer_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char * const cmu_rng_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", +}; + +static const char * const coex_uart1_groups[] = { + "gpio148", "gpio149", +}; + +static const char * const coex_uart2_groups[] = { + "gpio150", "gpio151", +}; + +static const char * const cri_trng_groups[] = { + "gpio99", +}; + +static const char * const cri_trng0_groups[] = { + "gpio71", +}; + +static const char * const cri_trng1_groups[] = { + "gpio72", +}; + +static const char * const dbg_out_groups[] = { + "gpio9", +}; + +static const char * const ddr_bist_groups[] = { + "gpio36", "gpio37", "gpio40", "gpio41", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio40", "gpio41", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio45", "gpio47", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const dp_hot_groups[] = { + "gpio47", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio86", "gpio134", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio87", "gpio135", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio88", "gpio136", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio28", "gpio29", "gpio32", "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char * const jitter_bist_groups[] = { + "gpio24", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio46", "gpio47", "gpio86", "gpio87", "gpio88", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio87", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio87", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio127", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio128", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio126", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio129", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio122", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio124", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio121", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio123", +}; + +static const char * const mss_grfc0_groups[] = { + "gpio138", "gpio153", +}; + +static const char * const mss_grfc1_groups[] = { + "gpio139", +}; + +static const char * const mss_grfc10_groups[] = { + "gpio150", +}; + +static const char * const mss_grfc11_groups[] = { + "gpio151", +}; + +static const char * const mss_grfc12_groups[] = { + "gpio152", +}; + +static const char * const mss_grfc2_groups[] = { + "gpio140", +}; + +static const char * const mss_grfc3_groups[] = { + "gpio141", +}; + +static const char * const mss_grfc4_groups[] = { + "gpio142", +}; + +static const char * const mss_grfc5_groups[] = { + "gpio143", +}; + +static const char * const mss_grfc6_groups[] = { + "gpio144", +}; + +static const char * const mss_grfc7_groups[] = { + "gpio145", +}; + +static const char * const mss_grfc8_groups[] = { + "gpio146", +}; + +static const char * const mss_grfc9_groups[] = { + "gpio147", +}; + +static const char * const nav_groups[] = { + "gpio153", "gpio154", "gpio155", +}; + +static const char * const pcie0_clkreqn_groups[] = { + "gpio95", +}; + +static const char * const pcie1_clkreqn_groups[] = { + "gpio98", +}; + +static const char * const phase_flag_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio25", "gpio26", + "gpio76", "gpio77", "gpio78", "gpio79", "gpio81", "gpio82", "gpio83", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const pll_bist_groups[] = { + "gpio20", +}; + +static const char * const pll_clk_groups[] = { + "gpio107", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio125", +}; + +static const char * const prng_rosc_groups[] = { + "gpio73", "gpio75", "gpio81", "gpio83", "gpio81", +}; + +static const char * const qdss_cti_groups[] = { + "gpio2", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio93", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio188", "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", + "gpio194", "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", + "gpio202", "gpio203", "gpio204", "gpio205", +}; + +static const char * const qlink0_enable_groups[] = { + "gpio157", +}; + +static const char * const qlink0_request_groups[] = { + "gpio156", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio158", +}; + +static const char * const qlink1_enable_groups[] = { + "gpio160", +}; + +static const char * const qlink1_request_groups[] = { + "gpio159", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio161", +}; + +static const char * const qlink2_enable_groups[] = { + "gpio163", +}; + +static const char * const qlink2_request_groups[] = { + "gpio162", +}; + +static const char * const qlink2_wmss_groups[] = { + "gpio164", +}; + +static const char * const qspi0_groups[] = { + "gpio52", +}; + +static const char * const qspi1_groups[] = { + "gpio53", +}; + +static const char * const qspi2_groups[] = { + "gpio48", +}; + +static const char * const qspi3_groups[] = { + "gpio49", +}; + +static const char * const qspi_clk_groups[] = { + "gpio50", +}; + +static const char * const qspi_cs_groups[] = { + "gpio51", "gpio54", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup10_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup11_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup12_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup13_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup14_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup15_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const qup16_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const qup17_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const qup18_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const qup19_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const qup2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qup20_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const qup21_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const qup3_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qup5_groups[] = { + "gpio84", "gpio85", "gpio206", "gpio207", +}; + +static const char * const qup6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup8_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup9_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup_l4_groups[] = { + "gpio24", "gpio40", "gpio58", "gpio63", +}; + +static const char * const qup_l5_groups[] = { + "gpio25", "gpio41", "gpio59", "gpio66", +}; + +static const char * const qup_l6_groups[] = { + "gpio26", "gpio42", "gpio62", "gpio67", +}; + +static const char * const sd_write_groups[] = { + "gpio93", +}; + +static const char * const sdc40_groups[] = { + "gpio52", +}; + +static const char * const sdc41_groups[] = { + "gpio53", +}; + +static const char * const sdc42_groups[] = { + "gpio48", +}; + +static const char * const sdc43_groups[] = { + "gpio49", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio124", +}; + +static const char * const tb_trig_groups[] = { + "gpio64", "gpio137", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio64", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio65", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio66", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio67", +}; + +static const char * const tmess_prng0_groups[] = { + "gpio80", +}; + +static const char * const tmess_prng1_groups[] = { + "gpio79", +}; + +static const char * const tmess_prng2_groups[] = { + "gpio77", +}; + +static const char * const tmess_prng3_groups[] = { + "gpio76", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio91", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio91", +}; + +static const char * const uim0_clk_groups[] = { + "gpio131", +}; + +static const char * const uim0_data_groups[] = { + "gpio130", +}; + +static const char * const uim0_present_groups[] = { + "gpio133", +}; + +static const char * const uim0_reset_groups[] = { + "gpio132", +}; + +static const char * const uim1_clk_groups[] = { + "gpio135", +}; + +static const char * const uim1_data_groups[] = { + "gpio134", +}; + +static const char * const uim1_present_groups[] = { + "gpio137", +}; + +static const char * const uim1_reset_groups[] = { + "gpio136", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio90", +}; + +static const char * const usb_phy_groups[] = { + "gpio91", +}; + +static const char * const vfr_0_groups[] = { + "gpio89", +}; + +static const char * const vfr_1_groups[] = { + "gpio155", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio18", +}; + +static const struct msm_function sm8450_functions[] = { + FUNCTION(gpio), + FUNCTION(aon_cam), + FUNCTION(atest_char), + FUNCTION(atest_usb), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer), + FUNCTION(cmu_rng), + FUNCTION(coex_uart1), + FUNCTION(coex_uart2), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(mss_grfc0), + FUNCTION(mss_grfc1), + FUNCTION(mss_grfc10), + FUNCTION(mss_grfc11), + FUNCTION(mss_grfc12), + FUNCTION(mss_grfc2), + FUNCTION(mss_grfc3), + FUNCTION(mss_grfc4), + FUNCTION(mss_grfc5), + FUNCTION(mss_grfc6), + FUNCTION(mss_grfc7), + FUNCTION(mss_grfc8), + FUNCTION(mss_grfc9), + FUNCTION(nav), + FUNCTION(pcie0_clkreqn), + FUNCTION(pcie1_clkreqn), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_clk), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qlink0_enable), + FUNCTION(qlink0_request), + FUNCTION(qlink0_wmss), + FUNCTION(qlink1_enable), + FUNCTION(qlink1_request), + FUNCTION(qlink1_wmss), + FUNCTION(qlink2_enable), + FUNCTION(qlink2_request), + FUNCTION(qlink2_wmss), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup2), + FUNCTION(qup20), + FUNCTION(qup21), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sec_mi2s), + FUNCTION(tb_trig), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tmess_prng0), + FUNCTION(tmess_prng1), + FUNCTION(tmess_prng2), + FUNCTION(tmess_prng3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(uim0_clk), + FUNCTION(uim0_data), + FUNCTION(uim0_present), + FUNCTION(uim0_reset), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(usb2phy_ac), + FUNCTION(usb_phy), + FUNCTION(vfr_0), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8450_groups[] = { + [0] = PINGROUP(0, qup0, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup0, qdss_cti, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup1, phase_flag, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup1, phase_flag, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup1, phase_flag, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup1, phase_flag, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup2, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup2, dbg_out, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup2, phase_flag, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup2, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3, phase_flag, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3, phase_flag, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3, phase_flag, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3, phase_flag, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup4, phase_flag, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup4, phase_flag, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup4, phase_flag, _, vsense_trigger, _, _, _, _, _), + [19] = PINGROUP(19, qup4, phase_flag, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup6, pll_bist, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup6, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup6, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup6, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup7, qup_l4, jitter_bist, _, _, _, _, _, _), + [25] = PINGROUP(25, qup7, qup_l5, phase_flag, _, _, _, _, _, _), + [26] = PINGROUP(26, qup7, qup_l6, phase_flag, _, _, _, _, _, _), + [27] = PINGROUP(27, qup7, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup8, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup8, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup8, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup8, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup9, ibi_i3c, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup9, ibi_i3c, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup9, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup9, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup10, ddr_bist, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup10, ddr_bist, atest_usb, _, _, _, _, _, _), + [38] = PINGROUP(38, qup10, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup10, atest_usb, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup11, qup_l4, ddr_bist, ddr_pxi1, _, _, _, _, _), + [41] = PINGROUP(41, qup11, qup_l5, ddr_bist, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, qup11, qup_l6, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup11, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup12, ddr_pxi3, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup12, ddr_pxi2, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup12, mdp_vsync, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup12, dp_hot, mdp_vsync, ddr_pxi2, _, _, _, _, _), + [48] = PINGROUP(48, qup13, qspi2, sdc42, _, _, _, _, _, _), + [49] = PINGROUP(49, qup13, qspi3, sdc43, _, _, _, _, _, _), + [50] = PINGROUP(50, qup13, qspi_clk, sdc4_clk, _, _, _, _, _, _), + [51] = PINGROUP(51, qup13, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = PINGROUP(52, qup14, qspi0, sdc40, ddr_pxi0, _, _, _, _, _), + [53] = PINGROUP(53, qup14, qspi1, sdc41, _, _, _, _, _, _), + [54] = PINGROUP(54, qup14, qspi_cs, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup14, atest_usb, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup15, ibi_i3c, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup15, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup15, qup_l4, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup15, qup_l5, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup16, ibi_i3c, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup16, ibi_i3c, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup16, qup_l6, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup16, qup_l4, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup17, tb_trig, tgu_ch0, _, _, _, _, _, _), + [65] = PINGROUP(65, qup17, tgu_ch1, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qup17, qup_l5, tgu_ch2, _, _, _, _, _, _), + [67] = PINGROUP(67, qup17, qup_l6, tgu_ch3, _, _, _, _, _, _), + [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qup18, cri_trng0, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qup19, cri_trng1, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qup19, prng_rosc, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup19, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup19, prng_rosc, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup20, phase_flag, tmess_prng3, _, _, _, _, _, _), + [77] = PINGROUP(77, qup20, phase_flag, tmess_prng2, _, _, _, _, _, _), + [78] = PINGROUP(78, qup20, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qup20, phase_flag, tmess_prng1, _, _, _, _, _, _), + [80] = PINGROUP(80, qup21, qdss_cti, phase_flag, tmess_prng0, _, _, _, _, _), + [81] = PINGROUP(81, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), + [82] = PINGROUP(82, qup21, qdss_cti, phase_flag, _, _, _, _, _, _), + [83] = PINGROUP(83, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), + [84] = PINGROUP(84, qup5, qdss_cti, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qup5, qdss_cti, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0, mdp_vsync1, gcc_gp1, atest_char, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2, mdp_vsync3, gcc_gp2, atest_char, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync, gcc_gp3, atest_char, _, _, _, _, _, _), + [89] = PINGROUP(89, vfr_0, atest_char, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb2phy_ac, atest_char, _, _, _, _, _, _, _), + [91] = PINGROUP(91, usb_phy, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [92] = PINGROUP(92, phase_flag, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, sd_write, qdss_cti, phase_flag, _, _, _, _, _, _), + [94] = PINGROUP(94, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [95] = PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, _), + [96] = PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [97] = PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [98] = PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _), + [99] = PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cam_mclk, qdss_gpio, pll_clk, _, _, _, _, _, _), + [108] = PINGROUP(108, aon_cam, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_async, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_timer, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, cci_timer, qdss_gpio, _, _, _, _, _, _, _), + [118] = PINGROUP(118, cci_timer, qdss_gpio, _, _, _, _, _, _, _), + [119] = PINGROUP(119, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), + [120] = PINGROUP(120, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), + [121] = PINGROUP(121, mi2s2_sck, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, mi2s2_data0, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, mi2s2_ws, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, mi2s2_data1, sec_mi2s, audio_ref, _, _, _, _, _, _), + [125] = PINGROUP(125, pri_mi2s, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, mi2s0_sck, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, mi2s0_data0, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, mi2s0_data1, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, mi2s0_ws, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim0_data, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim0_reset, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim0_present, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_data, gcc_gp1, _, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_clk, gcc_gp2, _, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), + [137] = PINGROUP(137, uim1_present, tb_trig, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, mss_grfc0, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, mss_grfc1, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, mss_grfc2, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, mss_grfc3, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, mss_grfc4, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, mss_grfc5, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, mss_grfc6, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, mss_grfc7, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, mss_grfc8, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, mss_grfc9, _, _, _, _, _, _, _), + [148] = PINGROUP(148, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [149] = PINGROUP(149, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [150] = PINGROUP(150, coex_uart2, mss_grfc10, _, _, _, _, _, _, _), + [151] = PINGROUP(151, coex_uart2, mss_grfc11, _, _, _, _, _, _, _), + [152] = PINGROUP(152, mss_grfc12, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, mss_grfc0, nav, _, _, _, _, _, _, _), + [154] = PINGROUP(154, nav, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, nav, vfr_1, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink0_request, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qlink0_enable, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink1_request, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink1_enable, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qlink1_wmss, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _), + [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _), + [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _), + [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _), + [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _), + [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _), + [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _), + [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _), + [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _), + [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _), + [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _), + [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _), + [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _), + [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _), + [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _), + [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _), + [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _), + [210] = UFS_RESET(ufs_reset, 0xde000), + [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), + [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), + [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8450_pdc_map[] = { + { 2, 70 }, { 3, 77 }, { 7, 52 }, { 8, 108 }, { 10, 128 }, { 11, 53 }, + { 12, 129 }, { 13, 130 }, { 14, 131 }, { 15, 67 }, { 19, 69 }, { 21, 132 }, + { 23, 54 }, { 26, 56 }, { 27, 71 }, { 28, 57 }, { 31, 55 }, { 32, 58 }, + { 34, 72 }, { 35, 43 }, { 36, 78 }, { 38, 79 }, { 39, 62 }, { 40, 80 }, + { 41, 133 }, { 43, 81 }, { 44, 87 }, { 45, 134 }, { 46, 66 }, { 47, 63 }, + { 50, 88 }, { 51, 89 }, { 55, 90 }, { 56, 59 }, { 59, 82 }, { 60, 60 }, + { 62, 135 }, { 63, 91 }, { 66, 136 }, { 67, 44 }, { 69, 137 }, { 71, 97 }, + { 75, 73 }, { 79, 74 }, { 80, 96 }, { 81, 98 }, { 82, 45 }, { 83, 99 }, + { 84, 94 }, { 85, 100 }, { 86, 101 }, { 87, 102 }, { 88, 92 }, { 89, 83 }, + { 90, 84 }, { 91, 85 }, { 92, 46 }, { 95, 103 }, { 96, 104 }, { 98, 105 }, + { 99, 106 }, { 115, 95 }, { 116, 76 }, { 117, 75 }, { 118, 86 }, { 119, 93 }, + { 133, 47 }, { 137, 42 }, { 148, 61 }, { 150, 68 }, { 153, 65 }, { 154, 48 }, + { 155, 49 }, { 156, 64 }, { 159, 50 }, { 162, 51 }, { 166, 111 }, { 169, 114 }, + { 171, 115 }, { 172, 116 }, { 174, 117 }, { 176, 107 }, { 181, 109 }, + { 182, 110 }, { 185, 112 }, { 187, 113 }, { 188, 118 }, { 190, 122 }, + { 192, 123 }, { 195, 124 }, { 201, 119 }, { 203, 120 }, { 205, 121 }, +}; + +static const struct msm_pinctrl_soc_data sm8450_tlmm = { + .pins = sm8450_pins, + .npins = ARRAY_SIZE(sm8450_pins), + .functions = sm8450_functions, + .nfunctions = ARRAY_SIZE(sm8450_functions), + .groups = sm8450_groups, + .ngroups = ARRAY_SIZE(sm8450_groups), + .ngpios = 211, + .wakeirq_map = sm8450_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), +}; + +static int sm8450_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8450_tlmm); +} + +static const struct of_device_id sm8450_tlmm_of_match[] = { + { .compatible = "qcom,sm8450-tlmm", }, + { }, +}; + +static struct platform_driver sm8450_tlmm_driver = { + .driver = { + .name = "sm8450-tlmm", + .of_match_table = sm8450_tlmm_of_match, + }, + .probe = sm8450_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8450_tlmm_init(void) +{ + return platform_driver_register(&sm8450_tlmm_driver); +} +arch_initcall(sm8450_tlmm_init); + +static void __exit sm8450_tlmm_exit(void) +{ + platform_driver_unregister(&sm8450_tlmm_driver); +} +module_exit(sm8450_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8450 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); From bd92baaa262dc1342f1514a3937f151d37ee740d Mon Sep 17 00:00:00 2001 From: Lakshmi Sowjanya D Date: Wed, 1 Dec 2021 12:56:25 +0530 Subject: [PATCH 79/98] dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver Add Device Tree bindings documentation and an entry in MAINTAINERS file for Intel Thunder Bay SoC's pin controller. Signed-off-by: Lakshmi Sowjanya D Link: https://lore.kernel.org/r/20211201072626.19599-2-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij --- .../pinctrl/intel,pinctrl-thunderbay.yaml | 119 ++++++++++++++++++ MAINTAINERS | 5 + 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml new file mode 100644 index 000000000000..0ec476248f21 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Thunder Bay pin controller Device Tree Bindings + +maintainers: + - Lakshmi Sowjanya D + +description: | + Intel Thunder Bay SoC integrates a pin controller which enables control + of pin directions, input/output values and configuration + for a total of 67 pins. + +properties: + compatible: + const: intel,thunderbay-pinctrl + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupts: + description: + Specifies the interrupt lines to be used by the controller. + maxItems: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '^gpio@[0-9a-f]*$': + type: object + + description: + Child nodes can be specified to contain pin configuration information, + which can then be utilized by pinctrl client devices. + The following properties are supported. + + properties: + pins: + description: | + The name(s) of the pins to be configured in the child node. + Supported pin names are "GPIO0" up to "GPIO66". + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + drive-strength: + description: Drive strength for the pad. + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + + bias-bus-hold: + type: boolean + + input-schmitt-enable: + type: boolean + + slew-rate: + description: GPIO slew rate control. + 0 - Slow + 1 - Fast + enum: [0, 1] + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + #include + // Example 1 + pinctrl0: gpio@0 { + compatible = "intel,thunderbay-pinctrl"; + reg = <0x600b0000 0x88>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&pinctrl0 0 0 67>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // Example 2 + pinctrl1: gpio@1 { + compatible = "intel,thunderbay-pinctrl"; + reg = <0x600c0000 0x88>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&pinctrl1 0 0 53>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5250298d2817..7741bcc23502 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15117,6 +15117,11 @@ L: linux-omap@vger.kernel.org S: Maintained F: drivers/pinctrl/pinctrl-single.c +PIN CONTROLLER - THUNDERBAY +M: Lakshmi Sowjanya D +S: Supported +F: drivers/pinctrl/pinctrl-thunderbay.c + PKTCDVD DRIVER M: linux-block@vger.kernel.org S: Orphan From 12422af8194df85243d68b11f8783de9d01e58dc Mon Sep 17 00:00:00 2001 From: Lakshmi Sowjanya D Date: Wed, 1 Dec 2021 12:56:26 +0530 Subject: [PATCH 80/98] pinctrl: Add Intel Thunder Bay pinctrl driver About Intel Thunder Bay: ----------------------- Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Thunder Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Thunder Bay SoC. Co-developed-by: Kiran Kumar S Signed-off-by: Kiran Kumar S Signed-off-by: Lakshmi Sowjanya D Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 19 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-thunderbay.c | 1322 ++++++++++++++++++++++++++ 3 files changed, 1342 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-thunderbay.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6a961d5f8726..a3457a4b4d9d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -499,4 +499,23 @@ config PINCTRL_EQUILIBRIUM pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and pinconf settings are retrieved from device tree. +config PINCTRL_THUNDERBAY + tristate "Generic pinctrl and GPIO driver for Intel Thunder Bay SoC" + depends on ARCH_THUNDERBAY || (ARM64 && COMPILE_TEST) + depends on HAS_IOMEM + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_GENERIC + help + This selects pin control driver for the Intel Thunder Bay SoC. + It provides pin config functions such as pullup, pulldown, + interrupt, drive strength, sec lock, schmitt trigger, slew + rate control and direction control. This module will be + called as pinctrl-thunderbay. + endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 5e63de2ffcf4..0d5744e7f8fb 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o +obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/pinctrl/pinctrl-thunderbay.c b/drivers/pinctrl/pinctrl-thunderbay.c new file mode 100644 index 000000000000..b5b47f4dd774 --- /dev/null +++ b/drivers/pinctrl/pinctrl-thunderbay.c @@ -0,0 +1,1322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Thunder Bay SOC pinctrl/GPIO driver + * + * Copyright (C) 2021 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" +#include "pinmux.h" + +/* Bit 0:2 and 4:6 should be used for mode selection */ +#define THB_GPIO_PINMUX_MODE_0 0x00 +#define THB_GPIO_PINMUX_MODE_1 0x11 +#define THB_GPIO_PINMUX_MODE_2 0x22 +#define THB_GPIO_PINMUX_MODE_3 0x33 +#define THB_GPIO_PINMUX_MODE_4 0x44 + +#define THB_GPIO_PORT_SELECT_MASK BIT(8) +#define THB_GPIO_PAD_DIRECTION_MASK BIT(10) +#define THB_GPIO_SPU_MASK BIT(11) +#define THB_GPIO_PULL_ENABLE_MASK BIT(12) +#define THB_GPIO_PULL_UP_MASK BIT(13) +#define THB_GPIO_PULL_DOWN_MASK BIT(14) +#define THB_GPIO_ENAQ_MASK BIT(15) +/* bit 16-19: Drive Strength for the Pad */ +#define THB_GPIO_DRIVE_STRENGTH_MASK (0xF0000) +#define THB_GPIO_SLEW_RATE_MASK BIT(20) +#define THB_GPIO_SCHMITT_TRIGGER_MASK BIT(21) + +#define THB_GPIO_REG_OFFSET(pin_num) ((pin_num) * (0x4)) +#define THB_MAX_MODE_SUPPORTED (5u) +#define THB_MAX_NPINS_SUPPORTED (67u) + +/* store Pin status */ +static u32 thb_pinx_status[THB_MAX_NPINS_SUPPORTED]; + +struct thunderbay_mux_desc { + u8 mode; + const char *name; +}; + +#define THUNDERBAY_PIN_DESC(pin_number, pin_name, ...) { \ + .number = pin_number, \ + .name = pin_name, \ + .drv_data = &(struct thunderbay_mux_desc[]) { \ + __VA_ARGS__, { } }, \ +} + +#define THUNDERBAY_MUX(pin_mode, pin_function) { \ + .mode = pin_mode, \ + .name = pin_function, \ +} + +struct thunderbay_pin_soc { + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +/** + * struct thunderbay_pinctrl - Intel Thunderbay pinctrl structure + * @pctrl: Pointer to the pin controller device + * @base0: First register base address + * @dev: Pointer to the device structure + * @chip: GPIO chip used by this pin controller + * @soc: Pin control configuration data based on SoC + * @ngroups: Number of pin groups available + * @nfuncs: Number of pin functions available + */ +struct thunderbay_pinctrl { + struct pinctrl_dev *pctrl; + void __iomem *base0; + struct device *dev; + struct gpio_chip chip; + const struct thunderbay_pin_soc *soc; + unsigned int ngroups; + unsigned int nfuncs; +}; + +static const struct pinctrl_pin_desc thunderbay_pins[] = { + THUNDERBAY_PIN_DESC(0, "GPIO0", + THUNDERBAY_MUX(0X0, "I2C0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(1, "GPIO1", + THUNDERBAY_MUX(0X0, "I2C0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(2, "GPIO2", + THUNDERBAY_MUX(0X0, "I2C1_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(3, "GPIO3", + THUNDERBAY_MUX(0X0, "I2C1_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(4, "GPIO4", + THUNDERBAY_MUX(0X0, "I2C2_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(5, "GPIO5", + THUNDERBAY_MUX(0X0, "I2C2_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(6, "GPIO6", + THUNDERBAY_MUX(0X0, "I2C3_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(7, "GPIO7", + THUNDERBAY_MUX(0X0, "I2C3_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(8, "GPIO8", + THUNDERBAY_MUX(0X0, "I2C4_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(9, "GPIO9", + THUNDERBAY_MUX(0X0, "I2C4_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(10, "GPIO10", + THUNDERBAY_MUX(0X0, "UART0_M0"), + THUNDERBAY_MUX(0X1, "RT0_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(11, "GPIO11", + THUNDERBAY_MUX(0X0, "UART0_M0"), + THUNDERBAY_MUX(0X1, "RT0_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(12, "GPIO12", + THUNDERBAY_MUX(0X0, "UART0_M0"), + THUNDERBAY_MUX(0X1, "RT1_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(13, "GPIO13", + THUNDERBAY_MUX(0X0, "UART0_M0"), + THUNDERBAY_MUX(0X1, "RT1_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(14, "GPIO14", + THUNDERBAY_MUX(0X0, "UART1_M0"), + THUNDERBAY_MUX(0X1, "RT2_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "TRIGGER_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(15, "GPIO15", + THUNDERBAY_MUX(0X0, "UART1_M0"), + THUNDERBAY_MUX(0X1, "RT2_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "TRIGGER_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(16, "GPIO16", + THUNDERBAY_MUX(0X0, "UART1_M0"), + THUNDERBAY_MUX(0X1, "RT3_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(17, "GPIO17", + THUNDERBAY_MUX(0X0, "UART1_M0"), + THUNDERBAY_MUX(0X1, "RT3_DSU_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(18, "GPIO18", + THUNDERBAY_MUX(0X0, "SPI0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(19, "GPIO19", + THUNDERBAY_MUX(0X0, "SPI0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(20, "GPIO20", + THUNDERBAY_MUX(0X0, "SPI0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "TPIU_TRACE_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(21, "GPIO21", + THUNDERBAY_MUX(0X0, "SPI0_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "TPIU_TRACE_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(22, "GPIO22", + THUNDERBAY_MUX(0X0, "SPI1_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M0"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(23, "GPIO23", + THUNDERBAY_MUX(0X0, "SPI1_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(24, "GPIO24", + THUNDERBAY_MUX(0X0, "SPI1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_TRACE_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(25, "GPIO25", + THUNDERBAY_MUX(0X0, "SPI1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_TRACE_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(26, "GPIO26", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(27, "GPIO27", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(28, "GPIO28", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(29, "GPIO29", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(30, "GPIO30", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(31, "GPIO31", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(32, "GPIO32", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(33, "GPIO33", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(34, "GPIO34", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DIG_VIEW_0"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(35, "GPIO35", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DIG_VIEW_1"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(36, "GPIO36", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_0"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(37, "GPIO37", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_1"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(38, "GPIO38", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_2"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(39, "GPIO39", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(40, "GPIO40", + THUNDERBAY_MUX(0X0, "ETHER0_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(41, "GPIO41", + THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_MAX_PLATFORM_POWER_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(42, "GPIO42", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(43, "GPIO43", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(44, "GPIO44", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(45, "GPIO45", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(46, "GPIO46", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(47, "GPIO47", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(48, "GPIO48", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(49, "GPIO49", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DEBUG_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(50, "GPIO50", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DIG_VIEW_0"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(51, "GPIO51", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "DIG_VIEW_1"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(52, "GPIO52", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_0"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(53, "GPIO53", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_1"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(54, "GPIO54", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_2"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(55, "GPIO55", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(56, "GPIO56", + THUNDERBAY_MUX(0X0, "ETHER1_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "POWER_INTERRUPT_ICCMAX_VDDD_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(57, "GPIO57", + THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_ICCMAX_VPU_M0"), + THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"), + THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(58, "GPIO58", + THUNDERBAY_MUX(0X0, "THERMTRIP_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(59, "GPIO59", + THUNDERBAY_MUX(0X0, "THERMTRIP_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(60, "GPIO60", + THUNDERBAY_MUX(0X0, "SMBUS_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(61, "GPIO61", + THUNDERBAY_MUX(0X0, "SMBUS_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "POWER_INTERRUPT_ICCMAX_VDDD_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(62, "GPIO62", + THUNDERBAY_MUX(0X0, "PLATFORM_RESET_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(63, "GPIO63", + THUNDERBAY_MUX(0X0, "PLATFORM_RESET_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(64, "GPIO64", + THUNDERBAY_MUX(0X0, "PLATFORM_SHUTDOWN_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(65, "GPIO65", + THUNDERBAY_MUX(0X0, "PLATFORM_SHUTDOWN_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), + THUNDERBAY_PIN_DESC(66, "GPIO66", + THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_ICCMAX_MEDIA_M0"), + THUNDERBAY_MUX(0X1, "EMPTY_M1"), + THUNDERBAY_MUX(0X2, "EMPTY_M2"), + THUNDERBAY_MUX(0X3, "EMPTY_M3"), + THUNDERBAY_MUX(0X4, "GPIO_M4")), +}; + +static const struct thunderbay_pin_soc thunderbay_data = { + .pins = thunderbay_pins, + .npins = ARRAY_SIZE(thunderbay_pins), +}; + +static u32 thb_gpio_read_reg(struct gpio_chip *chip, unsigned int pinnr) +{ + struct thunderbay_pinctrl *tpc = gpiochip_get_data(chip); + + return readl(tpc->base0 + THB_GPIO_REG_OFFSET(pinnr)); +} + +static u32 thb_gpio_write_reg(struct gpio_chip *chip, unsigned int pinnr, u32 value) +{ + struct thunderbay_pinctrl *tpc = gpiochip_get_data(chip); + + writel(value, (tpc->base0 + THB_GPIO_REG_OFFSET(pinnr))); + return 0; +} + +static int thb_read_gpio_data(struct gpio_chip *chip, unsigned int offset, unsigned int pad_dir) +{ + int data_offset; + u32 data_reg; + + /* as per GPIO Spec = pad_dir 0:input, 1:output */ + data_offset = 0x2000u + (offset / 32); + if (!pad_dir) + data_offset += 4; + data_reg = thb_gpio_read_reg(chip, data_offset); + + return data_reg & BIT(offset % 32); +} + +static int thb_write_gpio_data(struct gpio_chip *chip, unsigned int offset, unsigned int value) +{ + int data_offset; + u32 data_reg; + + data_offset = 0x2000u + (offset / 32); + + data_reg = thb_gpio_read_reg(chip, data_offset); + + if (value > 0) + data_reg |= BIT(offset % 32); + else + data_reg &= ~BIT(offset % 32); + + return thb_gpio_write_reg(chip, data_offset, data_reg); +} + +static int thunderbay_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + u32 reg = thb_gpio_read_reg(chip, offset); + + /* Return direction only if configured as GPIO else negative error */ + if (reg & THB_GPIO_PORT_SELECT_MASK) + return !(reg & THB_GPIO_PAD_DIRECTION_MASK); + return -EINVAL; +} + +static int thunderbay_gpio_set_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + u32 reg = thb_gpio_read_reg(chip, offset); + + /* set pin as input only if it is GPIO else error */ + if (reg & THB_GPIO_PORT_SELECT_MASK) { + reg &= (~THB_GPIO_PAD_DIRECTION_MASK); + thb_gpio_write_reg(chip, offset, reg); + return 0; + } + return -EINVAL; +} + +static void thunderbay_gpio_set_value(struct gpio_chip *chip, unsigned int offset, int value) +{ + u32 reg = thb_gpio_read_reg(chip, offset); + + /* update pin value only if it is GPIO-output else error */ + if ((reg & THB_GPIO_PORT_SELECT_MASK) && (reg & THB_GPIO_PAD_DIRECTION_MASK)) + thb_write_gpio_data(chip, offset, value); +} + +static int thunderbay_gpio_set_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + u32 reg = thb_gpio_read_reg(chip, offset); + + /* set pin as output only if it is GPIO else error */ + if (reg & THB_GPIO_PORT_SELECT_MASK) { + reg |= THB_GPIO_PAD_DIRECTION_MASK; + thb_gpio_write_reg(chip, offset, reg); + thunderbay_gpio_set_value(chip, offset, value); + return 0; + } + return -EINVAL; +} + +static int thunderbay_gpio_get_value(struct gpio_chip *chip, unsigned int offset) +{ + u32 reg = thb_gpio_read_reg(chip, offset); + int gpio_dir = 0; + + /* Read pin value only if it is GPIO else error */ + if (reg & THB_GPIO_PORT_SELECT_MASK) { + /* 0=in, 1=out */ + gpio_dir = (reg & THB_GPIO_PAD_DIRECTION_MASK) > 0; + + /* Returns negative value when pin is configured as PORT */ + return thb_read_gpio_data(chip, offset, gpio_dir); + } + return -EINVAL; +} + +static int thunderbay_gpiochip_probe(struct thunderbay_pinctrl *tpc) +{ + struct gpio_chip *chip = &tpc->chip; + int ret; + + chip->label = dev_name(tpc->dev); + chip->parent = tpc->dev; + chip->request = gpiochip_generic_request; + chip->free = gpiochip_generic_free; + chip->get_direction = thunderbay_gpio_get_direction; + chip->direction_input = thunderbay_gpio_set_direction_input; + chip->direction_output = thunderbay_gpio_set_direction_output; + chip->get = thunderbay_gpio_get_value; + chip->set = thunderbay_gpio_set_value; + chip->set_config = gpiochip_generic_config; + /* identifies the first GPIO number handled by this chip; or, + * if negative during registration, requests dynamic ID allocation. + * Please pass -1 as base to let gpiolib select the chip base in all possible cases. + * We want to get rid of the static GPIO number space in the long run. + */ + chip->base = -1; + /* Number of GPIOs handled by this controller; the last GPIO handled is (base + ngpio - 1)*/ + chip->ngpio = THB_MAX_NPINS_SUPPORTED; + + /* Register/add Thunder Bay GPIO chip with Linux framework */ + ret = gpiochip_add_data(chip, tpc); + if (ret) + dev_err(tpc->dev, "Failed to add gpiochip\n"); + return ret; +} + +static int thunderbay_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &tpc->chip; + u32 reg = 0; + + if (thb_pinx_status[pin] == 0u) { + reg = thb_gpio_read_reg(chip, pin); + /* Updates PIN configuration as GPIO and sets GPIO to MODE-4*/ + reg |= (THB_GPIO_PORT_SELECT_MASK | THB_GPIO_PINMUX_MODE_4); + thb_gpio_write_reg(chip, pin, reg); + + /* update pin status as busy */ + thb_pinx_status[pin] = 1u; + + return 0; + } + return -EINVAL; +} + +static void thunderbay_free_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &tpc->chip; + u32 reg = 0; + + if (thb_pinx_status[pin] == 1u) { + reg = thb_gpio_read_reg(chip, pin); + + /* Updates PIN configuration from GPIO to PORT */ + reg &= (~THB_GPIO_PORT_SELECT_MASK); + + /* Change Port/gpio mode to default mode-0 */ + reg &= (~THB_GPIO_PINMUX_MODE_4); + + thb_gpio_write_reg(chip, pin, reg); + + /* update pin status as free */ + thb_pinx_status[pin] = 0u; + } +} + +static int thb_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_select, unsigned int group_select) +{ + struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &tpc->chip; + struct function_desc *function; + unsigned int i, pin_mode; + struct group_desc *group; + int ret = -EINVAL; + u32 reg = 0u; + + group = pinctrl_generic_get_group(pctldev, group_select); + if (!group) + return -EINVAL; + + function = pinmux_generic_get_function(pctldev, func_select); + if (!function) + return -EINVAL; + + pin_mode = *(unsigned int *)(function->data); + + /* Change modes for pins in the selected group */ + for (i = 0; i < group->num_pins; i++) { + reg = thb_gpio_read_reg(chip, group->pins[i]); + + switch (pin_mode) { + case 0u: + reg |= THB_GPIO_PINMUX_MODE_0; + break; + case 1u: + reg |= THB_GPIO_PINMUX_MODE_1; + break; + case 2u: + reg |= THB_GPIO_PINMUX_MODE_2; + break; + case 3u: + reg |= THB_GPIO_PINMUX_MODE_3; + break; + case 4u: + reg |= THB_GPIO_PINMUX_MODE_4; + break; + default: + return -EINVAL; + } + + ret = thb_gpio_write_reg(chip, group->pins[i], reg); + if (~ret) { + /* update pin status as busy */ + thb_pinx_status[group->pins[i]] = 1u; + } + } + return ret; +} + +static int thunderbay_build_groups(struct thunderbay_pinctrl *tpc) +{ + struct group_desc *thunderbay_groups; + int i; + + tpc->ngroups = tpc->soc->npins; + thunderbay_groups = devm_kcalloc(tpc->dev, tpc->ngroups, + sizeof(*thunderbay_groups), GFP_KERNEL); + if (!thunderbay_groups) + return -ENOMEM; + + for (i = 0; i < tpc->ngroups; i++) { + struct group_desc *group = thunderbay_groups + i; + const struct pinctrl_pin_desc *pin_info = thunderbay_pins + i; + + group->name = pin_info->name; + group->pins = (int *)&pin_info->number; + pinctrl_generic_add_group(tpc->pctrl, group->name, + group->pins, 1, NULL); + } + return 0; +} + +static int thunderbay_add_functions(struct thunderbay_pinctrl *tpc, struct function_desc *funcs) +{ + struct function_desc *function = funcs; + int i; + + /* Assign the groups for each function */ + for (i = 0; i < tpc->soc->npins; i++) { + const struct pinctrl_pin_desc *pin_info = thunderbay_pins + i; + struct thunderbay_mux_desc *pin_mux = pin_info->drv_data; + + while (pin_mux->name) { + const char **grp; + int j, grp_num, match = 0; + size_t grp_size; + struct function_desc *func; + + for (j = 0; j < tpc->nfuncs; j++) { + if (!strcmp(pin_mux->name, function[j].name)) { + match = 1; + break; + } + } + + if (!match) + return -EINVAL; + + func = function + j; + grp_num = func->num_group_names; + grp_size = sizeof(*func->group_names); + + if (!func->group_names) { + func->group_names = devm_kcalloc(tpc->dev, + grp_num, + grp_size, + GFP_KERNEL); + if (!func->group_names) { + kfree(func); + return -ENOMEM; + } + } + + grp = func->group_names; + while (*grp) + grp++; + + *grp = pin_info->name; + pin_mux++; + } + } + + /* Add all functions */ + for (i = 0; i < tpc->nfuncs; i++) { + pinmux_generic_add_function(tpc->pctrl, + function[i].name, + function[i].group_names, + function[i].num_group_names, + function[i].data); + } + kfree(function); + return 0; +} + +static int thunderbay_build_functions(struct thunderbay_pinctrl *tpc) +{ + struct function_desc *thunderbay_funcs; + void *ptr; + int pin; + + /* Total number of functions is unknown at this point. Allocate first. */ + tpc->nfuncs = 0; + thunderbay_funcs = kcalloc(tpc->soc->npins * 8, + sizeof(*thunderbay_funcs), GFP_KERNEL); + if (!thunderbay_funcs) + return -ENOMEM; + + /* Find total number of functions and each's properties */ + for (pin = 0; pin < tpc->soc->npins; pin++) { + const struct pinctrl_pin_desc *pin_info = thunderbay_pins + pin; + struct thunderbay_mux_desc *pin_mux = pin_info->drv_data; + + while (pin_mux->name) { + struct function_desc *func = thunderbay_funcs; + + while (func->name) { + if (!strcmp(pin_mux->name, func->name)) { + func->num_group_names++; + break; + } + func++; + } + + if (!func->name) { + func->name = pin_mux->name; + func->num_group_names = 1; + func->data = (int *)&pin_mux->mode; + tpc->nfuncs++; + } + + pin_mux++; + } + } + + /* Reallocate memory based on actual number of functions */ + ptr = krealloc(thunderbay_funcs, + tpc->nfuncs * sizeof(*thunderbay_funcs), GFP_KERNEL); + if (!ptr) + return -ENOMEM; + + thunderbay_funcs = ptr; + return thunderbay_add_functions(tpc, thunderbay_funcs); +} + +static int thunderbay_pinconf_set_tristate(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg |= THB_GPIO_ENAQ_MASK; + else + reg &= ~THB_GPIO_ENAQ_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_tristate(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = (reg & THB_GPIO_ENAQ_MASK) > 0; + + return 0; +} + +static int thunderbay_pinconf_set_pulldown(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg |= THB_GPIO_PULL_DOWN_MASK; + else + reg &= ~THB_GPIO_PULL_DOWN_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_pulldown(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg = 0; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_PULL_DOWN_MASK) > 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_set_pullup(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg &= ~THB_GPIO_PULL_UP_MASK; + else + reg |= THB_GPIO_PULL_UP_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_pullup(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_PULL_UP_MASK) == 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_set_opendrain(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg &= ~THB_GPIO_PULL_ENABLE_MASK; + else + reg |= THB_GPIO_PULL_ENABLE_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_opendrain(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_PULL_ENABLE_MASK) == 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_set_pushpull(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg |= THB_GPIO_PULL_ENABLE_MASK; + else + reg &= ~THB_GPIO_PULL_ENABLE_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_pushpull(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_PULL_ENABLE_MASK) > 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_set_drivestrength(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + + /* Drive Strength: 0x0 to 0xF */ + if (config <= 0xF) { + reg = (reg | config); + return thb_gpio_write_reg(chip, pin, reg); + } + + return -EINVAL; +} + +static int thunderbay_pinconf_get_drivestrength(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + reg = (reg & THB_GPIO_DRIVE_STRENGTH_MASK) >> 16; + *config = (reg > 0) ? reg : 0; + + return 0; +} + +static int thunderbay_pinconf_set_schmitt(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg |= THB_GPIO_SCHMITT_TRIGGER_MASK; + else + reg &= ~THB_GPIO_SCHMITT_TRIGGER_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_schmitt(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_SCHMITT_TRIGGER_MASK) > 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_set_slew_rate(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg = 0; + + reg = thb_gpio_read_reg(chip, pin); + if (config > 0) + reg |= THB_GPIO_SLEW_RATE_MASK; + else + reg &= ~THB_GPIO_SLEW_RATE_MASK; + + return thb_gpio_write_reg(chip, pin, reg); +} + +static int thunderbay_pinconf_get_slew_rate(struct thunderbay_pinctrl *tpc, + unsigned int pin, u32 *config) +{ + struct gpio_chip *chip = &tpc->chip; + u32 reg; + + reg = thb_gpio_read_reg(chip, pin); + *config = ((reg & THB_GPIO_SLEW_RATE_MASK) > 0) ? 1 : 0; + + return 0; +} + +static int thunderbay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + ret = thunderbay_pinconf_get_tristate(tpc, pin, &arg); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = thunderbay_pinconf_get_pulldown(tpc, pin, &arg); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = thunderbay_pinconf_get_pullup(tpc, pin, &arg); + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + ret = thunderbay_pinconf_get_opendrain(tpc, pin, &arg); + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + ret = thunderbay_pinconf_get_pushpull(tpc, pin, &arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = thunderbay_pinconf_get_drivestrength(tpc, pin, &arg); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + ret = thunderbay_pinconf_get_schmitt(tpc, pin, &arg); + break; + + case PIN_CONFIG_SLEW_RATE: + ret = thunderbay_pinconf_get_slew_rate(tpc, pin, &arg); + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return ret; +} + +static int thunderbay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + unsigned int pinconf; + int ret = 0; + u32 arg; + + for (pinconf = 0; pinconf < num_configs; pinconf++) { + param = pinconf_to_config_param(configs[pinconf]); + arg = pinconf_to_config_argument(configs[pinconf]); + + switch (param) { + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + ret = thunderbay_pinconf_set_tristate(tpc, pin, arg); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = thunderbay_pinconf_set_pulldown(tpc, pin, arg); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + ret = thunderbay_pinconf_set_pullup(tpc, pin, arg); + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + ret = thunderbay_pinconf_set_opendrain(tpc, pin, arg); + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + ret = thunderbay_pinconf_set_pushpull(tpc, pin, arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = thunderbay_pinconf_set_drivestrength(tpc, pin, arg); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + ret = thunderbay_pinconf_set_schmitt(tpc, pin, arg); + break; + + case PIN_CONFIG_SLEW_RATE: + ret = thunderbay_pinconf_set_slew_rate(tpc, pin, arg); + break; + + default: + return -ENOTSUPP; + } + } + return ret; +} + +static const struct pinctrl_ops thunderbay_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static const struct pinmux_ops thunderbay_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = thb_pinctrl_set_mux, + .gpio_request_enable = thunderbay_request_gpio, + .gpio_disable_free = thunderbay_free_gpio, +}; + +static const struct pinconf_ops thunderbay_confops = { + .is_generic = true, + .pin_config_get = thunderbay_pinconf_get, + .pin_config_set = thunderbay_pinconf_set, +}; + +static struct pinctrl_desc thunderbay_pinctrl_desc = { + .name = "thunderbay-pinmux", + .pctlops = &thunderbay_pctlops, + .pmxops = &thunderbay_pmxops, + .confops = &thunderbay_confops, + .owner = THIS_MODULE, +}; + +static const struct of_device_id thunderbay_pinctrl_match[] = { + { + .compatible = "intel,thunderbay-pinctrl", + .data = &thunderbay_data + }, + {} +}; + +static int thunderbay_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct device *dev = &pdev->dev; + struct thunderbay_pinctrl *tpc; + struct resource *iomem; + int ret; + + of_id = of_match_node(thunderbay_pinctrl_match, pdev->dev.of_node); + if (!of_id) + return -ENODEV; + + tpc = devm_kzalloc(dev, sizeof(*tpc), GFP_KERNEL); + if (!tpc) + return -ENOMEM; + + tpc->dev = dev; + tpc->soc = of_id->data; + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!iomem) + return -ENXIO; + + tpc->base0 = devm_ioremap_resource(dev, iomem); + if (IS_ERR(tpc->base0)) + return PTR_ERR(tpc->base0); + + thunderbay_pinctrl_desc.pins = tpc->soc->pins; + thunderbay_pinctrl_desc.npins = tpc->soc->npins; + + /* Register pinctrl */ + tpc->pctrl = devm_pinctrl_register(dev, &thunderbay_pinctrl_desc, tpc); + if (IS_ERR(tpc->pctrl)) + return PTR_ERR(tpc->pctrl); + + /* Setup pinmux groups */ + ret = thunderbay_build_groups(tpc); + if (ret) + return ret; + + /* Setup pinmux functions */ + ret = thunderbay_build_functions(tpc); + if (ret) + return ret; + + /* Setup GPIO */ + ret = thunderbay_gpiochip_probe(tpc); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, tpc); + + return 0; +} + +static int thunderbay_pinctrl_remove(struct platform_device *pdev) +{ + /* thunderbay_pinctrl_remove function to clear the assigned memory */ + return 0; +} + +static struct platform_driver thunderbay_pinctrl_driver = { + .driver = { + .name = "thunderbay-pinctrl", + .of_match_table = thunderbay_pinctrl_match, + }, + .probe = thunderbay_pinctrl_probe, + .remove = thunderbay_pinctrl_remove, +}; + +builtin_platform_driver(thunderbay_pinctrl_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Kiran Kumar S "); +MODULE_DESCRIPTION("Intel Thunder Bay Pinctrl/GPIO Driver"); +MODULE_LICENSE("GPL v2"); From b124c8bd50c7550ed966c09f69ffdbaaedc0aa15 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 9 Dec 2021 13:34:56 +0200 Subject: [PATCH 81/98] pinctrl: Sort Kconfig and Makefile entries alphabetically Sort Kconfig and Makefile entries alphabetically for better maintenance in the future. While at it fix some style issues, such as: - "Say Y"/"Say yes"/"Say Yes" --> "Say Y" - "pullup/pulldown" --> "pull-up and pull-down" - wrong indentation Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 521 +++++++++++++++++++-------------------- drivers/pinctrl/Makefile | 49 ++-- 2 files changed, 285 insertions(+), 285 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a3457a4b4d9d..c27c9ee89f0e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -31,6 +31,24 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. +config PINCTRL_AMD + tristate "AMD GPIO pin control" + depends on HAS_IOMEM + depends on ACPI || COMPILE_TEST + select GPIOLIB + select GPIOLIB_IRQCHIP + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + The driver for memory mapped GPIO functionality on AMD platforms + (x86 or arm). Most of the pins are usually muxed to some other + functionality by firmware, so only a small amount is available + for GPIO use. + + Requires ACPI/FDT device enumeration code to set up a platform + device. + config PINCTRL_APPLE_GPIO tristate "Apple SoC GPIO pin controller driver" depends on ARCH_APPLE @@ -69,20 +87,6 @@ config PINCTRL_AS3722 open drain configuration for the GPIO pins of AS3722 devices. It also supports the GPIO functionality through gpiolib. -config PINCTRL_AXP209 - tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" - depends on MFD_AXP20X - depends on OF - select PINMUX - select GENERIC_PINCONF - select GPIOLIB - help - AXP PMICs provides multiple GPIOs that can be muxed for different - functions. This driver bundles a pinctrl driver to select the function - muxing and a GPIO driver to handle the GPIO when the GPIO function is - selected. - Say yes to enable pinctrl and GPIO support for the AXP209 PMIC - config PINCTRL_AT91 bool "AT91 pinctrl driver" depends on OF @@ -109,23 +113,19 @@ config PINCTRL_AT91PIO4 Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 controller available on sama5d2 SoC. -config PINCTRL_AMD - tristate "AMD GPIO pin control" - depends on HAS_IOMEM - depends on ACPI || COMPILE_TEST - select GPIOLIB - select GPIOLIB_IRQCHIP +config PINCTRL_AXP209 + tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" + depends on MFD_AXP20X + depends on OF select PINMUX - select PINCONF select GENERIC_PINCONF + select GPIOLIB help - driver for memory mapped GPIO functionality on AMD platforms - (x86 or arm).Most pins are usually muxed to some other - functionality by firmware,so only a small amount is available - for gpio use. - - Requires ACPI/FDT device enumeration code to set up a platform - device. + AXP PMICs provides multiple GPIOs that can be muxed for different + functions. This driver bundles a pinctrl driver to select the function + muxing and a GPIO driver to handle the GPIO when the GPIO function is + selected. + Say Y to enable pinctrl and GPIO support for the AXP209 PMIC. config PINCTRL_BM1880 bool "Bitmain BM1880 Pinctrl driver" @@ -136,13 +136,13 @@ config PINCTRL_BM1880 Pinctrl driver for Bitmain BM1880 SoC. config PINCTRL_DA850_PUPD - tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups" + tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups" depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST) select PINCONF select GENERIC_PINCONF help Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control - pullup/pulldown pin groups. + pull-up and pull-down pin groups. config PINCTRL_DA9062 tristate "Dialog Semiconductor DA9062 PMIC pinctrl and GPIO Support" @@ -154,7 +154,7 @@ config PINCTRL_DA9062 function muxing and a GPIO driver to handle the GPIO when the GPIO function is selected. - Say yes to enable pinctrl and GPIO support for the DA9062 PMIC. + Say Y to enable pinctrl and GPIO support for the DA9062 PMIC. config PINCTRL_DIGICOLOR bool @@ -162,12 +162,93 @@ config PINCTRL_DIGICOLOR select PINMUX select GENERIC_PINCONF +config PINCTRL_EQUILIBRIUM + tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC" + depends on OF && HAS_IOMEM + depends on X86 || COMPILE_TEST + select PINMUX + select PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + help + Equilibrium driver is a pinctrl and GPIO driver for Intel Lightning + Mountain network processor SoC that supports both the GPIO and pin + control frameworks. It provides interfaces to setup pin muxing, assign + desired pin functions, configure GPIO attributes for LGM SoC pins. + Pin muxing and pin config settings are retrieved from device tree. + +config PINCTRL_GEMINI + bool + depends on ARCH_GEMINI + default ARCH_GEMINI + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + +config PINCTRL_INGENIC + bool "Pinctrl driver for the Ingenic JZ47xx SoCs" + default MACH_INGENIC + depends on OF + depends on MIPS || COMPILE_TEST + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP_MMIO + +config PINCTRL_K210 + bool "Pinctrl driver for the Canaan Kendryte K210 SoC" + depends on RISCV && SOC_CANAAN && OF + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select GPIOLIB + select OF_GPIO + select REGMAP_MMIO + default SOC_CANAAN + help + Add support for the Canaan Kendryte K210 RISC-V SOC Field + Programmable IO Array (FPIOA) controller. + +config PINCTRL_KEEMBAY + tristate "Pinctrl driver for Intel Keem Bay SoC" + depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST) + depends on HAS_IOMEM + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_GENERIC + help + This selects pin control driver for the Intel Keem Bay SoC. + It provides pin config functions such as pull-up, pull-down, + interrupt, drive strength, sec lock, Schmitt trigger, slew + rate control and direction control. This module will be + called as pinctrl-keembay. + config PINCTRL_LANTIQ bool depends on LANTIQ select PINMUX select PINCONF +config PINCTRL_FALCON + bool + depends on SOC_FALCON + depends on PINCTRL_LANTIQ + +config PINCTRL_XWAY + bool + depends on SOC_TYPE_XWAY + depends on PINCTRL_LANTIQ + config PINCTRL_LPC18XX bool "NXP LPC18XX/43XX SCU pinctrl driver" depends on OF && (ARCH_LPC18XX || COMPILE_TEST) @@ -177,18 +258,16 @@ config PINCTRL_LPC18XX help Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU). -config PINCTRL_FALCON - bool - depends on SOC_FALCON - depends on PINCTRL_LANTIQ - -config PINCTRL_GEMINI - bool - depends on ARCH_GEMINI - default ARCH_GEMINI +config PINCTRL_MAX77620 + tristate "MAX77620/MAX20024 Pincontrol support" + depends on MFD_MAX77620 && OF select PINMUX select GENERIC_PINCONF - select MFD_SYSCON + help + Say Y here to enable Pin control support for Maxim MAX77620 PMIC. + This PMIC has 8 GPIO pins that work as GPIO as well as special + function in alternate mode. This driver also configure push-pull, + open drain, FPS slots etc. config PINCTRL_MCP23S08_I2C tristate @@ -212,6 +291,37 @@ config PINCTRL_MCP23S08 This provides a GPIO interface supporting inputs and outputs and a corresponding interrupt-controller. +config PINCTRL_MICROCHIP_SGPIO + bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + depends on OF + depends on HAS_IOMEM + select GPIOLIB + select GPIOLIB_IRQCHIP + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select OF_GPIO + help + Support for the serial GPIO interface used on Microsemi and + Microchip SoCs. By using a serial interface, the SIO + controller significantly extends the number of available + GPIOs with a minimum number of additional pins on the + device. The primary purpose of the SIO controller is to + connect control signals from SFP modules and to act as an + LED controller. + +config PINCTRL_OCELOT + bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs" + depends on OF + depends on HAS_IOMEM + select GPIOLIB + select GPIOLIB_IRQCHIP + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select OF_GPIO + select REGMAP_MMIO + config PINCTRL_OXNAS bool depends on OF @@ -223,89 +333,6 @@ config PINCTRL_OXNAS select GPIOLIB_IRQCHIP select MFD_SYSCON -config PINCTRL_ROCKCHIP - tristate "Rockchip gpio and pinctrl driver" - depends on ARCH_ROCKCHIP || COMPILE_TEST - depends on OF - select GPIOLIB - select PINMUX - select GENERIC_PINCONF - select GENERIC_IRQ_CHIP - select MFD_SYSCON - select OF_GPIO - default ARCH_ROCKCHIP - help - This support pinctrl and gpio driver for Rockchip SoCs. - -config PINCTRL_SINGLE - tristate "One-register-per-pin type device tree based pinctrl driver" - depends on OF - depends on HAS_IOMEM - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects the device tree based generic pinctrl driver. - -config PINCTRL_SX150X - bool "Semtech SX150x I2C GPIO expander pinctrl driver" - depends on I2C=y - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select GPIOLIB_IRQCHIP - select REGMAP - help - Say yes here to provide support for Semtech SX150x-series I2C - GPIO expanders as pinctrl module. - Compatible models include: - - 8 bits: sx1508q, sx1502q - - 16 bits: sx1509q, sx1506q - -config PINCTRL_PISTACHIO - bool "IMG Pistachio SoC pinctrl driver" - depends on OF && (MIPS || COMPILE_TEST) - depends on GPIOLIB - select PINMUX - select GENERIC_PINCONF - select GPIOLIB_IRQCHIP - select OF_GPIO - help - This support pinctrl and gpio driver for IMG Pistachio SoC. - -config PINCTRL_ST - bool - depends on OF - select PINMUX - select PINCONF - select GPIOLIB_IRQCHIP - -config PINCTRL_STMFX - tristate "STMicroelectronics STMFX GPIO expander pinctrl driver" - depends on I2C - depends on OF_GPIO - select GENERIC_PINCONF - select GPIOLIB_IRQCHIP - select MFD_STMFX - help - Driver for STMicroelectronics Multi-Function eXpander (STMFX) - GPIO expander. - This provides a GPIO interface supporting inputs and outputs, - and configuring push-pull, open-drain, and can also be used as - interrupt-controller. - -config PINCTRL_MAX77620 - tristate "MAX77620/MAX20024 Pincontrol support" - depends on MFD_MAX77620 && OF - select PINMUX - select GENERIC_PINCONF - help - Say Yes here to enable Pin control support for Maxim PMIC MAX77620. - This PMIC has 8 GPIO pins that work as GPIO as well as special - function in alternate mode. This driver also configure push-pull, - open drain, FPS slots etc. - config PINCTRL_PALMAS tristate "Pinctrl driver for the PALMAS Series MFD devices" depends on OF && MFD_PALMAS @@ -334,6 +361,111 @@ config PINCTRL_PIC32MZDA def_bool y if PIC32MZDA select PINCTRL_PIC32 +config PINCTRL_PISTACHIO + bool "IMG Pistachio SoC pinctrl driver" + depends on OF && (MIPS || COMPILE_TEST) + depends on GPIOLIB + select PINMUX + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + select OF_GPIO + help + This support pinctrl and GPIO driver for IMG Pistachio SoC. + +config PINCTRL_RK805 + tristate "Pinctrl and GPIO driver for RK805 PMIC" + depends on MFD_RK808 + select GPIOLIB + select PINMUX + select GENERIC_PINCONF + help + This selects the pinctrl driver for RK805. + +config PINCTRL_ROCKCHIP + tristate "Rockchip gpio and pinctrl driver" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + select GPIOLIB + select PINMUX + select GENERIC_PINCONF + select GENERIC_IRQ_CHIP + select MFD_SYSCON + select OF_GPIO + default ARCH_ROCKCHIP + help + This support pinctrl and GPIO driver for Rockchip SoCs. + +config PINCTRL_SINGLE + tristate "One-register-per-pin type device tree based pinctrl driver" + depends on OF + depends on HAS_IOMEM + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects the device tree based generic pinctrl driver. + +config PINCTRL_ST + bool + depends on OF + select PINMUX + select PINCONF + select GPIOLIB_IRQCHIP + +config PINCTRL_STMFX + tristate "STMicroelectronics STMFX GPIO expander pinctrl driver" + depends on I2C + depends on OF_GPIO + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + select MFD_STMFX + help + Driver for STMicroelectronics Multi-Function eXpander (STMFX) + GPIO expander. + This provides a GPIO interface supporting inputs and outputs, + and configuring push-pull, open-drain, and can also be used as + interrupt-controller. + +config PINCTRL_SX150X + bool "Semtech SX150x I2C GPIO expander pinctrl driver" + depends on I2C=y + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP + help + Say Y here to provide support for Semtech SX150x-series I2C + GPIO expanders as pinctrl module. + Compatible models include: + - 8 bits: sx1508q, sx1502q + - 16 bits: sx1509q, sx1506q + +config PINCTRL_TB10X + bool + depends on OF && ARC_PLAT_TB10X + select GPIOLIB + +config PINCTRL_THUNDERBAY + tristate "Generic pinctrl and GPIO driver for Intel Thunder Bay SoC" + depends on ARCH_THUNDERBAY || (ARM64 && COMPILE_TEST) + depends on HAS_IOMEM + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_GENERIC + help + This selects pin control driver for the Intel Thunder Bay SoC. + It provides pin config functions such as pull-up, pull-down, + interrupt, drive strength, sec lock, Schmitt trigger, slew + rate control and direction control. This module will be + called as pinctrl-thunderbay. + config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" depends on ARCH_ZYNQ @@ -358,96 +490,15 @@ config PINCTRL_ZYNQMP This driver can also be built as a module. If so, the module will be called pinctrl-zynqmp. -config PINCTRL_INGENIC - bool "Pinctrl driver for the Ingenic JZ47xx SoCs" - default MACH_INGENIC - depends on OF - depends on MIPS || COMPILE_TEST - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GPIOLIB - select GPIOLIB_IRQCHIP - select REGMAP_MMIO - -config PINCTRL_RK805 - tristate "Pinctrl and GPIO driver for RK805 PMIC" - depends on MFD_RK808 - select GPIOLIB - select PINMUX - select GENERIC_PINCONF - help - This selects the pinctrl driver for RK805. - -config PINCTRL_OCELOT - bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs" - depends on OF - depends on HAS_IOMEM - select GPIOLIB - select GPIOLIB_IRQCHIP - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select OF_GPIO - select REGMAP_MMIO - -config PINCTRL_MICROCHIP_SGPIO - bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" - depends on OF - depends on HAS_IOMEM - select GPIOLIB - select GPIOLIB_IRQCHIP - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select OF_GPIO - help - Support for the serial GPIO interface used on Microsemi and - Microchip SoC's. By using a serial interface, the SIO - controller significantly extends the number of available - GPIOs with a minimum number of additional pins on the - device. The primary purpose of the SIO controller is to - connect control signals from SFP modules and to act as an - LED controller. - -config PINCTRL_K210 - bool "Pinctrl driver for the Canaan Kendryte K210 SoC" - depends on RISCV && SOC_CANAAN && OF - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - select GPIOLIB - select OF_GPIO - select REGMAP_MMIO - default SOC_CANAAN - help - Add support for the Canaan Kendryte K210 RISC-V SOC Field - Programmable IO Array (FPIOA) controller. - -config PINCTRL_KEEMBAY - tristate "Pinctrl driver for Intel Keem Bay SoC" - depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST) - depends on HAS_IOMEM - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GPIOLIB - select GPIOLIB_IRQCHIP - select GPIO_GENERIC - help - This selects pin control driver for the Intel Keembay SoC. - It provides pin config functions such as pullup, pulldown, - interrupt, drive strength, sec lock, schmitt trigger, slew - rate control and direction control. This module will be - called as pinctrl-keembay. - source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" +source "drivers/pinctrl/cirrus/Kconfig" source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" +source "drivers/pinctrl/mediatek/Kconfig" +source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" @@ -463,59 +514,7 @@ source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" -source "drivers/pinctrl/vt8500/Kconfig" -source "drivers/pinctrl/mediatek/Kconfig" -source "drivers/pinctrl/meson/Kconfig" -source "drivers/pinctrl/cirrus/Kconfig" source "drivers/pinctrl/visconti/Kconfig" - -config PINCTRL_XWAY - bool - depends on SOC_TYPE_XWAY - depends on PINCTRL_LANTIQ - -config PINCTRL_TB10X - bool - depends on OF && ARC_PLAT_TB10X - select GPIOLIB - -config PINCTRL_EQUILIBRIUM - tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC" - depends on OF && HAS_IOMEM - depends on X86 || COMPILE_TEST - select PINMUX - select PINCONF - select GPIOLIB - select GPIO_GENERIC - select GPIOLIB_IRQCHIP - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - - help - Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel Lightning - Mountain network processor SoC that supports both the linux GPIO and pin - control frameworks. It provides interfaces to setup pinmux, assign desired - pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and - pinconf settings are retrieved from device tree. - -config PINCTRL_THUNDERBAY - tristate "Generic pinctrl and GPIO driver for Intel Thunder Bay SoC" - depends on ARCH_THUNDERBAY || (ARM64 && COMPILE_TEST) - depends on HAS_IOMEM - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GPIOLIB - select GPIOLIB_IRQCHIP - select GPIO_GENERIC - help - This selects pin control driver for the Intel Thunder Bay SoC. - It provides pin config functions such as pullup, pulldown, - interrupt, drive strength, sec lock, schmitt trigger, slew - rate control and direction control. This module will be - called as pinctrl-thunderbay. +source "drivers/pinctrl/vt8500/Kconfig" endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0d5744e7f8fb..6be6c3fc6663 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -6,57 +6,59 @@ subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG obj-y += core.o pinctrl-utils.o obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o -obj-$(CONFIG_OF) += devicetree.o obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o +obj-$(CONFIG_OF) += devicetree.o + +obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o -obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o -obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o +obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o -obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o +obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o +obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o +obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o +obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o +obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o +obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o +obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o +obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o -obj-$(CONFIG_PINCTRL_MESON) += meson/ +obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o +obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o -obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o -obj-$(CONFIG_ARCH_TEGRA) += tegra/ -obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o -obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o -obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o -obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o -obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o -obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o -obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o -obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o -obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o -obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o -obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o -obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o -obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o -obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o +obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o +obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o +obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o +obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ +obj-y += cirrus/ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ +obj-y += mediatek/ +obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-y += mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ @@ -69,9 +71,8 @@ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ -obj-$(CONFIG_ARCH_VT8500) += vt8500/ -obj-y += mediatek/ -obj-y += cirrus/ obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ +obj-$(CONFIG_ARCH_VT8500) += vt8500/ From dc1b242478f47d04a41f319a14f163711c52646a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Dec 2021 14:45:13 +0100 Subject: [PATCH 82/98] pinctrl: bcm2835: Silence uninit warning The uninitialized variable would be caught by the BUG_ON() logic below, but the kernel test robot cannot see that. Silence the warning by initializing the variable. Reported-by: kernel test robot Link: https://lore.kernel.org/r/20211209134513.306212-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 2abcc6ce4eba..e473fc1509d3 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -407,7 +407,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); struct irq_chip *host_chip = irq_desc_get_chip(desc); int irq = irq_desc_get_irq(desc); - int group; + int group = 0; int i; for (i = 0; i < BCM2835_NUM_IRQS; i++) { From 1a4541b68e250bc4b21bd4c6178877523c5d896b Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 6 Dec 2021 14:16:47 +0100 Subject: [PATCH 83/98] pinctrl-bcm2835: don't call pinctrl_gpio_direction() Set the direction directly without calling pinctrl_gpio_direction(). This avoids the mutex_lock() calls in that function, which would invalid the can_sleep = false. Signed-off-by: Hans Verkuil Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20211206131648.1521868-3-hverkuil-cisco@xs4all.nl Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index e473fc1509d3..d8cacdaf1476 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -313,7 +313,10 @@ static inline void bcm2835_pinctrl_fsel_set( static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - return pinctrl_gpio_direction_input(chip->base + offset); + struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); + + bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); + return 0; } static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -348,8 +351,11 @@ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int bcm2835_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - bcm2835_gpio_set(chip, offset, value); - return pinctrl_gpio_direction_output(chip->base + offset); + struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); + + bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); + bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT); + return 0; } static const struct gpio_chip bcm2835_gpio_chip = { From 8df89a7cbc63c7598c00611ad17b67e8d5b4fad3 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 6 Dec 2021 14:16:48 +0100 Subject: [PATCH 84/98] pinctrl-sunxi: don't call pinctrl_gpio_direction() Set the direction directly without calling pinctrl_gpio_direction(). This avoids the mutex_lock() calls in that function, which would invalid the can_sleep = false. Signed-off-by: Hans Verkuil Link: https://lore.kernel.org/r/20211206131648.1521868-4-hverkuil-cisco@xs4all.nl Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 862c84efb718..80d6750c74a6 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -835,7 +835,9 @@ static const struct pinmux_ops sunxi_pmx_ops = { static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - return pinctrl_gpio_direction_input(chip->base + offset); + struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); + + return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, true); } static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -885,8 +887,10 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { + struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); + sunxi_pinctrl_gpio_set(chip, offset, value); - return pinctrl_gpio_direction_output(chip->base + offset); + return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, false); } static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, From 8a8d6bbe1d3bc7137c777ba06246d7e9c08dde4d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 14 Dec 2021 14:58:54 +0200 Subject: [PATCH 85/98] pinctrl: Get rid of duplicate of_node assignment in the drivers GPIO library does copy the of_node from the parent device of the GPIO chip, there is no need to repeat this in the individual drivers. Remove these assignment all at once. For the details one may look into the of_gpio_dev_init() implementation. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20211214125855.33207-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-owl.c | 1 - drivers/pinctrl/bcm/pinctrl-bcm2835.c | 1 - drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 1 - drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 1 - drivers/pinctrl/cirrus/pinctrl-lochnagar.c | 3 --- drivers/pinctrl/mediatek/pinctrl-moore.c | 7 +++---- drivers/pinctrl/mediatek/pinctrl-paris.c | 5 ++--- drivers/pinctrl/pinctrl-amd.c | 3 --- drivers/pinctrl/pinctrl-at91-pio4.c | 1 - drivers/pinctrl/pinctrl-at91.c | 1 - drivers/pinctrl/pinctrl-digicolor.c | 5 ++--- drivers/pinctrl/pinctrl-mcp23s08.c | 1 - drivers/pinctrl/pinctrl-ocelot.c | 1 - drivers/pinctrl/pinctrl-oxnas.c | 1 - drivers/pinctrl/pinctrl-pic32.c | 2 +- drivers/pinctrl/pinctrl-stmfx.c | 1 - drivers/pinctrl/pinctrl-sx150x.c | 3 --- drivers/pinctrl/pinctrl-xway.c | 1 - drivers/pinctrl/qcom/pinctrl-msm.c | 1 - drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 1 - drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 1 - drivers/pinctrl/renesas/pinctrl-rza2.c | 1 - drivers/pinctrl/spear/pinctrl-plgpio.c | 1 - drivers/pinctrl/vt8500/pinctrl-wmt.c | 1 - 24 files changed, 8 insertions(+), 37 deletions(-) diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 781f2200ed58..ed46abc15d72 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -874,7 +874,6 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->owner = THIS_MODULE; - chip->of_node = pctrl->dev->of_node; pctrl->irq_chip.name = chip->of_node->name; pctrl->irq_chip.irq_ack = owl_gpio_irq_ack; diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index d8cacdaf1476..ae8b6ad2ea51 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1228,7 +1228,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) pc->gpio_chip = *pdata->gpio_chip; pc->gpio_chip.parent = dev; - pc->gpio_chip.of_node = np; for (i = 0; i < BCM2835_NUM_BANKS; i++) { unsigned long events; diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index a7a0dd638a26..52fa2f4cd618 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -836,7 +836,6 @@ static int iproc_gpio_probe(struct platform_device *pdev) chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; gc->label = dev_name(dev); gc->parent = dev; - gc->of_node = dev->of_node; gc->request = iproc_gpio_request; gc->free = iproc_gpio_free; gc->direction_input = iproc_gpio_direction_input; diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index e03142895f61..643dbd315033 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -648,7 +648,6 @@ static int nsp_gpio_probe(struct platform_device *pdev) gc->ngpio = val; gc->label = dev_name(dev); gc->parent = dev; - gc->of_node = dev->of_node; gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; gc->direction_input = nsp_gpio_direction_input; diff --git a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c index 670ac53a3141..3fda4446d70b 100644 --- a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c +++ b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c @@ -1161,9 +1161,6 @@ static int lochnagar_pin_probe(struct platform_device *pdev) priv->gpio_chip.can_sleep = true; priv->gpio_chip.parent = dev; priv->gpio_chip.base = -1; -#ifdef CONFIG_OF_GPIO - priv->gpio_chip.of_node = dev->of_node; -#endif switch (lochnagar->type) { case LOCHNAGAR1: diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index ad3b67163973..5bfaa84839c7 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -519,7 +519,7 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); } -static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) +static int mtk_build_gpiochip(struct mtk_pinctrl *hw) { struct gpio_chip *chip = &hw->chip; int ret; @@ -536,7 +536,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) chip->set_config = mtk_gpio_set_config; chip->base = -1; chip->ngpio = hw->soc->npins; - chip->of_node = np; chip->of_gpio_n_cells = 2; ret = gpiochip_add_data(chip, hw); @@ -550,7 +549,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) * Documentation/devicetree/bindings/gpio/gpio.txt on how to * bind pinctrl and gpio drivers via the "gpio-ranges" property. */ - if (!of_find_property(np, "gpio-ranges", NULL)) { + if (!of_find_property(hw->dev->of_node, "gpio-ranges", NULL)) { ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, chip->ngpio); if (ret < 0) { @@ -691,7 +690,7 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, "Failed to add EINT, but pinctrl still can work\n"); /* Build gpiochip should be after pinctrl_enable is done */ - err = mtk_build_gpiochip(hw, pdev->dev.of_node); + err = mtk_build_gpiochip(hw); if (err) { dev_err(&pdev->dev, "Failed to add gpio_chip\n"); return err; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 4c6f6d967b18..f9f9110f2107 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -895,7 +895,7 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce); } -static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) +static int mtk_build_gpiochip(struct mtk_pinctrl *hw) { struct gpio_chip *chip = &hw->chip; int ret; @@ -913,7 +913,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) chip->set_config = mtk_gpio_set_config; chip->base = -1; chip->ngpio = hw->soc->npins; - chip->of_node = np; chip->of_gpio_n_cells = 2; ret = gpiochip_add_data(chip, hw); @@ -1037,7 +1036,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, "Failed to add EINT, but pinctrl still can work\n"); /* Build gpiochip should be after pinctrl_enable is done */ - err = mtk_build_gpiochip(hw, pdev->dev.of_node); + err = mtk_build_gpiochip(hw); if (err) { dev_err(&pdev->dev, "Failed to add gpio_chip\n"); return err; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index ecab9064a845..1a7d686494ff 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -1009,9 +1009,6 @@ static int amd_gpio_probe(struct platform_device *pdev) gpio_dev->gc.owner = THIS_MODULE; gpio_dev->gc.parent = &pdev->dev; gpio_dev->gc.ngpio = resource_size(res) / 4; -#if defined(CONFIG_OF_GPIO) - gpio_dev->gc.of_node = pdev->dev.of_node; -#endif gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; gpio_dev->groups = kerncz_groups; diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 03c32b2c5d30..fafd1f55cba7 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1136,7 +1136,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) } atmel_pioctrl->gpio_chip = &atmel_gpio_chip; - atmel_pioctrl->gpio_chip->of_node = dev->of_node; atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; atmel_pioctrl->gpio_chip->label = dev_name(dev); atmel_pioctrl->gpio_chip->parent = dev; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 6022496bb6a9..d91a010e65f5 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1868,7 +1868,6 @@ static int at91_gpio_probe(struct platform_device *pdev) at91_chip->chip = at91_gpio_template; chip = &at91_chip->chip; - chip->of_node = np; chip->label = dev_name(&pdev->dev); chip->parent = &pdev->dev; chip->owner = THIS_MODULE; diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index ff702cfbaa28..cc3546fc4610 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -233,7 +233,7 @@ static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) spin_unlock_irqrestore(&pmap->lock, flags); } -static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np) +static int dc_gpiochip_add(struct dc_pinmap *pmap) { struct gpio_chip *chip = &pmap->chip; int ret; @@ -248,7 +248,6 @@ static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np) chip->set = dc_gpio_set; chip->base = -1; chip->ngpio = PINS_COUNT; - chip->of_node = np; chip->of_gpio_n_cells = 2; spin_lock_init(&pmap->lock); @@ -326,7 +325,7 @@ static int dc_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(pmap->pctl); } - return dc_gpiochip_add(pmap, pdev->dev.of_node); + return dc_gpiochip_add(pmap); } static const struct of_device_id dc_pinctrl_ids[] = { diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index bccebe43dd6a..695236636d05 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -551,7 +551,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.set = mcp23s08_set; #ifdef CONFIG_OF_GPIO mcp->chip.of_gpio_n_cells = 2; - mcp->chip.of_node = dev->of_node; #endif mcp->chip.base = base; diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 42aab9ba049a..fc969208d904 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1748,7 +1748,6 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->ngpio = info->desc->npins; gc->parent = &pdev->dev; gc->base = -1; - gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; irq = irq_of_parse_and_map(gc->of_node, 0); diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index cebd810bd6d1..fb10a8473ebe 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -1232,7 +1232,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev) bank->id = id; bank->gpio_chip.parent = &pdev->dev; - bank->gpio_chip.of_node = np; bank->gpio_chip.ngpio = ngpios; girq = &bank->gpio_chip.irq; girq->chip = &bank->irq_chip; diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 748dabd8db6e..37acfdfc2cae 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2241,7 +2241,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) } bank->gpio_chip.parent = &pdev->dev; - bank->gpio_chip.of_node = np; + girq = &bank->gpio_chip.irq; girq->chip = &bank->irq_chip; girq->parent_handler = pic32_gpio_irq_handler; diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 5fa2488fae87..ab4dde40d3ed 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -675,7 +675,6 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->gpio_chip.base = -1; pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; pctl->gpio_chip.can_sleep = true; - pctl->gpio_chip.of_node = np; pctl->irq_chip.name = dev_name(pctl->dev); pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 484a3b9e875c..a87ea3b95cf4 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1163,9 +1163,6 @@ static int sx150x_probe(struct i2c_client *client, pctl->gpio.set = sx150x_gpio_set; pctl->gpio.set_config = gpiochip_generic_config; pctl->gpio.parent = dev; -#ifdef CONFIG_OF_GPIO - pctl->gpio.of_node = dev->of_node; -#endif pctl->gpio.can_sleep = true; pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); if (!pctl->gpio.label) diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index 5e3f31b55eb7..3a03beb8a755 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -1763,7 +1763,6 @@ static int pinmux_xway_probe(struct platform_device *pdev) /* register the gpio chip */ xway_chip.parent = &pdev->dev; xway_chip.owner = THIS_MODULE; - xway_chip.of_node = pdev->dev.of_node; ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL); if (ret) { dev_err(&pdev->dev, "Failed to register gpio chip\n"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ae09e2dd8a50..780878dede9e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1264,7 +1264,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->owner = THIS_MODULE; - chip->of_node = pctrl->dev->of_node; if (msm_gpio_needs_valid_mask(pctrl)) chip->init_valid_mask = msm_gpio_init_valid_mask; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index b5949f766a7a..1b41adda8129 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -773,7 +773,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) pctrl->chip = pm8xxx_gpio_template; pctrl->chip.base = -1; pctrl->chip.parent = &pdev->dev; - pctrl->chip.of_node = pdev->dev.of_node; pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.ngpio = pctrl->npins; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 842940594c4a..49893a5133a8 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -857,7 +857,6 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) pctrl->chip = pm8xxx_mpp_template; pctrl->chip.base = -1; pctrl->chip.parent = &pdev->dev; - pctrl->chip.of_node = pdev->dev.of_node; pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.ngpio = pctrl->npins; diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 32829eb9656c..c0a04f1ee994 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -240,7 +240,6 @@ static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) int ret; chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); - chip.of_node = np; chip.parent = priv->dev; chip.ngpio = priv->npins; diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index b36449724f3f..ada401ef4342 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -581,7 +581,6 @@ static int plgpio_probe(struct platform_device *pdev) plgpio->chip.label = dev_name(&pdev->dev); plgpio->chip.parent = &pdev->dev; plgpio->chip.owner = THIS_MODULE; - plgpio->chip.of_node = pdev->dev.of_node; if (!IS_ERR(plgpio->clk)) { ret = clk_prepare(plgpio->clk); diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index 65b97e240196..6fac30de1c6a 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -565,7 +565,6 @@ int wmt_pinctrl_probe(struct platform_device *pdev, data->gpio_chip = wmt_gpio_chip; data->gpio_chip.parent = &pdev->dev; - data->gpio_chip.of_node = pdev->dev.of_node; data->gpio_chip.ngpio = data->nbanks * 32; platform_set_drvdata(pdev, data); From 54dd5a419f26e994d64754d5f009e36825dec0db Mon Sep 17 00:00:00 2001 From: Julian Braha Date: Wed, 15 Dec 2021 16:40:22 -0500 Subject: [PATCH 86/98] pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED When PINCTRL_ASPEED_G* is selected, and MFD_SYSCON is not selected, Kbuild gives the following warnings: WARNING: unmet direct dependencies detected for PINCTRL_ASPEED Depends on [n]: PINCTRL [=y] && (ARCH_ASPEED [=n] || COMPILE_TEST [=y]) && OF [=y] && MFD_SYSCON [=n] Selected by [y]: - PINCTRL_ASPEED_G4 [=y] && PINCTRL [=y] && (MACH_ASPEED_G4 [=n] || COMPILE_TEST [=y]) && OF [=y] WARNING: unmet direct dependencies detected for PINCTRL_ASPEED Depends on [n]: PINCTRL [=y] && (ARCH_ASPEED [=n] || COMPILE_TEST [=y]) && OF [=y] && MFD_S> Selected by [y]: - PINCTRL_ASPEED_G5 [=y] && PINCTRL [=y] && (MACH_ASPEED_G5 [=n] || COMPILE_TEST [=y]) && O> WARNING: unmet direct dependencies detected for PINCTRL_ASPEED Depends on [n]: PINCTRL [=y] && (ARCH_ASPEED [=n] || COMPILE_TEST [=y]) && OF [=y] && MFD_S> Selected by [y]: - PINCTRL_ASPEED_G6 [=y] && PINCTRL [=y] && (MACH_ASPEED_G6 [=n] || COMPILE_TEST [=y]) && O> This is because MACH_ASPEED_G* depend on (ARCH_ASPEED || COMPILE_TEST). ARCH_ASPEED enables the MFD_SYSCON dependency, but COMPILE_TEST doesn't. These unmet dependency bugs were detected by Kismet, a static analysis tool for Kconfig. Please advise if this is not the appropriate solution. Signed-off-by: Julian Braha Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20211215214022.146391-1-julianbraha@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index de8b185c4fee..1a4e5b9ed471 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_ASPEED bool depends on (ARCH_ASPEED || COMPILE_TEST) && OF - depends on MFD_SYSCON + select MFD_SYSCON select PINMUX select PINCONF select GENERIC_PINCONF From e8f24c58d1b69ecf410a673c22f546dc732bb879 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 6 Dec 2021 09:22:37 +0000 Subject: [PATCH 87/98] ARM: dts: gpio-ranges property is now required Since [1], added in 5.7, the absence of a gpio-ranges property has prevented GPIOs from being restored to inputs when released. Add those properties for BCM283x and BCM2711 devices. [1] commit 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") Fixes: 2ab73c6d8323 ("gpio: Support GPIO controllers without pin-ranges") Signed-off-by: Phil Elwell Acked-by: Florian Fainelli Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20211206092237.4105895-3-phil@raspberrypi.com Signed-off-by: Linus Walleij --- arch/arm/boot/dts/bcm2711.dtsi | 2 ++ arch/arm/boot/dts/bcm283x.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 3b60297af7f6..387f5b4e5837 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -576,6 +576,8 @@ , ; + gpio-ranges = <&gpio 0 0 58>; + gpclk0_gpio49: gpclk0_gpio49 { pin-gpclk { pins = "gpio49"; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index a3e06b680947..c113661a6668 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -126,6 +126,8 @@ interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&gpio 0 0 54>; + /* Defines common pin muxing groups * * While each pin can have its mux selected From 02f117134952c06faef2adb322630c51fcd3c197 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 16 Dec 2021 17:22:03 +0100 Subject: [PATCH 88/98] pinctrl: imx: prepare for making "group_names" in "function_desc" const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The plan for "struct function_desc" is to make its "group_names" /double/ const. That will allow drivers to use it with static const data. This imx change is required to avoid: drivers/pinctrl/freescale/pinctrl-imx.c: In function 'imx_pinctrl_parse_functions': drivers/pinctrl/freescale/pinctrl-imx.c:672:24: error: assignment of read-only location '*(func->group_names + (sizetype)(i * 4))' 672 | func->group_names[i] = child->name; | ^ Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20211216162206.8027-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index daf28bc5661d..47b2ab1a14d0 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -648,6 +648,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct function_desc *func; struct group_desc *grp; + const char **group_names; u32 i = 0; dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); @@ -663,14 +664,16 @@ static int imx_pinctrl_parse_functions(struct device_node *np, dev_err(ipctl->dev, "no groups defined in %pOF\n", np); return -EINVAL; } - func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names, - sizeof(char *), GFP_KERNEL); + + group_names = devm_kcalloc(ipctl->dev, func->num_group_names, + sizeof(char *), GFP_KERNEL); if (!func->group_names) return -ENOMEM; + for_each_child_of_node(np, child) + group_names[i] = child->name; + func->group_names = group_names; for_each_child_of_node(np, child) { - func->group_names[i] = child->name; - grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), GFP_KERNEL); if (!grp) { From 5d0674999cc5caec72130ad8ff3a211d153bcef5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 16 Dec 2021 17:22:04 +0100 Subject: [PATCH 89/98] pinctrl: keembay: comment process of building functions a bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This should make code a bit easier to follow. While at it use some "for" loops to simplify array iteration loops. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20211216162206.8027-2-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-keembay.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-keembay.c b/drivers/pinctrl/pinctrl-keembay.c index 2bce563d5b8b..9a602abad8df 100644 --- a/drivers/pinctrl/pinctrl-keembay.c +++ b/drivers/pinctrl/pinctrl-keembay.c @@ -1617,37 +1617,38 @@ static int keembay_build_functions(struct keembay_pinctrl *kpc) struct function_desc *keembay_funcs, *new_funcs; int i; - /* Allocate total number of functions */ + /* + * Allocate maximum possible number of functions. Assume every pin + * being part of 8 (hw maximum) globally unique muxes. + */ kpc->nfuncs = 0; keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL); if (!keembay_funcs) return -ENOMEM; - /* Find total number of functions and each's properties */ + /* Setup 1 function for each unique mux */ for (i = 0; i < kpc->npins; i++) { const struct pinctrl_pin_desc *pdesc = keembay_pins + i; - struct keembay_mux_desc *mux = pdesc->drv_data; + struct keembay_mux_desc *mux; - while (mux->name) { - struct function_desc *fdesc = keembay_funcs; + for (mux = pdesc->drv_data; mux->name; mux++) { + struct function_desc *fdesc; - while (fdesc->name) { + /* Check if we already have function for this mux */ + for (fdesc = keembay_funcs; fdesc->name; fdesc++) { if (!strcmp(mux->name, fdesc->name)) { fdesc->num_group_names++; break; } - - fdesc++; } + /* Setup new function for this mux we didn't see before */ if (!fdesc->name) { fdesc->name = mux->name; fdesc->num_group_names = 1; fdesc->data = &mux->mode; kpc->nfuncs++; } - - mux++; } } From c26c4bfc10401415b3a5c5a83b94095d7c425617 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 16 Dec 2021 17:22:05 +0100 Subject: [PATCH 90/98] pinctrl: keembay: rework loops looking for groups names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the outer loop iterate over functions as that's the real subject. This simplifies code (and reduces amount of lines of code) as allocating memory for names doesn't require extra checks anymore. While at it use local "group_names" variable. The plan for "struct function_desc" is to make its "group_names" /double/ const. That will allow drivers to use it with static const data. This keembay "group_names" change is required to avoid: drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_add_functions': drivers/pinctrl/pinctrl-keembay.c:1594:8: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] 1594 | grp = func->group_names; | ^ Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20211216162206.8027-3-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-keembay.c | 62 ++++++++++++------------------- 1 file changed, 23 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/pinctrl-keembay.c b/drivers/pinctrl/pinctrl-keembay.c index 9a602abad8df..152c35bce8ec 100644 --- a/drivers/pinctrl/pinctrl-keembay.c +++ b/drivers/pinctrl/pinctrl-keembay.c @@ -1555,58 +1555,42 @@ static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc, struct device *dev) } static int keembay_add_functions(struct keembay_pinctrl *kpc, - struct function_desc *function) + struct function_desc *functions) { unsigned int i; /* Assign the groups for each function */ - for (i = 0; i < kpc->npins; i++) { - const struct pinctrl_pin_desc *pdesc = keembay_pins + i; - struct keembay_mux_desc *mux = pdesc->drv_data; + for (i = 0; i < kpc->nfuncs; i++) { + struct function_desc *func = &functions[i]; + const char **group_names; + unsigned int grp_idx = 0; + int j; - while (mux->name) { - struct function_desc *func; - const char **grp; - size_t grp_size; - u32 j, grp_num; + group_names = devm_kcalloc(kpc->dev, func->num_group_names, + sizeof(*group_names), GFP_KERNEL); + if (!group_names) + return -ENOMEM; - for (j = 0; j < kpc->nfuncs; j++) { - if (!strcmp(mux->name, function[j].name)) - break; + for (j = 0; j < kpc->npins; j++) { + const struct pinctrl_pin_desc *pdesc = &keembay_pins[j]; + struct keembay_mux_desc *mux; + + for (mux = pdesc->drv_data; mux->name; mux++) { + if (!strcmp(mux->name, func->name)) + group_names[grp_idx++] = pdesc->name; } - - if (j == kpc->nfuncs) - return -EINVAL; - - func = function + j; - grp_num = func->num_group_names; - grp_size = sizeof(*func->group_names); - - if (!func->group_names) { - func->group_names = devm_kcalloc(kpc->dev, - grp_num, - grp_size, - GFP_KERNEL); - if (!func->group_names) - return -ENOMEM; - } - - grp = func->group_names; - while (*grp) - grp++; - - *grp = pdesc->name; - mux++; } + + func->group_names = group_names; } /* Add all functions */ for (i = 0; i < kpc->nfuncs; i++) { pinmux_generic_add_function(kpc->pctrl, - function[i].name, - function[i].group_names, - function[i].num_group_names, - function[i].data); + functions[i].name, + functions[i].group_names, + functions[i].num_group_names, + functions[i].data); } return 0; From bd0aae66c4820897797ab550acddd8c659a10b10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 16 Dec 2021 17:22:06 +0100 Subject: [PATCH 91/98] pinctrl: add one more "const" for generic function groups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generic code doesn't modify those strings and .get_function_groups callback has that extra "const" as well. This allows more flexibility in GENERIC_PINMUX_FUNCTIONS users. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20211216162206.8027-4-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinmux.c | 2 +- drivers/pinctrl/pinmux.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 6cdbd9ccf2f0..f94d43b082d9 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -875,7 +875,7 @@ EXPORT_SYMBOL_GPL(pinmux_generic_get_function); */ int pinmux_generic_add_function(struct pinctrl_dev *pctldev, const char *name, - const char **groups, + const char * const *groups, const unsigned int num_groups, void *data) { diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 78c3a31be882..72fcf03eaa43 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -129,7 +129,7 @@ static inline void pinmux_init_device_debugfs(struct dentry *devroot, */ struct function_desc { const char *name; - const char **group_names; + const char * const *group_names; int num_group_names; void *data; }; @@ -150,7 +150,7 @@ struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev, int pinmux_generic_add_function(struct pinctrl_dev *pctldev, const char *name, - const char **groups, + const char * const *groups, unsigned const num_groups, void *data); From 744d04fb4836cc1778cbe853fcac503794ba6fdf Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Lanka Date: Thu, 16 Dec 2021 15:18:45 -0800 Subject: [PATCH 92/98] dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings Add device tree binding Documentation details for Qualcomm SDX65 pinctrl driver. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/ff9abf953c274a1e34f59114642f67ecf02acb6f.1639696427.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sdx65-pinctrl.yaml | 191 ++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml new file mode 100644 index 000000000000..cdfcf29dffee --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX65 TLMM block + +maintainers: + - Vamsi krishna Lanka + +description: + This binding describes the Top Level Mode Multiplexer block found in the + SDX65 platform. + +properties: + compatible: + const: qcom,sdx65-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sdx65-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sdx65-tlmm-state" +'$defs': + qcom-sdx65-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" + - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ] + minItems: 1 + maxItems: 150 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0x03000000 0xdc2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "blsp_uart1"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "blsp_uart1"; + bias-disable; + }; + }; + }; +... From ce852837335abc874e4d943ebbbe7432465a413b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 16 Dec 2021 17:12:27 +0200 Subject: [PATCH 93/98] pinctrl: Propagate firmware node from a parent device When creating MFD platform devices the firmware node is left unset. This, in particular, prevents GPIO library to use it for different purposes. Propagate firmware node from the parent device and let GPIO library do the right thing. While at it, slightly modify the headers to reflect the usage of APIs. Signed-off-by: Andy Shevchenko Acked-by: Charles Keepax Reviewed-by: Adam Thomson Link: https://lore.kernel.org/r/20211216151227.58687-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/cirrus/pinctrl-madera-core.c | 5 ++++- drivers/pinctrl/pinctrl-as3722.c | 13 +++++++------ drivers/pinctrl/pinctrl-da9062.c | 6 +++--- drivers/pinctrl/pinctrl-max77620.c | 11 +++++++---- drivers/pinctrl/pinctrl-rk805.c | 12 ++++++------ 5 files changed, 27 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index dce2626384a9..e1cfbee3643a 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include + #include #include #include @@ -1004,13 +1006,14 @@ static int madera_pin_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "%s\n", __func__); + device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->dev = &pdev->dev; priv->madera = madera; - pdev->dev.of_node = madera->dev->of_node; switch (madera->type) { case CS47L15: diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index 13c193156363..4313756b52e6 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -23,19 +23,20 @@ #include #include #include +#include #include #include -#include -#include #include +#include +#include +#include + #include #include #include #include #include #include -#include -#include #include "core.h" #include "pinconf.h" @@ -551,12 +552,13 @@ static int as3722_pinctrl_probe(struct platform_device *pdev) struct as3722_pctrl_info *as_pci; int ret; + device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); + as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL); if (!as_pci) return -ENOMEM; as_pci->dev = &pdev->dev; - as_pci->dev->of_node = pdev->dev.parent->of_node; as_pci->as3722 = dev_get_drvdata(pdev->dev.parent); platform_set_drvdata(pdev, as_pci); @@ -578,7 +580,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev) as_pci->gpio_chip = as3722_gpio_chip; as_pci->gpio_chip.parent = &pdev->dev; - as_pci->gpio_chip.of_node = pdev->dev.parent->of_node; ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci); if (ret < 0) { dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret); diff --git a/drivers/pinctrl/pinctrl-da9062.c b/drivers/pinctrl/pinctrl-da9062.c index 1c08579f0198..0e0ac3f3ffef 100644 --- a/drivers/pinctrl/pinctrl-da9062.c +++ b/drivers/pinctrl/pinctrl-da9062.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -256,6 +257,8 @@ static int da9062_pctl_probe(struct platform_device *pdev) struct da9062_pctl *pctl; int i; + device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); if (!pctl) return -ENOMEM; @@ -277,9 +280,6 @@ static int da9062_pctl_probe(struct platform_device *pdev) pctl->gc = reference_gc; pctl->gc.label = dev_name(&pdev->dev); pctl->gc.parent = &pdev->dev; -#ifdef CONFIG_OF_GPIO - pctl->gc.of_node = parent->of_node; -#endif platform_set_drvdata(pdev, pctl); diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c index c643ed43ebbf..1ee94574f0af 100644 --- a/drivers/pinctrl/pinctrl-max77620.c +++ b/drivers/pinctrl/pinctrl-max77620.c @@ -10,14 +10,16 @@ */ #include +#include #include -#include +#include +#include +#include + #include #include #include #include -#include -#include #include "core.h" #include "pinconf.h" @@ -551,12 +553,13 @@ static int max77620_pinctrl_probe(struct platform_device *pdev) struct max77620_pctrl_info *mpci; int i; + device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); + mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL); if (!mpci) return -ENOMEM; mpci->dev = &pdev->dev; - mpci->dev->of_node = pdev->dev.parent->of_node; mpci->rmap = max77620->rmap; mpci->pins = max77620_pins_desc; diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index c6f4229eb106..7c1f7408fb9a 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -13,17 +13,17 @@ #include #include #include -#include -#include #include +#include +#include +#include + #include #include #include #include #include #include -#include -#include #include "core.h" #include "pinconf.h" @@ -420,18 +420,18 @@ static int rk805_pinctrl_probe(struct platform_device *pdev) struct rk805_pctrl_info *pci; int ret; + device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); + pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL); if (!pci) return -ENOMEM; pci->dev = &pdev->dev; - pci->dev->of_node = pdev->dev.parent->of_node; pci->rk808 = dev_get_drvdata(pdev->dev.parent); pci->pinctrl_desc = rk805_pinctrl_desc; pci->gpio_chip = rk805_gpio_chip; pci->gpio_chip.parent = &pdev->dev; - pci->gpio_chip.of_node = pdev->dev.parent->of_node; platform_set_drvdata(pdev, pci); From a382d568f144b9e533ad210117c6c50d8dbdcaf1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 24 Dec 2021 14:57:47 +0000 Subject: [PATCH 94/98] pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_optional(). Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211224145748.18754-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-samsung.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 8941f658e7f1..0f6e9305fec5 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1095,7 +1095,6 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) struct samsung_pinctrl_drv_data *drvdata; const struct samsung_pin_ctrl *ctrl; struct device *dev = &pdev->dev; - struct resource *res; int ret; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -1109,9 +1108,11 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) } drvdata->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res) - drvdata->irq = res->start; + ret = platform_get_irq_optional(pdev, 0); + if (ret < 0 && ret != -ENXIO) + return ret; + if (ret > 0) + drvdata->irq = ret; if (ctrl->retention_data) { drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, From aa63e6562ab38f838fd7e3e5d6708495dd144c05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 22 Dec 2021 22:28:07 +0100 Subject: [PATCH 95/98] pinctrl: imx: fix allocation result check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix code to check correct variable value. Reported-by: Abel Vesa Fixes: 02f117134952 ("pinctrl: imx: prepare for making "group_names" in "function_desc" const") Signed-off-by: Rafał Miłecki Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20211222212807.27122-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 47b2ab1a14d0..16bc1bfc03e4 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -667,7 +667,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, group_names = devm_kcalloc(ipctl->dev, func->num_group_names, sizeof(char *), GFP_KERNEL); - if (!func->group_names) + if (!group_names) return -ENOMEM; for_each_child_of_node(np, child) group_names[i] = child->name; From 4b1643cb57da8df86c02a0826cb12ed750abaed7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 22 Dec 2021 07:43:44 +0100 Subject: [PATCH 96/98] pinctrl: bcm: ns: use generic groups & functions helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This simplifies ns driver and gets rid of ~70 lines of code. "const" had to be dropped from "struct ns_pinctrl_group" @pins to match "struct group_desc" @pins and pinctrl_generic_add_group(). Otherwise it would cause: drivers/pinctrl/bcm/pinctrl-ns.c: In function 'ns_pinctrl_probe': drivers/pinctrl/bcm/pinctrl-ns.c:277:13: warning: passing argument 3 of 'pinctrl_generic_add_group' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] 277 | group->pins, group->num_pins, NULL); | ~~~~~^~~~~~ Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20211222064344.14624-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/Kconfig | 2 + drivers/pinctrl/bcm/pinctrl-ns.c | 165 +++++++++---------------------- 2 files changed, 51 insertions(+), 116 deletions(-) diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 8fc1feedd861..5123f4c33854 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -146,6 +146,8 @@ config PINCTRL_NS depends on OF && (ARCH_BCM_5301X || COMPILE_TEST) select PINMUX select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS default ARCH_BCM_5301X help Say yes here to enable the Broadcom NS SoC pins driver. diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c index d7f8175d2c1c..65a86543c58c 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns.c +++ b/drivers/pinctrl/bcm/pinctrl-ns.c @@ -14,6 +14,9 @@ #include #include +#include "../core.h" +#include "../pinmux.h" + #define FLAG_BCM4708 BIT(1) #define FLAG_BCM4709 BIT(2) #define FLAG_BCM53012 BIT(3) @@ -25,10 +28,6 @@ struct ns_pinctrl { void __iomem *base; struct pinctrl_desc pctldesc; - struct ns_pinctrl_group *groups; - unsigned int num_groups; - struct ns_pinctrl_function *functions; - unsigned int num_functions; }; /* @@ -65,22 +64,22 @@ static const struct pinctrl_pin_desc ns_pinctrl_pins[] = { struct ns_pinctrl_group { const char *name; - const unsigned int *pins; + unsigned int *pins; const unsigned int num_pins; unsigned int chipsets; }; -static const unsigned int spi_pins[] = { 0, 1, 2, 3 }; -static const unsigned int i2c_pins[] = { 4, 5 }; -static const unsigned int mdio_pins[] = { 6, 7 }; -static const unsigned int pwm0_pins[] = { 8 }; -static const unsigned int pwm1_pins[] = { 9 }; -static const unsigned int pwm2_pins[] = { 10 }; -static const unsigned int pwm3_pins[] = { 11 }; -static const unsigned int uart1_pins[] = { 12, 13, 14, 15 }; -static const unsigned int uart2_pins[] = { 16, 17 }; -static const unsigned int sdio_pwr_pins[] = { 22 }; -static const unsigned int sdio_1p8v_pins[] = { 23 }; +static unsigned int spi_pins[] = { 0, 1, 2, 3 }; +static unsigned int i2c_pins[] = { 4, 5 }; +static unsigned int mdio_pins[] = { 6, 7 }; +static unsigned int pwm0_pins[] = { 8 }; +static unsigned int pwm1_pins[] = { 9 }; +static unsigned int pwm2_pins[] = { 10 }; +static unsigned int pwm3_pins[] = { 11 }; +static unsigned int uart1_pins[] = { 12, 13, 14, 15 }; +static unsigned int uart2_pins[] = { 16, 17 }; +static unsigned int sdio_pwr_pins[] = { 22 }; +static unsigned int sdio_1p8v_pins[] = { 23 }; #define NS_GROUP(_name, _pins, _chipsets) \ { \ @@ -146,38 +145,10 @@ static const struct ns_pinctrl_function ns_pinctrl_functions[] = { * Groups code */ -static int ns_pinctrl_get_groups_count(struct pinctrl_dev *pctrl_dev) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - return ns_pinctrl->num_groups; -} - -static const char *ns_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev, - unsigned int selector) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - return ns_pinctrl->groups[selector].name; -} - -static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev, - unsigned int selector, - const unsigned int **pins, - unsigned int *num_pins) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - *pins = ns_pinctrl->groups[selector].pins; - *num_pins = ns_pinctrl->groups[selector].num_pins; - - return 0; -} - static const struct pinctrl_ops ns_pinctrl_ops = { - .get_groups_count = ns_pinctrl_get_groups_count, - .get_group_name = ns_pinctrl_get_group_name, - .get_group_pins = ns_pinctrl_get_group_pins, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, .dt_node_to_map = pinconf_generic_dt_node_to_map_group, .dt_free_map = pinconf_generic_dt_free_map, }; @@ -186,48 +157,22 @@ static const struct pinctrl_ops ns_pinctrl_ops = { * Functions code */ -static int ns_pinctrl_get_functions_count(struct pinctrl_dev *pctrl_dev) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - return ns_pinctrl->num_functions; -} - -static const char *ns_pinctrl_get_function_name(struct pinctrl_dev *pctrl_dev, - unsigned int selector) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - return ns_pinctrl->functions[selector].name; -} - -static int ns_pinctrl_get_function_groups(struct pinctrl_dev *pctrl_dev, - unsigned int selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - - *groups = ns_pinctrl->functions[selector].groups; - *num_groups = ns_pinctrl->functions[selector].num_groups; - - return 0; -} - static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int func_select, - unsigned int grp_select) + unsigned int group_selector) { struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + struct group_desc *group; u32 unset = 0; u32 tmp; int i; - for (i = 0; i < ns_pinctrl->groups[grp_select].num_pins; i++) { - int pin_number = ns_pinctrl->groups[grp_select].pins[i]; + group = pinctrl_generic_get_group(pctrl_dev, group_selector); + if (!group) + return -EINVAL; - unset |= BIT(pin_number); - } + for (i = 0; i < group->num_pins; i++) + unset |= BIT(group->pins[i]); tmp = readl(ns_pinctrl->base); tmp &= ~unset; @@ -237,9 +182,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, } static const struct pinmux_ops ns_pinctrl_pmxops = { - .get_functions_count = ns_pinctrl_get_functions_count, - .get_function_name = ns_pinctrl_get_function_name, - .get_function_groups = ns_pinctrl_get_function_groups, + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, .set_mux = ns_pinctrl_set_mux, }; @@ -267,8 +212,6 @@ static int ns_pinctrl_probe(struct platform_device *pdev) struct ns_pinctrl *ns_pinctrl; struct pinctrl_desc *pctldesc; struct pinctrl_pin_desc *pin; - struct ns_pinctrl_group *group; - struct ns_pinctrl_function *function; struct resource *res; int i; @@ -315,37 +258,6 @@ static int ns_pinctrl_probe(struct platform_device *pdev) } } - ns_pinctrl->groups = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_groups), - sizeof(struct ns_pinctrl_group), - GFP_KERNEL); - if (!ns_pinctrl->groups) - return -ENOMEM; - for (i = 0, group = &ns_pinctrl->groups[0]; - i < ARRAY_SIZE(ns_pinctrl_groups); i++) { - const struct ns_pinctrl_group *src = &ns_pinctrl_groups[i]; - - if (src->chipsets & ns_pinctrl->chipset_flag) { - memcpy(group++, src, sizeof(*src)); - ns_pinctrl->num_groups++; - } - } - - ns_pinctrl->functions = devm_kcalloc(dev, - ARRAY_SIZE(ns_pinctrl_functions), - sizeof(struct ns_pinctrl_function), - GFP_KERNEL); - if (!ns_pinctrl->functions) - return -ENOMEM; - for (i = 0, function = &ns_pinctrl->functions[0]; - i < ARRAY_SIZE(ns_pinctrl_functions); i++) { - const struct ns_pinctrl_function *src = &ns_pinctrl_functions[i]; - - if (src->chipsets & ns_pinctrl->chipset_flag) { - memcpy(function++, src, sizeof(*src)); - ns_pinctrl->num_functions++; - } - } - /* Register */ ns_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, ns_pinctrl); @@ -354,6 +266,27 @@ static int ns_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(ns_pinctrl->pctldev); } + for (i = 0; i < ARRAY_SIZE(ns_pinctrl_groups); i++) { + const struct ns_pinctrl_group *group = &ns_pinctrl_groups[i]; + + if (!(group->chipsets & ns_pinctrl->chipset_flag)) + continue; + + pinctrl_generic_add_group(ns_pinctrl->pctldev, group->name, + group->pins, group->num_pins, NULL); + } + + for (i = 0; i < ARRAY_SIZE(ns_pinctrl_functions); i++) { + const struct ns_pinctrl_function *function = &ns_pinctrl_functions[i]; + + if (!(function->chipsets & ns_pinctrl->chipset_flag)) + continue; + + pinmux_generic_add_function(ns_pinctrl->pctldev, function->name, + function->groups, + function->num_groups, NULL); + } + return 0; } From 79dcd4e840ccfaf8018ec96415fdc0250e945c77 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Mon, 20 Dec 2021 20:18:24 +0800 Subject: [PATCH 97/98] dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations On mt8195, the pinctrl node has pinctrl groups to group pin configurations by users' need. In each pinctrl group, it has subnode(s) to list pins needed and pin configurations. By supporting multiple subnodes, we can configure different pin characteristics (driving/pull-up/pull-down/etc.) in a pinctrl group. Update pinctrl-mt8195.yaml to add subnode in pinctrl groups and an example to illustrate the usage. Signed-off-by: Tinghan Shen Acked-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211220121825.6446-4-tinghan.shen@mediatek.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-mt8195.yaml | 344 ++++++++++-------- 1 file changed, 191 insertions(+), 153 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 3cf74df12862..328ea59c5466 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -55,137 +55,159 @@ properties: Identifying i2c pins pull up/down type which is RSEL. It can support RSEL define or si unit value(ohm) to set different resistance. -#PIN CONFIGURATION NODES +# PIN CONFIGURATION NODES patternProperties: '-pins$': type: object - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - gpio_pin { - pinmux = ; - }; - /* GPIO8 set as multifunction SDA0 */ - i2c0_pin { - pinmux = ; - }; - }; - $ref: "pinmux-node.yaml" - - properties: - pinmux: - description: | - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - - bias-pull-down: - description: | - For pull down type is normal, it don't need add RSEL & R1R0 define - and resistance value. - For pull down type is PUPD/R0/R1 type, it can add R1R0 define to - set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8195. - For pull down type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull down PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull down RSEL type define value. - - enum: [75000, 5000] - - description: mt8195 pull down RSEL type si unit value(ohm). - - An example of using RSEL define: - pincontroller { - i2c0_pin { - pinmux = ; - bias-pull-down = ; - }; - }; - An example of using si unit resistance value(ohm): - &pio { - mediatek,rsel_resistance_in_si_unit; - } - pincontroller { - i2c0_pin { - pinmux = ; - bias-pull-down = <75000>; - }; - }; - - bias-pull-up: - description: | - For pull up type is normal, it don't need add RSEL & R1R0 define - and resistance value. - For pull up type is PUPD/R0/R1 type, it can add R1R0 define to - set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8195. - For pull up type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull up PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull up RSEL type define value. - - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] - - description: mt8195 pull up RSEL type si unit value(ohm). - An example of using RSEL define: - pincontroller { - i2c0_pin { - pinmux = ; - bias-pull-up = ; - }; - }; - An example of using si unit resistance value(ohm): - &pio { - mediatek,rsel_resistance_in_si_unit; - } - pincontroller { - i2c0_pin { - pinmux = ; - bias-pull-up = <1000>; - }; - }; - - bias-disable: true - - output-high: true - - output-low: true - - input-enable: true - - input-disable: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - required: - - pinmux - additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = ; + } + }; + /* GPIO8 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = ; + } + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h + directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8195. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel_resistance_in_si_unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) + "75000" & "5000" in mt8195. + oneOf: + - enum: [100, 101, 102, 103] + - description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + - description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + - description: mt8195 pull down RSEL type si unit value(ohm). + + An example of using RSEL define: + pincontroller { + i2c0_pin { + pins { + pinmux = ; + bias-pull-down = ; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel_resistance_in_si_unit; + } + pincontroller { + i2c0_pin { + pins { + pinmux = ; + bias-pull-down = <75000>; + } + }; + }; + + bias-pull-up: + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8195. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel_resistance_in_si_unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & + "75000" in mt8195. + oneOf: + - enum: [100, 101, 102, 103] + - description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + - description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + - description: mt8195 pull up RSEL type si unit value(ohm). + An example of using RSEL define: + pincontroller { + i2c0-pins { + pins { + pinmux = ; + bias-pull-up = ; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel_resistance_in_si_unit; + } + pincontroller { + i2c0-pins { + pins { + pinmux = ; + bias-pull-up = <1000>; + } + }; + }; + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux allOf: - $ref: "pinctrl.yaml#" @@ -204,30 +226,46 @@ additionalProperties: false examples: - | - #include - #include - pio: pinctrl@10005000 { - compatible = "mediatek,mt8195-pinctrl"; - reg = <0x10005000 0x1000>, - <0x11d10000 0x1000>, - <0x11d30000 0x1000>, - <0x11d40000 0x1000>, - <0x11e20000 0x1000>, - <0x11eb0000 0x1000>, - <0x11f40000 0x1000>, - <0x1000b000 0x1000>; - reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", - "iocfg_br", "iocfg_lm", "iocfg_rb", - "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 144>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; + #include + #include + # + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11eb0000 0x1000>, + <0x11f40000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; - pio-pins { - pinmux = ; - output-low; - }; - }; + pio-pins { + pins { + pinmux = ; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = , + , + ; + bias-disable; + }; + pins-spi-mi { + pinmux = ; + bias-pull-down; + }; + }; + }; From 7442936633bd1906a2571116ae334b68c56c8a72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 27 Dec 2021 13:22:37 +0100 Subject: [PATCH 98/98] pinctrl: imx: fix assigning groups names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes regression caused by incorrect array indexing. Reported-by: Fabio Estevam Fixes: 02f117134952 ("pinctrl: imx: prepare for making "group_names" in "function_desc" const") Signed-off-by: Rafał Miłecki Tested-by: Fabio Estevam Link: https://lore.kernel.org/r/20211227122237.6363-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 16bc1bfc03e4..fa3cc0b80ede 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -649,7 +649,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct function_desc *func; struct group_desc *grp; const char **group_names; - u32 i = 0; + u32 i; dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); @@ -669,10 +669,12 @@ static int imx_pinctrl_parse_functions(struct device_node *np, sizeof(char *), GFP_KERNEL); if (!group_names) return -ENOMEM; + i = 0; for_each_child_of_node(np, child) - group_names[i] = child->name; + group_names[i++] = child->name; func->group_names = group_names; + i = 0; for_each_child_of_node(np, child) { grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), GFP_KERNEL);