bnxt_en: Add 57500 new chip ID and basic structures.
57500 series is a new chip class (P5) that requires some driver changes in the next several patches. This adds basic chip ID, doorbells, and the notification queue (NQ) structures. Each MSIX is associated with an NQ instead of a CP ring in legacy chips. Each NQ has up to 2 associated CP rings for RX and TX. The same bnxt_cp_ring_info struct will be used for the NQ. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
1b9394e5a2
commit
e38287b72e
@@ -3322,6 +3322,13 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
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bp->bnapi[i] = bnapi;
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bp->bnapi[i]->index = i;
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bp->bnapi[i]->bp = bp;
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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struct bnxt_cp_ring_info *cpr =
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&bp->bnapi[i]->cp_ring;
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cpr->cp_ring_struct.ring_mem.flags =
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BNXT_RMEM_RING_PTE_FLAG;
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}
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}
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bp->rx_ring = kcalloc(bp->rx_nr_rings,
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@@ -3331,7 +3338,15 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
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return -ENOMEM;
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for (i = 0; i < bp->rx_nr_rings; i++) {
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bp->rx_ring[i].bnapi = bp->bnapi[i];
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struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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rxr->rx_ring_struct.ring_mem.flags =
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BNXT_RMEM_RING_PTE_FLAG;
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rxr->rx_agg_ring_struct.ring_mem.flags =
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BNXT_RMEM_RING_PTE_FLAG;
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}
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rxr->bnapi = bp->bnapi[i];
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bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
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}
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@@ -3353,12 +3368,16 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
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j = bp->rx_nr_rings;
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for (i = 0; i < bp->tx_nr_rings; i++, j++) {
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bp->tx_ring[i].bnapi = bp->bnapi[j];
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bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
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struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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txr->tx_ring_struct.ring_mem.flags =
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BNXT_RMEM_RING_PTE_FLAG;
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txr->bnapi = bp->bnapi[j];
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bp->bnapi[j]->tx_ring = txr;
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bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
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if (i >= bp->tx_nr_rings_xdp) {
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bp->tx_ring[i].txq_index = i -
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bp->tx_nr_rings_xdp;
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txr->txq_index = i - bp->tx_nr_rings_xdp;
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bp->bnapi[j]->tx_int = bnxt_tx_int;
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} else {
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bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
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@@ -9326,6 +9345,9 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto init_err_pci_clean;
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}
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if (BNXT_CHIP_P5(bp))
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bp->flags |= BNXT_FLAG_CHIP_P5;
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rc = bnxt_hwrm_func_reset(bp);
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if (rc)
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goto init_err_pci_clean;
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@@ -9340,7 +9362,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
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NETIF_F_RXCSUM | NETIF_F_GRO;
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if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
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if (BNXT_SUPPORTS_TPA(bp))
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dev->hw_features |= NETIF_F_LRO;
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dev->hw_enc_features =
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@@ -9354,7 +9376,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
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dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
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NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
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if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
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if (BNXT_SUPPORTS_TPA(bp))
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dev->hw_features |= NETIF_F_GRO_HW;
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dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
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if (dev->features & NETIF_F_GRO_HW)
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@@ -9365,10 +9387,12 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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init_waitqueue_head(&bp->sriov_cfg_wait);
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mutex_init(&bp->sriov_lock);
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#endif
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bp->gro_func = bnxt_gro_func_5730x;
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if (BNXT_CHIP_P4_PLUS(bp))
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bp->gro_func = bnxt_gro_func_5731x;
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else
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if (BNXT_SUPPORTS_TPA(bp)) {
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bp->gro_func = bnxt_gro_func_5730x;
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if (BNXT_CHIP_P4(bp))
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bp->gro_func = bnxt_gro_func_5731x;
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}
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if (!BNXT_CHIP_P4_PLUS(bp))
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bp->flags |= BNXT_FLAG_DOUBLE_DB;
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rc = bnxt_hwrm_func_drv_rgtr(bp);
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@@ -9432,7 +9456,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
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VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
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VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
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if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
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if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
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bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
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bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
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VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
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