can: m_can: Disable IRQs on FIFO bus errors
If FIFO reads or writes fail due to the underlying regmap (e.g., SPI) I/O, propagate that up to the m_can driver, log an error, and disable interrupts, similar to the mcp251xfd driver. While reworking the FIFO functions to add this error handling, add support for bulk reads and writes of multiple registers. Link: https://lore.kernel.org/r/20210817050853.14875-2-matt@bitbashing.io Signed-off-by: Matt Kline <matt@bitbashing.io> [mkl: re-wrap long lines, remove WARN_ON, convert to netdev block comments] Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Matt Kline
Marc Kleine-Budde
parent
5020ced445
commit
e39381770e
@ -320,36 +320,39 @@ static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
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cdev->ops->write_reg(cdev, reg, val);
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}
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static u32 m_can_fifo_read(struct m_can_classdev *cdev,
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u32 fgi, unsigned int offset)
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static int
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m_can_fifo_read(struct m_can_classdev *cdev,
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u32 fgi, unsigned int offset, void *val, size_t val_count)
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{
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u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
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offset;
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return cdev->ops->read_fifo(cdev, addr_offset);
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return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
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}
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static void m_can_fifo_write(struct m_can_classdev *cdev,
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u32 fpi, unsigned int offset, u32 val)
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static int
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m_can_fifo_write(struct m_can_classdev *cdev,
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u32 fpi, unsigned int offset, const void *val, size_t val_count)
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{
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u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
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offset;
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cdev->ops->write_fifo(cdev, addr_offset, val);
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return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
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}
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static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,
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u32 fpi, u32 val)
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static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
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u32 fpi, u32 val)
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{
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cdev->ops->write_fifo(cdev, fpi, val);
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return cdev->ops->write_fifo(cdev, fpi, &val, 1);
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}
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static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
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static int
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m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
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{
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u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
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offset;
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return cdev->ops->read_fifo(cdev, addr_offset);
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return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
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}
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static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
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@ -455,7 +458,7 @@ static void m_can_receive_skb(struct m_can_classdev *cdev,
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}
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}
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static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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static int m_can_read_fifo(struct net_device *dev, u32 rxfs)
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{
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struct net_device_stats *stats = &dev->stats;
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struct m_can_classdev *cdev = netdev_priv(dev);
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@ -463,18 +466,21 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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struct sk_buff *skb;
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u32 id, fgi, dlc;
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u32 timestamp = 0;
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int i;
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int i, err;
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/* calculate the fifo get index for where to read data */
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fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
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dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
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err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC, &dlc, 1);
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if (err)
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goto out_fail;
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if (dlc & RX_BUF_FDF)
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skb = alloc_canfd_skb(dev, &cf);
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else
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skb = alloc_can_skb(dev, (struct can_frame **)&cf);
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if (!skb) {
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stats->rx_dropped++;
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return;
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return 0;
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}
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if (dlc & RX_BUF_FDF)
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@ -482,7 +488,10 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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else
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cf->len = can_cc_dlc2len((dlc >> 16) & 0x0F);
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id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);
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err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &id, 1);
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if (err)
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goto out_fail;
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if (id & RX_BUF_XTD)
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cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
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else
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@ -499,10 +508,11 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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if (dlc & RX_BUF_BRS)
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cf->flags |= CANFD_BRS;
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for (i = 0; i < cf->len; i += 4)
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*(u32 *)(cf->data + i) =
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m_can_fifo_read(cdev, fgi,
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M_CAN_FIFO_DATA(i / 4));
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for (i = 0; i < cf->len; i += 4) {
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err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA(i / 4), cf->data + i, 1);
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if (err)
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goto out_fail;
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}
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}
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/* acknowledge rx fifo 0 */
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@ -514,6 +524,12 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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timestamp = FIELD_GET(RX_BUF_RXTS_MASK, dlc);
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m_can_receive_skb(cdev, skb, timestamp);
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return 0;
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out_fail:
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netdev_err(dev, "FIFO read returned %d\n", err);
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return err;
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}
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static int m_can_do_rx_poll(struct net_device *dev, int quota)
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@ -521,6 +537,7 @@ static int m_can_do_rx_poll(struct net_device *dev, int quota)
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struct m_can_classdev *cdev = netdev_priv(dev);
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u32 pkts = 0;
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u32 rxfs;
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int err;
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rxfs = m_can_read(cdev, M_CAN_RXF0S);
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if (!(rxfs & RXFS_FFL_MASK)) {
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@ -529,7 +546,9 @@ static int m_can_do_rx_poll(struct net_device *dev, int quota)
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}
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while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
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m_can_read_fifo(dev, rxfs);
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err = m_can_read_fifo(dev, rxfs);
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if (err)
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return err;
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quota--;
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pkts++;
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@ -875,6 +894,7 @@ static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
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static int m_can_rx_handler(struct net_device *dev, int quota)
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{
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struct m_can_classdev *cdev = netdev_priv(dev);
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int rx_work_or_err;
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int work_done = 0;
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u32 irqstatus, psr;
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@ -911,8 +931,13 @@ static int m_can_rx_handler(struct net_device *dev, int quota)
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if (irqstatus & IR_ERR_BUS_30X)
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work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
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if (irqstatus & IR_RF0N)
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work_done += m_can_do_rx_poll(dev, (quota - work_done));
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if (irqstatus & IR_RF0N) {
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rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done));
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if (rx_work_or_err < 0)
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return rx_work_or_err;
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work_done += rx_work_or_err;
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}
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end:
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return work_done;
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}
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@ -920,12 +945,17 @@ end:
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static int m_can_rx_peripheral(struct net_device *dev)
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{
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struct m_can_classdev *cdev = netdev_priv(dev);
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int work_done;
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m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT);
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work_done = m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT);
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m_can_enable_all_interrupts(cdev);
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/* Don't re-enable interrupts if the driver had a fatal error
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* (e.g., FIFO read failure).
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*/
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if (work_done >= 0)
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m_can_enable_all_interrupts(cdev);
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return 0;
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return work_done;
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}
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static int m_can_poll(struct napi_struct *napi, int quota)
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@ -935,7 +965,11 @@ static int m_can_poll(struct napi_struct *napi, int quota)
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int work_done;
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work_done = m_can_rx_handler(dev, quota);
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if (work_done < quota) {
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/* Don't re-enable interrupts if the driver had a fatal error
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* (e.g., FIFO read failure).
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*/
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if (work_done >= 0 && work_done < quota) {
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napi_complete_done(napi, work_done);
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m_can_enable_all_interrupts(cdev);
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}
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@ -966,7 +1000,7 @@ static void m_can_tx_update_stats(struct m_can_classdev *cdev,
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stats->tx_packets++;
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}
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static void m_can_echo_tx_event(struct net_device *dev)
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static int m_can_echo_tx_event(struct net_device *dev)
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{
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u32 txe_count = 0;
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u32 m_can_txefs;
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@ -985,12 +1019,18 @@ static void m_can_echo_tx_event(struct net_device *dev)
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/* Get and process all sent elements */
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for (i = 0; i < txe_count; i++) {
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u32 txe, timestamp = 0;
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int err;
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/* retrieve get index */
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fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS));
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/* get message marker, timestamp */
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txe = m_can_txe_fifo_read(cdev, fgi, 4);
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err = m_can_txe_fifo_read(cdev, fgi, 4, &txe);
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if (err) {
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netdev_err(dev, "TXE FIFO read returned %d\n", err);
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return err;
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}
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msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
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timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe);
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@ -1001,6 +1041,8 @@ static void m_can_echo_tx_event(struct net_device *dev)
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/* update stats */
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m_can_tx_update_stats(cdev, msg_mark, timestamp);
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}
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return 0;
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}
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static irqreturn_t m_can_isr(int irq, void *dev_id)
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@ -1032,8 +1074,8 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
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m_can_disable_all_interrupts(cdev);
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if (!cdev->is_peripheral)
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napi_schedule(&cdev->napi);
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else
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m_can_rx_peripheral(dev);
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else if (m_can_rx_peripheral(dev) < 0)
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goto out_fail;
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}
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if (cdev->version == 30) {
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@ -1051,7 +1093,9 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
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} else {
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if (ir & IR_TEFN) {
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/* New TX FIFO Element arrived */
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m_can_echo_tx_event(dev);
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if (m_can_echo_tx_event(dev) != 0)
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goto out_fail;
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can_led_event(dev, CAN_LED_EVENT_TX);
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if (netif_queue_stopped(dev) &&
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!m_can_tx_fifo_full(cdev))
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@ -1063,6 +1107,10 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
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can_rx_offload_threaded_irq_finish(&cdev->offload);
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return IRQ_HANDLED;
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out_fail:
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m_can_disable_all_interrupts(cdev);
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return IRQ_HANDLED;
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}
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static const struct can_bittiming_const m_can_bittiming_const_30X = {
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@ -1535,8 +1583,8 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
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struct net_device *dev = cdev->net;
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struct sk_buff *skb = cdev->tx_skb;
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u32 id, cccr, fdflags;
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int i;
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u32 id, dlc, cccr, fdflags;
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int i, err;
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int putidx;
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cdev->tx_skb = NULL;
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@ -1557,14 +1605,20 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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netif_stop_queue(dev);
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/* message ram configuration */
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m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id);
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m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC,
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can_fd_len2dlc(cf->len) << 16);
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err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &id, 1);
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if (err)
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goto out_fail;
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for (i = 0; i < cf->len; i += 4)
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m_can_fifo_write(cdev, 0,
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M_CAN_FIFO_DATA(i / 4),
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*(u32 *)(cf->data + i));
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dlc = can_fd_len2dlc(cf->len) << 16;
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err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC, &dlc, 1);
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if (err)
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goto out_fail;
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for (i = 0; i < cf->len; i += 4) {
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err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA(i / 4), cf->data + i, 1);
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if (err)
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goto out_fail;
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}
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can_put_echo_skb(skb, dev, 0, 0);
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@ -1609,7 +1663,9 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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putidx = FIELD_GET(TXFQS_TFQPI_MASK,
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m_can_read(cdev, M_CAN_TXFQS));
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/* Write ID Field to FIFO Element */
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m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
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err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &id, 1);
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if (err)
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goto out_fail;
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/* get CAN FD configuration of frame */
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fdflags = 0;
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@ -1624,15 +1680,19 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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* it is used in TX interrupt for
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* sending the correct echo frame
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*/
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m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,
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FIELD_PREP(TX_BUF_MM_MASK, putidx) |
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FIELD_PREP(TX_BUF_DLC_MASK,
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can_fd_len2dlc(cf->len)) |
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fdflags | TX_BUF_EFC);
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dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
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FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
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fdflags | TX_BUF_EFC;
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err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, &dlc, 1);
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if (err)
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goto out_fail;
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for (i = 0; i < cf->len; i += 4)
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m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),
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*(u32 *)(cf->data + i));
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for (i = 0; i < cf->len; i += 4) {
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err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),
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cf->data + i, 1);
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if (err)
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goto out_fail;
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}
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/* Push loopback echo.
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* Will be looped back on TX interrupt based on message marker
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@ -1649,6 +1709,11 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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}
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return NETDEV_TX_OK;
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out_fail:
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netdev_err(dev, "FIFO write returned %d\n", err);
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m_can_disable_all_interrupts(cdev);
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return NETDEV_TX_BUSY;
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}
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static void m_can_tx_work_queue(struct work_struct *ws)
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@ -1820,9 +1885,10 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev,
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cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
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}
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void m_can_init_ram(struct m_can_classdev *cdev)
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int m_can_init_ram(struct m_can_classdev *cdev)
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{
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int end, i, start;
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int err = 0;
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/* initialize the entire Message RAM in use to avoid possible
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* ECC/parity checksum errors when reading an uninitialized buffer
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@ -1831,8 +1897,13 @@ void m_can_init_ram(struct m_can_classdev *cdev)
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end = cdev->mcfg[MRAM_TXB].off +
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cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
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for (i = start; i < end; i += 4)
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m_can_fifo_write_no_off(cdev, i, 0x0);
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for (i = start; i < end; i += 4) {
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err = m_can_fifo_write_no_off(cdev, i, 0x0);
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if (err)
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break;
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}
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return err;
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}
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EXPORT_SYMBOL_GPL(m_can_init_ram);
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@ -65,9 +65,9 @@ struct m_can_ops {
|
||||
int (*clear_interrupts)(struct m_can_classdev *cdev);
|
||||
u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
|
||||
int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
|
||||
u32 (*read_fifo)(struct m_can_classdev *cdev, int addr_offset);
|
||||
int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
|
||||
int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
|
||||
int val);
|
||||
const void *val, size_t val_count);
|
||||
int (*init)(struct m_can_classdev *cdev);
|
||||
};
|
||||
|
||||
@ -101,7 +101,7 @@ void m_can_class_free_dev(struct net_device *net);
|
||||
int m_can_class_register(struct m_can_classdev *cdev);
|
||||
void m_can_class_unregister(struct m_can_classdev *cdev);
|
||||
int m_can_class_get_clocks(struct m_can_classdev *cdev);
|
||||
void m_can_init_ram(struct m_can_classdev *priv);
|
||||
int m_can_init_ram(struct m_can_classdev *priv);
|
||||
|
||||
int m_can_class_suspend(struct device *dev);
|
||||
int m_can_class_resume(struct device *dev);
|
||||
|
||||
@ -39,11 +39,13 @@ static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
return readl(priv->base + reg);
|
||||
}
|
||||
|
||||
static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
|
||||
static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->base + offset);
|
||||
ioread32_rep(priv->base + offset, val, val_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
@ -55,11 +57,12 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
|
||||
const void *val, size_t val_count)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->base + offset);
|
||||
iowrite32_rep(priv->base + offset, val, val_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -29,11 +29,13 @@ static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
return readl(priv->base + reg);
|
||||
}
|
||||
|
||||
static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
|
||||
static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->mram_base + offset);
|
||||
ioread32_rep(priv->mram_base + offset, val, val_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
@ -45,11 +47,12 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
|
||||
const void *val, size_t val_count)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->mram_base + offset);
|
||||
iowrite32_rep(priv->base + offset, val, val_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -127,7 +130,9 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
||||
|
||||
platform_set_drvdata(pdev, mcan_class);
|
||||
|
||||
m_can_init_ram(mcan_class);
|
||||
ret = m_can_init_ram(mcan_class);
|
||||
if (ret)
|
||||
goto probe_fail;
|
||||
|
||||
pm_runtime_enable(mcan_class->dev);
|
||||
ret = m_can_class_register(mcan_class);
|
||||
|
||||
@ -153,14 +153,12 @@ static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
return val;
|
||||
}
|
||||
|
||||
static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
|
||||
static int tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset,
|
||||
void *val, size_t val_count)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
u32 val;
|
||||
|
||||
regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val);
|
||||
|
||||
return val;
|
||||
return regmap_bulk_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count);
|
||||
}
|
||||
|
||||
static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
@ -171,11 +169,11 @@ static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
}
|
||||
|
||||
static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
|
||||
int addr_offset, int val)
|
||||
int addr_offset, const void *val, size_t val_count)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val);
|
||||
return regmap_bulk_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count);
|
||||
}
|
||||
|
||||
static int tcan4x5x_power_enable(struct regulator *reg, int enable)
|
||||
@ -237,7 +235,9 @@ static int tcan4x5x_init(struct m_can_classdev *cdev)
|
||||
return ret;
|
||||
|
||||
/* Zero out the MCAN buffers */
|
||||
m_can_init_ram(cdev);
|
||||
ret = m_can_init_ram(cdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
|
||||
TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user