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drm/i915/pvc: Implement recommended caching policy

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As per the performance tuning guide, set the HOSTCACHEEN bit to
implement the recommended caching policy on PVC.

Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221130170723.2460014-1-wayne.boyer@intel.com
This commit is contained in:
Wayne Boyer 2022-11-30 09:07:23 -08:00 committed by Matt Roper
parent 9bbba0667f
commit e3995e08a3
2 changed files with 2 additions and 0 deletions
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1
drivers/gpu/drm/i915/gt/intel_gt_regs.h
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@ -972,6 +972,7 @@
#define GEN7_L3AGDIS (1 << 19)
#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c)
#define XEHPC_HOSTCACHEEN REG_BIT(1)
#define XEHPC_OVRLSCCC REG_BIT(0)
#define GEN7_L3CNTLREG2 _MMIO(0xb020)

1
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -2906,6 +2906,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
if (IS_PONTEVECCHIO(i915)) {
wa_write(wal, XEHPC_L3SCRUB,
SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
}
if (IS_DG2(i915)) {