drm/i915/pvc: Implement recommended caching policy
As per the performance tuning guide, set the HOSTCACHEEN bit to implement the recommended caching policy on PVC. Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221130170723.2460014-1-wayne.boyer@intel.com
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@ -972,6 +972,7 @@
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#define GEN7_L3AGDIS (1 << 19)
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#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c)
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#define XEHPC_HOSTCACHEEN REG_BIT(1)
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#define XEHPC_OVRLSCCC REG_BIT(0)
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#define GEN7_L3CNTLREG2 _MMIO(0xb020)
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@ -2906,6 +2906,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
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if (IS_PONTEVECCHIO(i915)) {
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wa_write(wal, XEHPC_L3SCRUB,
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SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
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wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
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}
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if (IS_DG2(i915)) {
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