drm/nouveau: initial falcon (fuc) engine base class implementation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
2d8b9ccbce
commit
e3aaa946bd
@ -11,6 +11,7 @@ nouveau-y := core/core/client.o
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nouveau-y += core/core/engctx.o
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nouveau-y += core/core/engine.o
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nouveau-y += core/core/enum.o
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nouveau-y += core/core/falcon.o
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nouveau-y += core/core/gpuobj.o
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nouveau-y += core/core/handle.o
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nouveau-y += core/core/mm.o
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247
drivers/gpu/drm/nouveau/core/core/falcon.c
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247
drivers/gpu/drm/nouveau/core/core/falcon.c
Normal file
@ -0,0 +1,247 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <core/falcon.h>
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#include <subdev/timer.h>
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u32
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_nouveau_falcon_rd32(struct nouveau_object *object, u64 addr)
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{
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struct nouveau_falcon *falcon = (void *)object;
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return nv_rd32(falcon, falcon->addr + addr);
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}
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void
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_nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data)
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{
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struct nouveau_falcon *falcon = (void *)object;
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nv_wr32(falcon, falcon->addr + addr, data);
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}
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int
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_nouveau_falcon_init(struct nouveau_object *object)
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{
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struct nouveau_device *device = nv_device(object);
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struct nouveau_falcon *falcon = (void *)object;
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const struct firmware *fw;
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char name[32] = "internal";
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int ret, i;
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u32 caps;
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/* enable engine, and determine its capabilities */
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ret = nouveau_engine_init(&falcon->base);
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if (ret)
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return ret;
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if (device->chipset < 0xa3 ||
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device->chipset == 0xaa || device->chipset == 0xac) {
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falcon->version = 0;
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falcon->secret = (falcon->addr == 0x087000) ? 1 : 0;
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} else {
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caps = nv_ro32(falcon, 0x12c);
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falcon->version = (caps & 0x0000000f);
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falcon->secret = (caps & 0x00000030) >> 4;
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}
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caps = nv_ro32(falcon, 0x108);
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falcon->code.limit = (caps & 0x000001ff) << 8;
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falcon->data.limit = (caps & 0x0003fe00) >> 1;
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nv_debug(falcon, "falcon version: %d\n", falcon->version);
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nv_debug(falcon, "secret level: %d\n", falcon->secret);
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nv_debug(falcon, "code limit: %d\n", falcon->code.limit);
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nv_debug(falcon, "data limit: %d\n", falcon->data.limit);
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/* wait for 'uc halted' to be signalled before continuing */
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if (falcon->secret) {
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nv_wait(falcon, 0x008, 0x00000010, 0x00000010);
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nv_wo32(falcon, 0x004, 0x00000010);
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}
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/* disable all interrupts */
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nv_wo32(falcon, 0x014, 0xffffffff);
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/* no default ucode provided by the engine implementation, try and
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* locate a "self-bootstrapping" firmware image for the engine
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*/
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if (!falcon->code.data) {
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, &device->pdev->dev);
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if (ret == 0) {
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falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
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falcon->code.size = fw->size;
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falcon->data.data = NULL;
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falcon->data.size = 0;
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release_firmware(fw);
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}
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falcon->external = true;
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}
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/* next step is to try and load "static code/data segment" firmware
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* images for the engine
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*/
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if (!falcon->code.data) {
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, &device->pdev->dev);
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if (ret) {
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nv_error(falcon, "unable to load firmware data\n");
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return ret;
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}
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falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
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falcon->data.size = fw->size;
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release_firmware(fw);
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if (!falcon->data.data)
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return -ENOMEM;
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, &device->pdev->dev);
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if (ret) {
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nv_error(falcon, "unable to load firmware code\n");
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return ret;
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}
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falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
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falcon->code.size = fw->size;
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release_firmware(fw);
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if (!falcon->code.data)
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return -ENOMEM;
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}
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nv_debug(falcon, "firmware: %s (%s)\n", name, falcon->data.data ?
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"static code/data segments" : "self-bootstrapping");
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/* ensure any "self-bootstrapping" firmware image is in vram */
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if (!falcon->data.data && !falcon->core) {
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ret = nouveau_gpuobj_new(object->parent, NULL,
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falcon->code.size, 256, 0,
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&falcon->core);
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if (ret) {
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nv_error(falcon, "core allocation failed, %d\n", ret);
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return ret;
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}
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for (i = 0; i < falcon->code.size; i += 4)
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nv_wo32(falcon->core, i, falcon->code.data[i / 4]);
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}
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/* upload firmware bootloader (or the full code segments) */
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if (falcon->core) {
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if (device->card_type < NV_C0)
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nv_wo32(falcon, 0x618, 0x04000000);
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else
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nv_wo32(falcon, 0x618, 0x00000114);
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nv_wo32(falcon, 0x11c, 0);
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nv_wo32(falcon, 0x110, falcon->core->addr >> 8);
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nv_wo32(falcon, 0x114, 0);
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nv_wo32(falcon, 0x118, 0x00006610);
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} else {
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if (falcon->code.size > falcon->code.limit ||
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falcon->data.size > falcon->data.limit) {
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nv_error(falcon, "ucode exceeds falcon limit(s)\n");
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return -EINVAL;
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}
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if (falcon->version < 3) {
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nv_wo32(falcon, 0xff8, 0x00100000);
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for (i = 0; i < falcon->code.size / 4; i++)
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nv_wo32(falcon, 0xff4, falcon->code.data[i]);
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} else {
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nv_wo32(falcon, 0x180, 0x01000000);
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for (i = 0; i < falcon->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wo32(falcon, 0x188, i >> 6);
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nv_wo32(falcon, 0x184, falcon->code.data[i]);
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}
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}
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}
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/* upload data segment (if necessary), zeroing the remainder */
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if (falcon->version < 3) {
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nv_wo32(falcon, 0xff8, 0x00000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nv_wo32(falcon, 0xff4, falcon->data.data[i]);
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for (; i < falcon->data.limit; i += 4)
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nv_wo32(falcon, 0xff4, 0x00000000);
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} else {
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nv_wo32(falcon, 0x1c0, 0x01000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nv_wo32(falcon, 0x1c4, falcon->data.data[i]);
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for (; i < falcon->data.limit / 4; i++)
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nv_wo32(falcon, 0x1c4, 0x00000000);
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}
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/* start it running */
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nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
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nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */
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nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */
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nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */
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return 0;
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}
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int
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_nouveau_falcon_fini(struct nouveau_object *object, bool suspend)
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{
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struct nouveau_falcon *falcon = (void *)object;
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if (!suspend) {
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nouveau_gpuobj_ref(NULL, &falcon->core);
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if (falcon->external) {
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kfree(falcon->data.data);
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kfree(falcon->code.data);
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falcon->code.data = NULL;
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}
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}
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nv_mo32(falcon, 0x048, 0x00000003, 0x00000000);
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nv_wo32(falcon, 0x014, 0xffffffff);
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return nouveau_engine_fini(&falcon->base, suspend);
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}
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int
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nouveau_falcon_create_(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, u32 addr, bool enable,
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const char *iname, const char *fname,
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int length, void **pobject)
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{
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struct nouveau_falcon *falcon;
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int ret;
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ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
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fname, length, pobject);
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falcon = *pobject;
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if (ret)
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return ret;
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falcon->addr = addr;
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return 0;
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}
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80
drivers/gpu/drm/nouveau/core/include/core/falcon.h
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80
drivers/gpu/drm/nouveau/core/include/core/falcon.h
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@ -0,0 +1,80 @@
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#ifndef __NOUVEAU_FALCON_H__
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#define __NOUVEAU_FALCON_H__
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#include <core/engine.h>
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#include <core/engctx.h>
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#include <core/gpuobj.h>
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struct nouveau_falcon_chan {
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struct nouveau_engctx base;
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};
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#define nouveau_falcon_context_create(p,e,c,g,s,a,f,d) \
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nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
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#define nouveau_falcon_context_destroy(d) \
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nouveau_engctx_destroy(&(d)->base)
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#define nouveau_falcon_context_init(d) \
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nouveau_engctx_init(&(d)->base)
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#define nouveau_falcon_context_fini(d,s) \
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nouveau_engctx_fini(&(d)->base, (s))
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#define _nouveau_falcon_context_dtor _nouveau_engctx_dtor
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#define _nouveau_falcon_context_init _nouveau_engctx_init
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#define _nouveau_falcon_context_fini _nouveau_engctx_fini
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#define _nouveau_falcon_context_rd32 _nouveau_engctx_rd32
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#define _nouveau_falcon_context_wr32 _nouveau_engctx_wr32
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struct nouveau_falcon_data {
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bool external;
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};
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struct nouveau_falcon {
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struct nouveau_engine base;
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u32 addr;
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u8 version;
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u8 secret;
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struct nouveau_gpuobj *core;
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bool external;
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struct {
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u32 limit;
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u32 *data;
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u32 size;
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} code;
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struct {
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u32 limit;
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u32 *data;
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u32 size;
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} data;
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};
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#define nv_falcon(priv) (&(priv)->base)
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#define nouveau_falcon_create(p,e,c,b,d,i,f,r) \
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nouveau_falcon_create_((p), (e), (c), (b), (d), (i), (f), \
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sizeof(**r),(void **)r)
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#define nouveau_falcon_destroy(p) \
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nouveau_engine_destroy(&(p)->base)
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#define nouveau_falcon_init(p) ({ \
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struct nouveau_falcon *falcon = (p); \
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_nouveau_falcon_init(nv_object(falcon)); \
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})
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#define nouveau_falcon_fini(p,s) ({ \
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struct nouveau_falcon *falcon = (p); \
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_nouveau_falcon_fini(nv_object(falcon), (s)); \
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})
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int nouveau_falcon_create_(struct nouveau_object *, struct nouveau_object *,
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struct nouveau_oclass *, u32, bool, const char *,
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const char *, int, void **);
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#define _nouveau_falcon_dtor _nouveau_engine_dtor
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int _nouveau_falcon_init(struct nouveau_object *);
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int _nouveau_falcon_fini(struct nouveau_object *, bool);
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u32 _nouveau_falcon_rd32(struct nouveau_object *, u64);
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void _nouveau_falcon_wr32(struct nouveau_object *, u64, u32);
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#endif
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