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drm/i915: Fix pixel clock and crtc clock config mismatch

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In case of dual link mode, the mode clock that we get
from the VBT is halved.

v2: Simplify the calculation (Jani).

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-4-git-send-email-vandita.kulkarni@intel.com
This commit is contained in:
Vandita Kulkarni 2019-05-02 20:41:02 +05:30 committed by Jani Nikula
parent 30bd7efdf6
commit e3c54da0fe
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/icl_dsi.c
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@ -1212,7 +1212,11 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
pipe_config->base.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);