iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Second Round of Renesas ARM Based SoC DT Updates for v4.4

Browse Source 
* Enable the following on the porter board:
   I2C2, PCI, PCIe, QSPI, SATA0, SDHI0/2, USB PHY and VIN0/ADV7180.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWHvNcAAoJENfPZGlqN0++J0EP+gMOFcFdLOqnnqDO75dV7Fey
 NsZJsOGU0avrrNwt0Q5LM8/jOinPShnTqoJcTMge1ErZTlBjdWMfCwmsttsvNu5G
 Oj9NALQx4824NnjjixwhJB1MTfH2JKcZWBmZylkEsiv+uA8domOFflaL7ZAJ+RER
 ZmoCrEWa6APQdrGnh8b43CKlFpxL6Zx3bKjPBo/z8NG6exhswMJXugkkSQMdRfxr
 utTcqD4sQ0V3JuQSBfYJeR4Z22vDYp+DtevqIkpaAdlhcJLM9lIaLnNujE9xqaoy
 L3ss3nROOqnQlTrTvifadB7fOG5ecs/5FD/N9QGj07Xfcx1DZrOqzGVaa8cMfS2a
 SmcOvLyYVafyNzyyAhhYj63/IzgUMoH1HEXZDX+x1yLgH8OlL9NG+HtuYARvFHFN
 yTXCXC524WC850PMFQ7MPuvl/axkpLU+g7cvhVZ/PKzG+VGckw6GWyxl2WCKcW/x
 7N6gD0IdF2g1WNl8vU3yOBDhIRb60CtjiuAEDN+X8GhMdaDfslqK7GGL5ulgkGrh
 owo7qUbvWry2TjowchszsDiW+0MtDsdKG3F1UISR+pN0D0JytRjqJW8aRnfX8oBc
 4S1oV9EaLddQd90nU+XL0Mcbu7txO7OKNvly2KeWHD2jDX+QJsZQ8PSwa2eTY8eD
 puv4pXOmwwnF9eJP+IXN
 =8OHS
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dt2-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.4" from Simon Horman:

* Enable the following on the porter board:
  I2C2, PCI, PCIe, QSPI, SATA0, SDHI0/2, USB PHY and VIN0/ADV7180.

* tag 'renesas-dt2-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: porter: enable internal PCI and USB PHY
  ARM: shmobile: porter: enable PCIe
  ARM: shmobile: porter: add QSPI DT support
  ARM: shmobile: porter: add VIN0/ADV7180 DT support
  ARM: shmobile: porter: add I2C2 DT support
  ARM: shmobile: porter: enable SATA0
  ARM: shmobile: porter: add SDHI0/2 DT support
This commit is contained in:
Arnd Bergmann 2015-10-15 17:18:49 +02:00
commit e3d05583a7
1 changed files with 202 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

202
arch/arm/boot/dts/r8a7791-porter.dts
View File

@ -10,6 +10,7 @@
/dts-v1/;
#include "r8a7791.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Porter";
@ -33,6 +34,50 @@
device_type = "memory";
reg = <2 0x00000000 0 0x40000000>;
};
vcc_sdhi0: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccq_sdhi0: regulator@1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi2: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccq_sdhi2: regulator@3 {
compatible = "regulator-gpio";
regulator-name = "SDHI2 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&extal_clk {
@ -54,6 +99,41 @@
renesas,groups = "intc_irq0";
renesas,function = "intc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
};
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
};
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
};
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
};
usb1_pins: usb1 {
renesas,groups = "usb1";
renesas,function = "usb1";
};
vin0_pins: vin0 {
renesas,groups = "vin0_data8", "vin0_clk";
renesas,function = "vin0";
};
};
&scif0 {
@ -78,3 +158,125 @@
micrel,led-mode = <1>;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
partition@0 {
label = "loader_prg";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "user_prg";
reg = <0x00040000 0x00400000>;
read-only;
};
partition@440000 {
label = "flash_fs";
reg = <0x00440000 0x03bc0000>;
};
};
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
};
&sata0 {
status = "okay";
};
/* composite video input */
&vin0 {
status = "ok";
pinctrl-0 = <&vin0_pins>;
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
};
};
};
&pci0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pci1 {
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
status = "okay";
};
&usbphy {
status = "okay";
};
&pcie_bus_clk {
status = "okay";
};
&pciec {
status = "okay";
};