Devicetree changes for omaps for v6.10
Update n900 charge limit, and make use of the clksel binding for dra7 for the clksel clocks and other dpll output related clocks. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmYp3y0RHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXPjUw/8CEk27NriuwwJ51pnDYL+kVMprTPvTRnn BPTXHduIIZjoKpSQxBoSx3vu/YklKPzrzng/OjyqLwINH228Edn4zufweuVRmHwa oXwQvnJyFoeKGjsMbUz57DThFosWUecWMpBUU3n/9/gZC64YAy4P5jXXJkAJXac4 iU4pfdZ3NuNW2Pv+g7DrUatvvqFPx8E2NvonMLVCUuZDxhQXo6XQQMNHrrLySPbq K45Z2864rj4Td2/T3X3GUVXbKI5xOZ63M2sVtYP5Z0UVBs+Ay3Rvj1YcELOWfPMi 17fzPd7sJ+wCPDFohF8UlpNEOns5m1KdTf1gRgPfB8vwQ/KghtOU7s+cTgeTJan3 nb1PuMcetRhJpAqmWPYhWPLRBNDjZEadp6pjNRRbABzO4uC1W4RhmrQ5lG5CBsHD SUF+snnLnQmmH7K3c+gtyyt/+Is0Ga2bq82Z/n4LvGsPk6pZScnMtxZJVEfJiknC ZEEA3t1F5HhzQaZaTx401Kwijj1oEg+54axjiL0ze9JLSL7NUMphCz6IJVKPOyNo WzH37RmwM/mFNAXbX317sJXERYdjY6wRY7lRPkLF19NP4CQkJ5/ckcYum4J8PmX9 RRpEhnMWl2Fsb7LmPYLH3/rIAUsa0aQ1jgY/wr4oVdHxs/Lf008Lc5S4zCklPAeV PXWGGMTLmxc= =+DGK -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYvWmwACgkQYKtH/8kJ Uic36w/+IKBMt8RR+lKWfY2Pn4QMjx4BgM68FoZ8fnC8BvX8jOaE66RpaxdZm/oC UAFsUPr/R232bBn4VzpjlsCUot0DoyEfucFO/Tvav9CukCL9bafMMYQ48fOpdK/h wYFBbohCDtdVIpqmXgEPcgyoC2WlyYlF19diM2OeFUidk/Yp/q6XTu8o5wxZ4I6i zM81BfN4zmnfogAr9N1Wkf8j3DQN1fXyHKVRHc5wRerMB0Y9jzggjdY0gSePvp2A Pc+BhXR17nSt+hnvuqR+ACIx1LPmO72O89RqIzthoEBhZwrboJNOCjR7+JF71kv+ On3dWm6rIkE9H+qj1fnVKD4H+QI9kIT6pijzBc3myH1LFsG6HL/ZUZjre1gY+XiX 3bfiwSBV495akdMToJdBy0sRezZJdfbAIpTurCJoDaTg8M7f8nCROVrftHXEPDDn RxT5USrW56/MsRoHT4gAxGDch8IWqmddgQ4v9sXa5QzomPPznLK9g3FRfdKrklbS OwHzX7nk7TeqHUrAIEcXeq0JcR5/4aTTg824dbg1D1EM8J8zwdMHE1nus6jLOpz9 XcoX6AqScW6xlBMZMmXpkSE0iE1kyCVuaDSgX4JXIfsAHKUsqOWzUSSOkntoTby+ rhDa5ofDrwhU/DvOyL/aIRH3+wErF6ZMNe4FmAr0Pcu2YA8JTEM= =jNDn -----END PGP SIGNATURE----- Merge tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt Devicetree changes for omaps for v6.10 Update n900 charge limit, and make use of the clksel binding for dra7 for the clksel clocks and other dpll output related clocks. * tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE ARM: dts: n900: set charge current limit to 950mA Link: https://lore.kernel.org/r/pull-1714020191-304166@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
e3edc3c8d8
arch/arm/boot/dts/ti/omap
@ -84,35 +84,44 @@
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};
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&scm_conf_clocks {
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dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_x2_ck>;
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ti,max-div = <63>;
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reg = <0x03fc>;
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ti,bit-shift = <20>;
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ti,latch-bit = <26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
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assigned-clock-rates = <80000000>;
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};
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dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
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/* CTRL_CORE_SMA_SW_0 */
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clock@3fc {
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compatible = "ti,clksel";
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reg = <0x3fc>;
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ti,bit-shift = <29>;
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ti,latch-bit = <26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
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};
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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mcan_clk: mcan_clk@3fc {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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ti,bit-shift = <27>;
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reg = <0x3fc>;
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dpll_gmac_h14x2_ctrl_ck: clock@20 {
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reg = <20>;
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clock-output-names = "dpll_gmac_h14x2_ctrl_ck";
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_x2_ck>;
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ti,max-div = <63>;
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ti,latch-bit = <26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
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assigned-clock-rates = <80000000>;
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#clock-cells = <0>;
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};
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mcan_clk: clock@27 {
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reg = <27>;
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clock-output-names = "mcan_clk";
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compatible = "ti,gate-clock";
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clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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#clock-cells = <0>;
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};
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dpll_gmac_h14x2_ctrl_mux_ck: clock@29 {
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reg = <29>;
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clock-output-names = "dpll_gmac_h14x2_ctrl_mux_ck";
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
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ti,latch-bit = <26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
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#clock-cells = <0>;
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};
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};
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};
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@ -285,13 +285,21 @@
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ti,invert-autoidle-bit;
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};
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dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_core_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x012c>;
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/* CM_CLKSEL_DPLL_CORE */
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clock@12c {
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compatible = "ti,clksel";
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reg = <0x12c>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_core_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_core_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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#clock-cells = <0>;
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};
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};
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dpll_core_ck: clock@120 {
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@ -368,13 +376,21 @@
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clock-div = <1>;
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};
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dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_dsp_byp_mux";
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clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
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ti,bit-shift = <23>;
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reg = <0x0240>;
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/* CM_CLKSEL_DPLL_DSP */
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clock@240 {
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compatible = "ti,clksel";
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reg = <0x240>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_dsp_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_dsp_byp_mux";
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clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
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#clock-cells = <0>;
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};
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};
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dpll_dsp_ck: clock@234 {
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@ -410,13 +426,21 @@
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clock-div = <1>;
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};
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dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_iva_byp_mux";
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clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
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ti,bit-shift = <23>;
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reg = <0x01ac>;
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/* CM_CLKSEL_DPLL_IVA */
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clock@1ac {
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compatible = "ti,clksel";
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reg = <0x1ac>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_iva_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_iva_byp_mux";
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clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
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#clock-cells = <0>;
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};
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};
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dpll_iva_ck: clock@1a0 {
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@ -452,13 +476,21 @@
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clock-div = <1>;
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};
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dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_gpu_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x02e4>;
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/* CM_CLKSEL_DPLL_GPU */
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clock@2e4 {
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compatible = "ti,clksel";
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reg = <0x2e4>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_gpu_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_gpu_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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#clock-cells = <0>;
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};
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};
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dpll_gpu_ck: clock@2d8 {
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@ -506,13 +538,21 @@
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clock-div = <1>;
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};
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dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_ddr_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x021c>;
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/* CM_CLKSEL_DPLL_DDR */
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clock@21c {
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compatible = "ti,clksel";
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reg = <0x21c>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_ddr_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_ddr_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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#clock-cells = <0>;
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};
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};
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dpll_ddr_ck: clock@210 {
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@ -535,13 +575,21 @@
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ti,invert-autoidle-bit;
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};
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dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_gmac_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x02b4>;
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/* CM_CLKSEL_DPLL_GMAC */
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clock@2b4 {
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compatible = "ti,clksel";
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reg = <0x2b4>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_gmac_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_gmac_byp_mux";
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clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
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#clock-cells = <0>;
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};
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};
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dpll_gmac_ck: clock@2a8 {
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@ -618,13 +666,21 @@
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clock-div = <1>;
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};
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dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_eve_byp_mux";
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clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
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ti,bit-shift = <23>;
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reg = <0x0290>;
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/* CM_CLKSEL_DPLL_EVE */
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clock@290 {
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compatible = "ti,clksel";
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reg = <0x290>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dpll_eve_byp_mux: clock@23 {
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reg = <23>;
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compatible = "ti,mux-clock";
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clock-output-names = "dpll_eve_byp_mux";
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clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
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#clock-cells = <0>;
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};
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};
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dpll_eve_ck: clock@284 {
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@ -838,15 +894,23 @@
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clock-div = <1>;
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};
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l3_iclk_div: clock-l3-iclk-div-4@100 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "l3_iclk_div";
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ti,max-div = <2>;
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ti,bit-shift = <4>;
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reg = <0x0100>;
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clocks = <&dpll_core_h12x2_ck>;
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ti,index-power-of-two;
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/* CM_CLKSEL_CORE */
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clock@100 {
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compatible = "ti,clksel";
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reg = <0x100>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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l3_iclk_div: clock@4 {
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reg = <4>;
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compatible = "ti,divider-clock";
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clock-output-names = "l3_iclk_div";
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ti,max-div = <2>;
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clocks = <&dpll_core_h12x2_ck>;
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ti,index-power-of-two;
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#clock-cells = <0>;
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};
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};
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l4_root_clk_div: clock-l4-root-clk-div {
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@ -911,12 +975,21 @@
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ti,index-starts-at-one;
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};
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abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "abe_dpll_sys_clk_mux";
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clocks = <&sys_clkin1>, <&sys_clkin2>;
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reg = <0x0118>;
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/* CM_CLKSEL_ABE_PLL_SYS */
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clock@118 {
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compatible = "ti,clksel";
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reg = <0x118>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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abe_dpll_sys_clk_mux: clock@0 {
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reg = <0>;
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compatible = "ti,mux-clock";
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clock-output-names = "abe_dpll_sys_clk_mux";
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clocks = <&sys_clkin1>, <&sys_clkin2>;
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#clock-cells = <0>;
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};
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};
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abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
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@ -1018,14 +1091,23 @@
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ti,index-power-of-two;
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};
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dsp_gclk_div: clock-dsp-gclk-div@18c {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clock-output-names = "dsp_gclk_div";
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clocks = <&dpll_dsp_m2_ck>;
|
||||
ti,max-div = <64>;
|
||||
reg = <0x018c>;
|
||||
ti,index-power-of-two;
|
||||
/* CM_CLKSEL_DPLL_USB */
|
||||
clock@18c {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x18c>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dsp_gclk_div: clock@0 {
|
||||
reg = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clock-output-names = "dsp_gclk_div";
|
||||
clocks = <&dpll_dsp_m2_ck>;
|
||||
ti,max-div = <64>;
|
||||
ti,index-power-of-two;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu_dclk: clock-gpu-dclk@1a0 {
|
||||
@ -1326,13 +1408,21 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "dpll_per_byp_mux";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x014c>;
|
||||
/* CM_CLKSEL_DPLL_PER */
|
||||
clock@14c {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x14c>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dpll_per_byp_mux: clock@23 {
|
||||
reg = <23>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "dpll_per_byp_mux";
|
||||
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dpll_per_ck: clock@140 {
|
||||
@ -1364,13 +1454,21 @@
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "dpll_usb_byp_mux";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x018c>;
|
||||
/* CM_CLKSEL_DPLL_USB */
|
||||
clock@18c {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x18c>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dpll_usb_byp_mux: clock@23 {
|
||||
reg = <23>;
|
||||
compatible = "ti,mux-clock";
|
||||
clock-output-names = "dpll_usb_byp_mux";
|
||||
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dpll_usb_ck: clock@180 {
|
||||
|
||||
@ -754,7 +754,7 @@
|
||||
ti,current-limit = <100>;
|
||||
ti,weak-battery-voltage = <3400>;
|
||||
ti,battery-regulation-voltage = <4200>;
|
||||
ti,charge-current = <650>;
|
||||
ti,charge-current = <950>;
|
||||
ti,termination-current = <100>;
|
||||
ti,resistor-sense = <68>;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user