clk: samsung: fsd: Add cmu_peric block clock information
Add CMU_PERIC block clock information needed for various IPs functions found in this block. Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com> Signed-off-by: Chandrasekar R <rcsekar@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Sriranjani P <sriranjani.p@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-6-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Alim Akhtar
Krzysztof Kozlowski
parent
4f346005aa
commit
e3f3dc3810
@ -8,14 +8,19 @@
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* Common Clock Framework support for FSD SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/fsd-clk.h>
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#include "clk.h"
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#include "clk-exynos-arm64.h"
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/* Register Offset definitions for CMU_CMU (0x11c10000) */
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#define PLL_LOCKTIME_PLL_SHARED0 0x0
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@ -308,3 +313,403 @@ static void __init fsd_clk_cmu_init(struct device_node *np)
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}
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CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
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/* Register Offset definitions for CMU_PERIC (0x14010000) */
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#define PLL_CON0_PERIC_DMACLK_MUX 0x100
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#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
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#define PLL_CON0_PERIC_PCLK_MUX 0x140
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#define PLL_CON0_PERIC_TBUCLK_MUX 0x160
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#define PLL_CON0_SPI_CLK 0x180
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#define PLL_CON0_SPI_PCLK 0x1a0
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#define PLL_CON0_UART_CLK 0x1c0
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#define PLL_CON0_UART_PCLK 0x1e0
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#define MUX_PERIC_EQOS_PHYRXCLK 0x1000
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#define DIV_EQOS_BUSCLK 0x1800
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#define DIV_PERIC_MCAN_CLK 0x1804
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#define DIV_RGMII_CLK 0x1808
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#define DIV_RII_CLK 0x180c
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#define DIV_RMII_CLK 0x1810
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#define DIV_SPI_CLK 0x1814
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#define DIV_UART_CLK 0x1818
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#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
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#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
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#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
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#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
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#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
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#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
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#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
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#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
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#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
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#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
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#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
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#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
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#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
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#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
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#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
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#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
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#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
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#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
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#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
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#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
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#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
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#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
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#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
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#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
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#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
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#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
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#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
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#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
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#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
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#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
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#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
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#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
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#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
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#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
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#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
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#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
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#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
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#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
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#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
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#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
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#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
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#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
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#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
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#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
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#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
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#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
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#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
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#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
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#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
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#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
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#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
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#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
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#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
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#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
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#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
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#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
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#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
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#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
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#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
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#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
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#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
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#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
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#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
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#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
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#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
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#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
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static const unsigned long peric_clk_regs[] __initconst = {
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PLL_CON0_PERIC_DMACLK_MUX,
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PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
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PLL_CON0_PERIC_PCLK_MUX,
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PLL_CON0_PERIC_TBUCLK_MUX,
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PLL_CON0_SPI_CLK,
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PLL_CON0_SPI_PCLK,
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PLL_CON0_UART_CLK,
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PLL_CON0_UART_PCLK,
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MUX_PERIC_EQOS_PHYRXCLK,
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DIV_EQOS_BUSCLK,
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DIV_PERIC_MCAN_CLK,
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DIV_RGMII_CLK,
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DIV_RII_CLK,
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DIV_RMII_CLK,
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DIV_SPI_CLK,
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DIV_UART_CLK,
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GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
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GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
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GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
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GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
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GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
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GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
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GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
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GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
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GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
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GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
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GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
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GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
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GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
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GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
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GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
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GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
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GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
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GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
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GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
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GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
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GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
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GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
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GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
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GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
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GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
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GAT_GPIO_PERIC_IPCLKPORT_PCLK,
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GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
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GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
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GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
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GAT_PERIC_DMA0_IPCLKPORT_ACLK,
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GAT_PERIC_DMA1_IPCLKPORT_ACLK,
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GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
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GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
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GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
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GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
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GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
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GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
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GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
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GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
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GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
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GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
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GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
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GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
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GAT_PERIC_SMMU_IPCLKPORT_CCLK,
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GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
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GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
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GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
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GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
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GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
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GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
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GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
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GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
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GAT_PERIC_TDM0_IPCLKPORT_PCLK,
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GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
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GAT_PERIC_TDM1_IPCLKPORT_PCLK,
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GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
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GAT_PERIC_UART0_IPCLKPORT_PCLK,
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GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
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GAT_PERIC_UART1_IPCLKPORT_PCLK,
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GAT_SYSREG_PERI_IPCLKPORT_PCLK,
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};
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static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
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FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
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};
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/* List of parent clocks for Muxes in CMU_PERIC */
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PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
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PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
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PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
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PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
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PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
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PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
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PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
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PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
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PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
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static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
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MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
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MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
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PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
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MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
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MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
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MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
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MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
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MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
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MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
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MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
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MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
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};
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static const struct samsung_div_clock peric_div_clks[] __initconst = {
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DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
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DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
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DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
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DIV_RGMII_CLK, 0, 4),
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DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
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DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
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DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
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DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
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};
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static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
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GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
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"fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
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21, CLK_IGNORE_UNUSED, 0),
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GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
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GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
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GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
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CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
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GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
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GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
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GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
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GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
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GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
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GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
|
||||
GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
|
||||
GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
|
||||
GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
|
||||
"dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
|
||||
GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
|
||||
"dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
|
||||
GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
|
||||
GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
|
||||
"dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
|
||||
"mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
|
||||
"dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
|
||||
"dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
|
||||
GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
|
||||
GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
|
||||
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
|
||||
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
|
||||
GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
|
||||
GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
|
||||
GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
|
||||
GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
|
||||
GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
|
||||
GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
|
||||
GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
|
||||
GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
|
||||
GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
|
||||
GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
|
||||
GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
|
||||
GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
|
||||
GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
|
||||
GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
|
||||
GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
|
||||
GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
|
||||
GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
|
||||
GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
|
||||
GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
|
||||
GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
|
||||
GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
|
||||
GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
|
||||
GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
|
||||
GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peric_cmu_info __initconst = {
|
||||
.mux_clks = peric_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric_mux_clks),
|
||||
.div_clks = peric_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(peric_div_clks),
|
||||
.gate_clks = peric_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
|
||||
.fixed_clks = peric_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
|
||||
.nr_clk_ids = PERIC_NR_CLK,
|
||||
.clk_regs = peric_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
|
||||
.clk_name = "dout_cmu_pll_shared0_div4",
|
||||
};
|
||||
|
||||
/**
|
||||
* fsd_cmu_probe - Probe function for FSD platform clocks
|
||||
* @pdev: Pointer to platform device
|
||||
*
|
||||
* Configure clock hierarchy for clock domains of FSD platform
|
||||
*/
|
||||
static int __init fsd_cmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct samsung_cmu_info *info;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
exynos_arm64_register_cmu(dev, dev->of_node, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* CMUs which belong to Power Domains and need runtime PM to be implemented */
|
||||
static const struct of_device_id fsd_cmu_of_match[] = {
|
||||
{
|
||||
.compatible = "tesla,fsd-clock-peric",
|
||||
.data = &peric_cmu_info,
|
||||
}, {
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_driver fsd_cmu_driver __refdata = {
|
||||
.driver = {
|
||||
.name = "fsd-cmu",
|
||||
.of_match_table = fsd_cmu_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = fsd_cmu_probe,
|
||||
};
|
||||
|
||||
static int __init fsd_cmu_init(void)
|
||||
{
|
||||
return platform_driver_register(&fsd_cmu_driver);
|
||||
}
|
||||
core_initcall(fsd_cmu_init);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user