drm/i915/pvc: Add new BCS engines to GuC engine list
Initialize ADS system info to reflect the availability of new BCS engines Original-author: CQ Tang Cc: Stuart Summers <stuart.summers@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220511060228.1179450-5-matthew.d.roper@intel.com
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@ -457,7 +457,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
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{
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info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt));
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info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt));
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info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
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info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
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info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
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info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
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}
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@ -1223,6 +1223,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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})
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#define RCS_MASK(gt) \
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ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
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#define BCS_MASK(gt) \
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ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
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#define VDBOX_MASK(gt) \
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ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
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#define VEBOX_MASK(gt) \
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