Second Round of Renesas ARM Based SoC DT Updates for v3.20
* Support Renesas memory controllers * Add SRC interrupt number on r8a779~ and r8a7791 SoCs * Fix MSTP8 input clocks on r8a7791 SoC * Add PM domain support to r8a7740 * Add DT bindings for the R-Mobile System Controller * Use Add sh73a0-specific FSI2 compatible property -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUuIxcAAoJENfPZGlqN0++8e0P/jWtO7tWT3p/ToEvUrVNWMI+ f3yztJa2dgLocJlRMfxMkmNUKGAGIa2B6emfYwBAXxRXEnXt4JPcjCkdiOBD+Ivm +sW9MxBWGKNu70dh8+iw4gif1Ii0Xf95t5RFs3MWuCjg4/94X6cafUFa9+plTHzt ENNlDunuyJzO/dUd52nC2cHlpRNHpQtmMm56KvEJwZdy/NvH3XJLEXNEtJFcIEqp lRzJeMPN+7iFDpZz3LHn4fMFJG1B+fQJcA1qTFKU+BWP15Sh7xzJJP2UJNT+jL2a 5sHcxWPmY0vhD8iZKqE6Cuk34SaToGBa/yGHIXKUx6jzU2hYEL7qhhCxkaqkt8Hc l+zlZ4WLCKXGdJ9jbq2rpRj5SylJixbF7wN/ojqiUfnMcy5B6+gJd6nsba4h6MUj OkDwmvcWMNGc5EXuVfsVbvM7Ue2MUQLbvzyrkxse4vEZOsNMiAmdsy165TD5tTKL fd3427ALhJV6Wjcym3VCj/2yAvjz8QhgKYmxHdohu0hO0fQ3bUpjOE8OMq4qdR45 SWeyzsih9m7QPXM4Mik3iPbooXs4J31qnwfHgCPCvWRpG8o8BIl2iTl8X49Wa5mZ dS30WxMluvhxWWBnoUAL1TOnRnDcb3hoZ59fMVA389k6BZvVOZquas5ShuugKm3D OSiCOqapvBRGLpSVhp2O =wr62 -----END PGP SIGNATURE----- Merge tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.20" from Simon Horman: * Support Renesas memory controllers * Add SRC interrupt number on r8a779~ and r8a7791 SoCs * Fix MSTP8 input clocks on r8a7791 SoC * Add PM domain support to r8a7740 * Add DT bindings for the R-Mobile System Controller * Use Add sh73a0-specific FSI2 compatible property * tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: PM / Domains: R-Mobile SYSC: Document SH-Mobile AG5 (sh73a0) binding ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes ARM: shmobile: r8a7740 dtsi: Add memory-controller node ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes ARM: shmobile: Add DT bindings for Renesas memory controllers ARM: shmobile: r8a7791: add SRC interrupt number on DTSI ARM: shmobile: r8a7790: add SRC interrupt number on DTSI ARM: shmobile: r8a7791: fix MSTP8 input clocks ARM: shmobile: r8a7740 dtsi: Add PM domain support PM / Domains: Add DT bindings for the R-Mobile System Controller ARM: shmobile: sh73a0 dtsi: Add SoC-specific FSI2 compatible property Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
e42da8a146
@ -0,0 +1,44 @@
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DT bindings for Renesas R-Mobile and SH-Mobile memory controllers
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=================================================================
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Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.
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These memory controllers differ from one SoC variant to another, and are called
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by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
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(DBSC3)", "SDRAM Bus State Controller (SBSC)").
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Currently memory controller device nodes are used only to reference PM
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domains, and prevent these PM domains from being powered down, which would
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crash the system.
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As there exist no actual drivers for these controllers yet, these bindings
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should be considered EXPERIMENTAL for now.
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Required properties:
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- compatible: Must be one of the following SoC-specific values:
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- "renesas,dbsc-r8a73a4" (R-Mobile APE6)
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- "renesas,dbsc3-r8a7740" (R-Mobile A1)
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- "renesas,sbsc-sh73a0" (SH-Mobile AG5)
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- reg: Must contain the base address and length of the memory controller's
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registers.
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Optional properties:
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- interrupts: Must contain a list of interrupt specifiers for memory
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controller interrupts, if available.
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- interrupts-names: Must contain a list of interrupt names corresponding to
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the interrupts in the interrupts property, if available.
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Valid interrupt names are:
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- "sec" (secure interrupt)
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- "temp" (normal (temperature) interrupt)
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- power-domains: Must contain a reference to the PM domain that the memory
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controller belongs to, if available.
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Example:
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sbsc1: memory-controller@fe400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfe400000 0x400>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc0>;
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};
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@ -0,0 +1,99 @@
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DT bindings for the Renesas R-Mobile System Controller
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== System Controller Node ==
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The R-Mobile System Controller provides the following functions:
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- Boot mode management,
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- Reset generation,
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- Power management.
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Required properties:
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- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
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fallback.
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Examples with soctypes are:
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- "renesas,sysc-r8a7740" (R-Mobile A1)
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- "renesas,sysc-sh73a0" (SH-Mobile AG5)
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- reg: Two address start and address range blocks for the device:
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- The first block refers to the normally accessible registers,
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- the second block refers to the registers protected by the HPB
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semaphore.
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Optional nodes:
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- pm-domains: This node contains a hierarchy of PM domain nodes, which should
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match the Power Area Hierarchy in the Power Domain Specifications section of
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the device's datasheet.
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== PM Domain Nodes ==
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Each of the PM domain nodes represents a PM domain, as documented by the
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generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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The nodes should be named by the real power area names, and thus their names
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should be unique.
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Required properties:
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- #power-domain-cells: Must be 0.
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Optional properties:
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- reg: If the PM domain is not always-on, this property must contain the bit
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index number for the corresponding power area in the various Power
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Control and Status Registers. The parent's node must contain the
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following two properties:
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- #address-cells: Must be 1,
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- #size-cells: Must be 0.
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If the PM domain is always-on, this property must be omitted.
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Example:
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This shows a subset of the r8a7740 PM domain hierarchy, containing the
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C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain,
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which is a subdomain of A4S.
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sysc: system-controller@e6180000 {
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compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
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reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
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pm-domains {
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pd_c5: c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a4s: a4s@10 {
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reg = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3sp: a3sp@11 {
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reg = <11>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4su: a4su@20 {
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reg = <20>;
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#power-domain-cells = <0>;
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};
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};
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};
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};
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== PM Domain Consumers ==
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Hardware blocks belonging to a PM domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding PM domain node.
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Example:
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
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power-domains = <&pd_a3sp>;
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#pwm-cells = <3>;
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};
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@ -38,6 +38,16 @@
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<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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dbsc1: memory-controller@e6790000 {
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compatible = "renesas,dbsc-r8a73a4";
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reg = <0 0xe6790000 0 0x10000>;
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};
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dbsc2: memory-controller@e67a0000 {
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compatible = "renesas,dbsc-r8a73a4";
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reg = <0 0xe67a0000 0 0x10000>;
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};
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dmac: dma-multiplexer {
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compatible = "renesas,shdma-mux";
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#dma-cells = <1>;
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@ -25,6 +25,7 @@
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device_type = "cpu";
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reg = <0x0>;
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clock-frequency = <800000000>;
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power-domains = <&pd_a3sm>;
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};
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};
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@ -36,17 +37,29 @@
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<0xc2000000 0x1000>;
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};
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dbsc3: memory-controller@fe400000 {
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compatible = "renesas,dbsc3-r8a7740";
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reg = <0xfe400000 0x400>;
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power-domains = <&pd_a4s>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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ptm {
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compatible = "arm,coresight-etm3x";
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power-domains = <&pd_d4>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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renesas,channels-mask = <0x3f>;
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@ -72,6 +85,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin1: IRQ8 - IRQ15 */
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@ -93,6 +107,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin2: IRQ16 - IRQ23 */
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@ -114,6 +129,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin3: IRQ24 - IRQ31 */
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@ -135,6 +151,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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ether: ethernet@e9a00000 {
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@ -143,6 +160,7 @@
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<0xe9a01800 0x800>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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power-domains = <&pd_a4s>;
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -159,6 +177,7 @@
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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power-domains = <&pd_a4r>;
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status = "disabled";
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};
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@ -172,6 +191,7 @@
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -181,6 +201,7 @@
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -190,6 +211,7 @@
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interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -199,6 +221,7 @@
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interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -208,6 +231,7 @@
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -217,6 +241,7 @@
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -226,6 +251,7 @@
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -235,6 +261,7 @@
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -244,6 +271,7 @@
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -253,6 +281,7 @@
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -271,12 +300,14 @@
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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power-domains = <&pd_c5>;
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};
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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@ -287,6 +318,7 @@
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -297,6 +329,7 @@
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -309,6 +342,7 @@
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -321,6 +355,7 @@
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -332,6 +367,7 @@
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reg = <0xfe1f0000 0x400>;
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interrupts = <0 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>;
|
||||
power-domains = <&pd_a4mp>;
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status = "disabled";
|
||||
};
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||||
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||||
@ -343,6 +379,7 @@
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<0 200 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&pd_a4r>;
|
||||
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||||
#renesas,channels = <3>;
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||||
|
||||
@ -357,6 +394,7 @@
|
||||
<0 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&pd_a4r>;
|
||||
|
||||
#renesas,channels = <3>;
|
||||
|
||||
@ -543,4 +581,71 @@
|
||||
"usbhost", "sdhi2", "usbfunc", "usphy";
|
||||
};
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
|
||||
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
|
||||
|
||||
pm-domains {
|
||||
pd_c5: c5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a4lc: a4lc@1 {
|
||||
reg = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a4mp: a4mp@2 {
|
||||
reg = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_d4: d4@3 {
|
||||
reg = <3>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a4r: a4r@5 {
|
||||
reg = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a3rv: a3rv@6 {
|
||||
reg = <6>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a4s: a4s@10 {
|
||||
reg = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_a3sp: a3sp@11 {
|
||||
reg = <11>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3sm: a3sm@12 {
|
||||
reg = <12>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_a3sg: a3sg@13 {
|
||||
reg = <13>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pd_a4su: a4su@20 {
|
||||
reg = <20>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1440,16 +1440,16 @@
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src0: src@0 { };
|
||||
src1: src@1 { };
|
||||
src2: src@2 { };
|
||||
src3: src@3 { };
|
||||
src4: src@4 { };
|
||||
src5: src@5 { };
|
||||
src6: src@6 { };
|
||||
src7: src@7 { };
|
||||
src8: src@8 { };
|
||||
src9: src@9 { };
|
||||
src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
|
||||
@ -1154,7 +1154,7 @@
|
||||
mstp8_clks: mstp8_clks@e6150990 {
|
||||
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
||||
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
|
||||
clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
|
||||
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
@ -1425,16 +1425,16 @@
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src0: src@0 { };
|
||||
src1: src@1 { };
|
||||
src2: src@2 { };
|
||||
src3: src@3 { };
|
||||
src4: src@4 { };
|
||||
src5: src@5 { };
|
||||
src6: src@6 { };
|
||||
src7: src@7 { };
|
||||
src8: src@8 { };
|
||||
src9: src@9 { };
|
||||
src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
|
||||
@ -42,6 +42,22 @@
|
||||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
sbsc2: memory-controller@fb400000 {
|
||||
compatible = "renesas,sbsc-sh73a0";
|
||||
reg = <0xfb400000 0x400>;
|
||||
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sec", "temp";
|
||||
};
|
||||
|
||||
sbsc1: memory-controller@fe400000 {
|
||||
compatible = "renesas,sbsc-sh73a0";
|
||||
reg = <0xfe400000 0x400>;
|
||||
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sec", "temp";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -317,7 +333,7 @@
|
||||
|
||||
sh_fsi2: sound@ec230000 {
|
||||
#sound-dai-cells = <1>;
|
||||
compatible = "renesas,sh_fsi2";
|
||||
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
|
||||
reg = <0xec230000 0x400>;
|
||||
interrupts = <0 146 0x4>;
|
||||
status = "disabled";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user