staging/rdma/hfi1: Add braces on all arms of statement
Add braces on all arms of statements to fix checkpatch check: CHECK: braces {} should be used on all arms of this statement Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
parent
17fb4f2923
commit
e490974e67
@ -13829,9 +13829,9 @@ int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey)
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int ret = 0;
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int ret = 0;
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u64 reg;
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u64 reg;
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if (ctxt < dd->num_rcv_contexts)
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if (ctxt < dd->num_rcv_contexts) {
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rcd = dd->rcd[ctxt];
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rcd = dd->rcd[ctxt];
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else {
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} else {
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ret = -EINVAL;
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ret = -EINVAL;
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goto done;
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goto done;
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}
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}
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@ -13857,9 +13857,9 @@ int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt)
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int ret = 0;
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int ret = 0;
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u64 reg;
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u64 reg;
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if (ctxt < dd->num_rcv_contexts)
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if (ctxt < dd->num_rcv_contexts) {
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rcd = dd->rcd[ctxt];
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rcd = dd->rcd[ctxt];
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else {
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} else {
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ret = -EINVAL;
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ret = -EINVAL;
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goto done;
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goto done;
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}
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}
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@ -302,9 +302,9 @@ static void rcv_hdrerr(struct hfi1_ctxtdata *rcd, struct hfi1_pportdata *ppd,
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goto drop;
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goto drop;
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/* Check for GRH */
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/* Check for GRH */
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if (lnh == HFI1_LRH_BTH)
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if (lnh == HFI1_LRH_BTH) {
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ohdr = &hdr->u.oth;
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ohdr = &hdr->u.oth;
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else if (lnh == HFI1_LRH_GRH) {
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} else if (lnh == HFI1_LRH_GRH) {
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u32 vtf;
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u32 vtf;
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ohdr = &hdr->u.l.oth;
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ohdr = &hdr->u.l.oth;
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@ -314,9 +314,9 @@ static void rcv_hdrerr(struct hfi1_ctxtdata *rcd, struct hfi1_pportdata *ppd,
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if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
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if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
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goto drop;
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goto drop;
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rcv_flags |= HFI1_HAS_GRH;
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rcv_flags |= HFI1_HAS_GRH;
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} else
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} else {
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goto drop;
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goto drop;
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}
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/* Get the destination QP number. */
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/* Get the destination QP number. */
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qp_num = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK;
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qp_num = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK;
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if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) {
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if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) {
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@ -618,14 +618,14 @@ static void __prescan_rxq(struct hfi1_packet *packet)
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hfi1_get_msgheader(dd, rhf_addr);
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hfi1_get_msgheader(dd, rhf_addr);
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lnh = be16_to_cpu(hdr->lrh[0]) & 3;
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lnh = be16_to_cpu(hdr->lrh[0]) & 3;
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if (lnh == HFI1_LRH_BTH)
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if (lnh == HFI1_LRH_BTH) {
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ohdr = &hdr->u.oth;
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ohdr = &hdr->u.oth;
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else if (lnh == HFI1_LRH_GRH) {
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} else if (lnh == HFI1_LRH_GRH) {
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ohdr = &hdr->u.l.oth;
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ohdr = &hdr->u.l.oth;
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grh = &hdr->u.l.grh;
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grh = &hdr->u.l.grh;
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} else
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} else {
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goto next; /* just in case */
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goto next; /* just in case */
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}
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bth1 = be32_to_cpu(ohdr->bth[1]);
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bth1 = be32_to_cpu(ohdr->bth[1]);
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is_ecn = !!(bth1 & (HFI1_FECN_SMASK | HFI1_BECN_SMASK));
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is_ecn = !!(bth1 & (HFI1_FECN_SMASK | HFI1_BECN_SMASK));
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@ -399,8 +399,9 @@ static ssize_t hfi1_file_write(struct file *fp, const char __user *data,
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ret = sc_enable(sc);
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ret = sc_enable(sc);
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hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_ENB,
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hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_ENB,
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uctxt->ctxt);
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uctxt->ctxt);
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} else
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} else {
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ret = sc_restart(sc);
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ret = sc_restart(sc);
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}
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if (!ret)
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if (!ret)
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sc_return_credits(sc);
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sc_return_credits(sc);
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break;
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break;
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@ -1409,8 +1410,9 @@ static unsigned int poll_next(struct file *fp,
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set_bit(HFI1_CTXT_WAITING_RCV, &uctxt->event_flags);
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set_bit(HFI1_CTXT_WAITING_RCV, &uctxt->event_flags);
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hfi1_rcvctrl(dd, HFI1_RCVCTRL_INTRAVAIL_ENB, uctxt->ctxt);
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hfi1_rcvctrl(dd, HFI1_RCVCTRL_INTRAVAIL_ENB, uctxt->ctxt);
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pollflag = 0;
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pollflag = 0;
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} else
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} else {
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pollflag = POLLIN | POLLRDNORM;
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pollflag = POLLIN | POLLRDNORM;
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}
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spin_unlock_irq(&dd->uctxt_lock);
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spin_unlock_irq(&dd->uctxt_lock);
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return pollflag;
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return pollflag;
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@ -1488,8 +1490,9 @@ static int manage_rcvq(struct hfi1_ctxtdata *uctxt, unsigned subctxt,
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if (uctxt->rcvhdrtail_kvaddr)
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if (uctxt->rcvhdrtail_kvaddr)
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clear_rcvhdrtail(uctxt);
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clear_rcvhdrtail(uctxt);
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rcvctrl_op = HFI1_RCVCTRL_CTXT_ENB;
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rcvctrl_op = HFI1_RCVCTRL_CTXT_ENB;
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} else
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} else {
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rcvctrl_op = HFI1_RCVCTRL_CTXT_DIS;
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rcvctrl_op = HFI1_RCVCTRL_CTXT_DIS;
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}
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hfi1_rcvctrl(dd, rcvctrl_op, uctxt->ctxt);
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hfi1_rcvctrl(dd, rcvctrl_op, uctxt->ctxt);
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/* always; new head should be equal to new tail; see above */
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/* always; new head should be equal to new tail; see above */
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bail:
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bail:
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@ -1713,9 +1713,10 @@ int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
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rcd->egrbufs.buffers[j].len)) {
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rcd->egrbufs.buffers[j].len)) {
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j++;
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j++;
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offset = 0;
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offset = 0;
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} else
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} else {
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offset += new_size;
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offset += new_size;
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}
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}
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}
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rcd->egrbufs.rcvtid_size = new_size;
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rcd->egrbufs.rcvtid_size = new_size;
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}
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}
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}
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}
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@ -135,15 +135,16 @@ static void send_trap(struct hfi1_ibport *ibp, void *data, unsigned len)
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struct ib_ah *ah;
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struct ib_ah *ah;
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ah = hfi1_create_qp0_ah(ibp, ibp->rvp.sm_lid);
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ah = hfi1_create_qp0_ah(ibp, ibp->rvp.sm_lid);
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if (IS_ERR(ah))
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if (IS_ERR(ah)) {
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ret = PTR_ERR(ah);
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ret = PTR_ERR(ah);
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else {
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} else {
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send_buf->ah = ah;
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send_buf->ah = ah;
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ibp->rvp.sm_ah = ibah_to_rvtah(ah);
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ibp->rvp.sm_ah = ibah_to_rvtah(ah);
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ret = 0;
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ret = 0;
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}
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}
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} else
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} else {
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ret = -EINVAL;
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ret = -EINVAL;
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}
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} else {
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} else {
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send_buf->ah = &ibp->rvp.sm_ah->ibah;
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send_buf->ah = &ibp->rvp.sm_ah->ibah;
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ret = 0;
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ret = 0;
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@ -769,9 +770,9 @@ static int __subn_get_opa_pkeytable(struct opa_smp *smp, u32 am, u8 *data,
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p[i] = cpu_to_be16(q[i]);
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p[i] = cpu_to_be16(q[i]);
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if (resp_len)
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if (resp_len)
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*resp_len += size;
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*resp_len += size;
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} else
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} else {
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smp->status |= IB_SMP_INVALID_FIELD;
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smp->status |= IB_SMP_INVALID_FIELD;
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}
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return reply((struct ib_mad_hdr *)smp);
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return reply((struct ib_mad_hdr *)smp);
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}
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}
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@ -977,15 +978,15 @@ static int set_port_states(struct hfi1_pportdata *ppd, struct opa_smp *smp,
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break;
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break;
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/* FALLTHROUGH */
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/* FALLTHROUGH */
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case IB_PORT_DOWN:
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case IB_PORT_DOWN:
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if (phys_state == IB_PORTPHYSSTATE_NOP)
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if (phys_state == IB_PORTPHYSSTATE_NOP) {
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link_state = HLS_DN_DOWNDEF;
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link_state = HLS_DN_DOWNDEF;
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else if (phys_state == IB_PORTPHYSSTATE_POLLING) {
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} else if (phys_state == IB_PORTPHYSSTATE_POLLING) {
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link_state = HLS_DN_POLL;
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link_state = HLS_DN_POLL;
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set_link_down_reason(ppd, OPA_LINKDOWN_REASON_FM_BOUNCE,
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set_link_down_reason(ppd, OPA_LINKDOWN_REASON_FM_BOUNCE,
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0, OPA_LINKDOWN_REASON_FM_BOUNCE);
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0, OPA_LINKDOWN_REASON_FM_BOUNCE);
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} else if (phys_state == IB_PORTPHYSSTATE_DISABLED)
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} else if (phys_state == IB_PORTPHYSSTATE_DISABLED) {
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link_state = HLS_DN_DISABLE;
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link_state = HLS_DN_DISABLE;
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else {
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} else {
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pr_warn("SubnSet(OPA_PortInfo) invalid physical state 0x%x\n",
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pr_warn("SubnSet(OPA_PortInfo) invalid physical state 0x%x\n",
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phys_state);
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phys_state);
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smp->status |= IB_SMP_INVALID_FIELD;
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smp->status |= IB_SMP_INVALID_FIELD;
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@ -1193,9 +1194,9 @@ static int __subn_set_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
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set_link_width_downgrade_enabled(ppd, lwe);
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set_link_width_downgrade_enabled(ppd, lwe);
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call_link_downgrade_policy = 1;
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call_link_downgrade_policy = 1;
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}
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}
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} else
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} else {
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smp->status |= IB_SMP_INVALID_FIELD;
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smp->status |= IB_SMP_INVALID_FIELD;
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}
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lse = be16_to_cpu(pi->link_speed.enabled);
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lse = be16_to_cpu(pi->link_speed.enabled);
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if (lse) {
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if (lse) {
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if (lse & be16_to_cpu(pi->link_speed.supported))
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if (lse & be16_to_cpu(pi->link_speed.supported))
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@ -123,8 +123,9 @@ int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto bail;
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goto bail;
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}
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}
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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} else
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} else {
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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}
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if (ret) {
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if (ret) {
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hfi1_early_err(&pdev->dev,
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hfi1_early_err(&pdev->dev,
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"Unable to set DMA consistent mask: %d\n", ret);
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"Unable to set DMA consistent mask: %d\n", ret);
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@ -326,13 +326,16 @@ __be32 hfi1_compute_aeth(struct rvt_qp *qp)
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x = (min + max) / 2;
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x = (min + max) / 2;
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if (credit_table[x] == credits)
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if (credit_table[x] == credits)
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break;
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break;
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if (credit_table[x] > credits)
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if (credit_table[x] > credits) {
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max = x;
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max = x;
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else if (min == x)
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} else {
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if (min == x) {
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break;
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break;
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else
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} else {
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min = x;
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min = x;
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}
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}
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}
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}
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aeth |= x << HFI1_AETH_CREDIT_SHIFT;
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aeth |= x << HFI1_AETH_CREDIT_SHIFT;
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}
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}
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return cpu_to_be32(aeth);
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return cpu_to_be32(aeth);
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@ -505,9 +505,9 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
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len = pmtu;
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len = pmtu;
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break;
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break;
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}
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}
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if (wqe->wr.opcode == IB_WR_SEND)
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if (wqe->wr.opcode == IB_WR_SEND) {
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qp->s_state = OP(SEND_ONLY);
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qp->s_state = OP(SEND_ONLY);
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else {
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} else {
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qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
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qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
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/* Immediate data comes after the BTH */
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/* Immediate data comes after the BTH */
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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@ -542,9 +542,9 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
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len = pmtu;
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len = pmtu;
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break;
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break;
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}
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}
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if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
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if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
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qp->s_state = OP(RDMA_WRITE_ONLY);
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qp->s_state = OP(RDMA_WRITE_ONLY);
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else {
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} else {
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qp->s_state =
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qp->s_state =
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OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
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OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
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/* Immediate data comes after RETH */
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/* Immediate data comes after RETH */
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@ -672,9 +672,9 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
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middle = HFI1_CAP_IS_KSET(SDMA_AHG);
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middle = HFI1_CAP_IS_KSET(SDMA_AHG);
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break;
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break;
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}
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}
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if (wqe->wr.opcode == IB_WR_SEND)
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if (wqe->wr.opcode == IB_WR_SEND) {
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qp->s_state = OP(SEND_LAST);
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qp->s_state = OP(SEND_LAST);
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else {
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} else {
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qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
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qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
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/* Immediate data comes after the BTH */
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/* Immediate data comes after the BTH */
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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@ -712,9 +712,9 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
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middle = HFI1_CAP_IS_KSET(SDMA_AHG);
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middle = HFI1_CAP_IS_KSET(SDMA_AHG);
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break;
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break;
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}
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}
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if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
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if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
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qp->s_state = OP(RDMA_WRITE_LAST);
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qp->s_state = OP(RDMA_WRITE_LAST);
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else {
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} else {
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qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
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qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
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/* Immediate data comes after the BTH */
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/* Immediate data comes after the BTH */
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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ohdr->u.imm_data = wqe->wr.ex.imm_data;
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@ -1013,10 +1013,12 @@ static void restart_rc(struct rvt_qp *qp, u32 psn, int wait)
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hfi1_send_complete(qp, wqe, IB_WC_RETRY_EXC_ERR);
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hfi1_send_complete(qp, wqe, IB_WC_RETRY_EXC_ERR);
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rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
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rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
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return;
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return;
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} else /* need to handle delayed completion */
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} else { /* need to handle delayed completion */
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return;
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return;
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} else
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}
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} else {
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qp->s_retry--;
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qp->s_retry--;
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}
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ibp = to_iport(qp->ibqp.device, qp->port_num);
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ibp = to_iport(qp->ibqp.device, qp->port_num);
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if (wqe->wr.opcode == IB_WR_RDMA_READ)
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if (wqe->wr.opcode == IB_WR_RDMA_READ)
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@ -1612,8 +1614,9 @@ static void rc_rcv_resp(struct hfi1_ibport *ibp,
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val = ((u64)be32_to_cpu(p[0]) << 32) |
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val = ((u64)be32_to_cpu(p[0]) << 32) |
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be32_to_cpu(p[1]);
|
be32_to_cpu(p[1]);
|
||||||
} else
|
} else {
|
||||||
val = 0;
|
val = 0;
|
||||||
|
}
|
||||||
if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
|
if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
|
||||||
opcode != OP(RDMA_READ_RESPONSE_FIRST))
|
opcode != OP(RDMA_READ_RESPONSE_FIRST))
|
||||||
goto ack_done;
|
goto ack_done;
|
||||||
|
@ -2009,8 +2009,9 @@ static int sdma_check_progress(
|
|||||||
ret = wait->sleep(sde, wait, tx, seq);
|
ret = wait->sleep(sde, wait, tx, seq);
|
||||||
if (ret == -EAGAIN)
|
if (ret == -EAGAIN)
|
||||||
sde->desc_avail = sdma_descq_freecnt(sde);
|
sde->desc_avail = sdma_descq_freecnt(sde);
|
||||||
} else
|
} else {
|
||||||
ret = -EBUSY;
|
ret = -EBUSY;
|
||||||
|
}
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -119,9 +119,9 @@ static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
|
|||||||
* Allow for slow slaves by simple
|
* Allow for slow slaves by simple
|
||||||
* delay for falling edge, sampling on rise.
|
* delay for falling edge, sampling on rise.
|
||||||
*/
|
*/
|
||||||
if (!bit)
|
if (!bit) {
|
||||||
udelay(2);
|
udelay(2);
|
||||||
else {
|
} else {
|
||||||
int rise_usec;
|
int rise_usec;
|
||||||
|
|
||||||
for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
|
for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
|
||||||
|
@ -139,9 +139,9 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||||||
len = pmtu;
|
len = pmtu;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (wqe->wr.opcode == IB_WR_SEND)
|
if (wqe->wr.opcode == IB_WR_SEND) {
|
||||||
qp->s_state = OP(SEND_ONLY);
|
qp->s_state = OP(SEND_ONLY);
|
||||||
else {
|
} else {
|
||||||
qp->s_state =
|
qp->s_state =
|
||||||
OP(SEND_ONLY_WITH_IMMEDIATE);
|
OP(SEND_ONLY_WITH_IMMEDIATE);
|
||||||
/* Immediate data comes after the BTH */
|
/* Immediate data comes after the BTH */
|
||||||
@ -168,9 +168,9 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||||||
len = pmtu;
|
len = pmtu;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
|
if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
|
||||||
qp->s_state = OP(RDMA_WRITE_ONLY);
|
qp->s_state = OP(RDMA_WRITE_ONLY);
|
||||||
else {
|
} else {
|
||||||
qp->s_state =
|
qp->s_state =
|
||||||
OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
|
OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
|
||||||
/* Immediate data comes after the RETH */
|
/* Immediate data comes after the RETH */
|
||||||
@ -199,9 +199,9 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||||||
middle = HFI1_CAP_IS_KSET(SDMA_AHG);
|
middle = HFI1_CAP_IS_KSET(SDMA_AHG);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (wqe->wr.opcode == IB_WR_SEND)
|
if (wqe->wr.opcode == IB_WR_SEND) {
|
||||||
qp->s_state = OP(SEND_LAST);
|
qp->s_state = OP(SEND_LAST);
|
||||||
else {
|
} else {
|
||||||
qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
|
qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
|
||||||
/* Immediate data comes after the BTH */
|
/* Immediate data comes after the BTH */
|
||||||
ohdr->u.imm_data = wqe->wr.ex.imm_data;
|
ohdr->u.imm_data = wqe->wr.ex.imm_data;
|
||||||
@ -224,9 +224,9 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||||||
middle = HFI1_CAP_IS_KSET(SDMA_AHG);
|
middle = HFI1_CAP_IS_KSET(SDMA_AHG);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
|
if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
|
||||||
qp->s_state = OP(RDMA_WRITE_LAST);
|
qp->s_state = OP(RDMA_WRITE_LAST);
|
||||||
else {
|
} else {
|
||||||
qp->s_state =
|
qp->s_state =
|
||||||
OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
|
OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
|
||||||
/* Immediate data comes after the BTH */
|
/* Immediate data comes after the BTH */
|
||||||
@ -353,8 +353,9 @@ inv:
|
|||||||
qp->r_state == OP(SEND_MIDDLE)) {
|
qp->r_state == OP(SEND_MIDDLE)) {
|
||||||
set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
|
set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
|
||||||
qp->r_sge.num_sge = 0;
|
qp->r_sge.num_sge = 0;
|
||||||
} else
|
} else {
|
||||||
rvt_put_ss(&qp->r_sge);
|
rvt_put_ss(&qp->r_sge);
|
||||||
|
}
|
||||||
qp->r_state = OP(SEND_LAST);
|
qp->r_state = OP(SEND_LAST);
|
||||||
switch (opcode) {
|
switch (opcode) {
|
||||||
case OP(SEND_FIRST):
|
case OP(SEND_FIRST):
|
||||||
@ -410,9 +411,9 @@ inv:
|
|||||||
case OP(SEND_ONLY):
|
case OP(SEND_ONLY):
|
||||||
case OP(SEND_ONLY_WITH_IMMEDIATE):
|
case OP(SEND_ONLY_WITH_IMMEDIATE):
|
||||||
send_first:
|
send_first:
|
||||||
if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags))
|
if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
|
||||||
qp->r_sge = qp->s_rdma_read_sge;
|
qp->r_sge = qp->s_rdma_read_sge;
|
||||||
else {
|
} else {
|
||||||
ret = hfi1_rvt_get_rwqe(qp, 0);
|
ret = hfi1_rvt_get_rwqe(qp, 0);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
goto op_err;
|
goto op_err;
|
||||||
@ -523,9 +524,9 @@ rdma_first:
|
|||||||
qp->r_sge.sge.length = 0;
|
qp->r_sge.sge.length = 0;
|
||||||
qp->r_sge.sge.sge_length = 0;
|
qp->r_sge.sge.sge_length = 0;
|
||||||
}
|
}
|
||||||
if (opcode == OP(RDMA_WRITE_ONLY))
|
if (opcode == OP(RDMA_WRITE_ONLY)) {
|
||||||
goto rdma_last;
|
goto rdma_last;
|
||||||
else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
|
} else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
|
||||||
wc.ex.imm_data = ohdr->u.rc.imm_data;
|
wc.ex.imm_data = ohdr->u.rc.imm_data;
|
||||||
goto rdma_last_imm;
|
goto rdma_last_imm;
|
||||||
}
|
}
|
||||||
@ -555,9 +556,9 @@ rdma_last_imm:
|
|||||||
tlen -= (hdrsize + pad + 4);
|
tlen -= (hdrsize + pad + 4);
|
||||||
if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
|
if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
|
||||||
goto drop;
|
goto drop;
|
||||||
if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags))
|
if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
|
||||||
rvt_put_ss(&qp->s_rdma_read_sge);
|
rvt_put_ss(&qp->s_rdma_read_sge);
|
||||||
else {
|
} else {
|
||||||
ret = hfi1_rvt_get_rwqe(qp, 1);
|
ret = hfi1_rvt_get_rwqe(qp, 1);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
goto op_err;
|
goto op_err;
|
||||||
|
@ -163,9 +163,9 @@ static void ud_loopback(struct rvt_qp *sqp, struct rvt_swqe *swqe)
|
|||||||
/*
|
/*
|
||||||
* Get the next work request entry to find where to put the data.
|
* Get the next work request entry to find where to put the data.
|
||||||
*/
|
*/
|
||||||
if (qp->r_flags & RVT_R_REUSE_SGE)
|
if (qp->r_flags & RVT_R_REUSE_SGE) {
|
||||||
qp->r_flags &= ~RVT_R_REUSE_SGE;
|
qp->r_flags &= ~RVT_R_REUSE_SGE;
|
||||||
else {
|
} else {
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = hfi1_rvt_get_rwqe(qp, 0);
|
ret = hfi1_rvt_get_rwqe(qp, 0);
|
||||||
@ -190,8 +190,9 @@ static void ud_loopback(struct rvt_qp *sqp, struct rvt_swqe *swqe)
|
|||||||
hfi1_copy_sge(&qp->r_sge, &ah_attr->grh,
|
hfi1_copy_sge(&qp->r_sge, &ah_attr->grh,
|
||||||
sizeof(struct ib_grh), 1, 0);
|
sizeof(struct ib_grh), 1, 0);
|
||||||
wc.wc_flags |= IB_WC_GRH;
|
wc.wc_flags |= IB_WC_GRH;
|
||||||
} else
|
} else {
|
||||||
hfi1_skip_sge(&qp->r_sge, sizeof(struct ib_grh), 1);
|
hfi1_skip_sge(&qp->r_sge, sizeof(struct ib_grh), 1);
|
||||||
|
}
|
||||||
ssge.sg_list = swqe->sg_list + 1;
|
ssge.sg_list = swqe->sg_list + 1;
|
||||||
ssge.sge = *swqe->sg_list;
|
ssge.sge = *swqe->sg_list;
|
||||||
ssge.num_sge = swqe->wr.num_sge;
|
ssge.num_sge = swqe->wr.num_sge;
|
||||||
@ -383,8 +384,9 @@ int hfi1_make_ud_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
|
|||||||
qp->s_hdrwords++;
|
qp->s_hdrwords++;
|
||||||
ohdr->u.ud.imm_data = wqe->wr.ex.imm_data;
|
ohdr->u.ud.imm_data = wqe->wr.ex.imm_data;
|
||||||
bth0 = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE << 24;
|
bth0 = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE << 24;
|
||||||
} else
|
} else {
|
||||||
bth0 = IB_OPCODE_UD_SEND_ONLY << 24;
|
bth0 = IB_OPCODE_UD_SEND_ONLY << 24;
|
||||||
|
}
|
||||||
sc5 = ibp->sl_to_sc[ah_attr->sl];
|
sc5 = ibp->sl_to_sc[ah_attr->sl];
|
||||||
lrh0 |= (ah_attr->sl & 0xf) << 4;
|
lrh0 |= (ah_attr->sl & 0xf) << 4;
|
||||||
if (qp->ibqp.qp_type == IB_QPT_SMI) {
|
if (qp->ibqp.qp_type == IB_QPT_SMI) {
|
||||||
@ -820,8 +822,9 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
|
|||||||
} else if (opcode == IB_OPCODE_UD_SEND_ONLY) {
|
} else if (opcode == IB_OPCODE_UD_SEND_ONLY) {
|
||||||
wc.ex.imm_data = 0;
|
wc.ex.imm_data = 0;
|
||||||
wc.wc_flags = 0;
|
wc.wc_flags = 0;
|
||||||
} else
|
} else {
|
||||||
goto drop;
|
goto drop;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* A GRH is expected to precede the data even if not
|
* A GRH is expected to precede the data even if not
|
||||||
@ -832,9 +835,9 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
|
|||||||
/*
|
/*
|
||||||
* Get the next work request entry to find where to put the data.
|
* Get the next work request entry to find where to put the data.
|
||||||
*/
|
*/
|
||||||
if (qp->r_flags & RVT_R_REUSE_SGE)
|
if (qp->r_flags & RVT_R_REUSE_SGE) {
|
||||||
qp->r_flags &= ~RVT_R_REUSE_SGE;
|
qp->r_flags &= ~RVT_R_REUSE_SGE;
|
||||||
else {
|
} else {
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = hfi1_rvt_get_rwqe(qp, 0);
|
ret = hfi1_rvt_get_rwqe(qp, 0);
|
||||||
@ -857,8 +860,9 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
|
|||||||
hfi1_copy_sge(&qp->r_sge, &hdr->u.l.grh,
|
hfi1_copy_sge(&qp->r_sge, &hdr->u.l.grh,
|
||||||
sizeof(struct ib_grh), 1, 0);
|
sizeof(struct ib_grh), 1, 0);
|
||||||
wc.wc_flags |= IB_WC_GRH;
|
wc.wc_flags |= IB_WC_GRH;
|
||||||
} else
|
} else {
|
||||||
hfi1_skip_sge(&qp->r_sge, sizeof(struct ib_grh), 1);
|
hfi1_skip_sge(&qp->r_sge, sizeof(struct ib_grh), 1);
|
||||||
|
}
|
||||||
hfi1_copy_sge(&qp->r_sge, data, wc.byte_len - sizeof(struct ib_grh),
|
hfi1_copy_sge(&qp->r_sge, data, wc.byte_len - sizeof(struct ib_grh),
|
||||||
1, 0);
|
1, 0);
|
||||||
rvt_put_ss(&qp->r_sge);
|
rvt_put_ss(&qp->r_sge);
|
||||||
@ -884,8 +888,9 @@ void hfi1_ud_rcv(struct hfi1_packet *packet)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
wc.pkey_index = (unsigned)mgmt_pkey_idx;
|
wc.pkey_index = (unsigned)mgmt_pkey_idx;
|
||||||
} else
|
} else {
|
||||||
wc.pkey_index = 0;
|
wc.pkey_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
wc.slid = be16_to_cpu(hdr->lrh[3]);
|
wc.slid = be16_to_cpu(hdr->lrh[3]);
|
||||||
sc = (be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf;
|
sc = (be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf;
|
||||||
|
@ -765,8 +765,9 @@ static inline u32 compute_data_length(struct user_sdma_request *req,
|
|||||||
* remaining.
|
* remaining.
|
||||||
*/
|
*/
|
||||||
len = min(len, req->data_len - req->sent);
|
len = min(len, req->data_len - req->sent);
|
||||||
} else
|
} else {
|
||||||
len = min(req->data_len - req->sent, (u32)req->info.fragsize);
|
len = min(req->data_len - req->sent, (u32)req->info.fragsize);
|
||||||
|
}
|
||||||
SDMA_DBG(req, "Data Length = %u", len);
|
SDMA_DBG(req, "Data Length = %u", len);
|
||||||
return len;
|
return len;
|
||||||
}
|
}
|
||||||
@ -1337,9 +1338,10 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
|
|||||||
INTR) >> 16);
|
INTR) >> 16);
|
||||||
val &= cpu_to_le16(~(1U << 13));
|
val &= cpu_to_le16(~(1U << 13));
|
||||||
AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val);
|
AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val);
|
||||||
} else
|
} else {
|
||||||
AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val);
|
AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val);
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt,
|
trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt,
|
||||||
req->info.comp_idx, req->sde->this_idx,
|
req->info.comp_idx, req->sde->this_idx,
|
||||||
|
@ -400,9 +400,9 @@ void hfi1_ib_rcv(struct hfi1_packet *packet)
|
|||||||
|
|
||||||
/* Check for GRH */
|
/* Check for GRH */
|
||||||
lnh = be16_to_cpu(hdr->lrh[0]) & 3;
|
lnh = be16_to_cpu(hdr->lrh[0]) & 3;
|
||||||
if (lnh == HFI1_LRH_BTH)
|
if (lnh == HFI1_LRH_BTH) {
|
||||||
packet->ohdr = &hdr->u.oth;
|
packet->ohdr = &hdr->u.oth;
|
||||||
else if (lnh == HFI1_LRH_GRH) {
|
} else if (lnh == HFI1_LRH_GRH) {
|
||||||
u32 vtf;
|
u32 vtf;
|
||||||
|
|
||||||
packet->ohdr = &hdr->u.l.oth;
|
packet->ohdr = &hdr->u.l.oth;
|
||||||
@ -412,8 +412,9 @@ void hfi1_ib_rcv(struct hfi1_packet *packet)
|
|||||||
if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
|
if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
|
||||||
goto drop;
|
goto drop;
|
||||||
packet->rcv_flags |= HFI1_HAS_GRH;
|
packet->rcv_flags |= HFI1_HAS_GRH;
|
||||||
} else
|
} else {
|
||||||
goto drop;
|
goto drop;
|
||||||
|
}
|
||||||
|
|
||||||
trace_input_ibhdr(rcd->dd, hdr);
|
trace_input_ibhdr(rcd->dd, hdr);
|
||||||
|
|
||||||
@ -528,9 +529,9 @@ static void verbs_sdma_complete(
|
|||||||
struct rvt_qp *qp = tx->qp;
|
struct rvt_qp *qp = tx->qp;
|
||||||
|
|
||||||
spin_lock(&qp->s_lock);
|
spin_lock(&qp->s_lock);
|
||||||
if (tx->wqe)
|
if (tx->wqe) {
|
||||||
hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
|
hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
|
||||||
else if (qp->ibqp.qp_type == IB_QPT_RC) {
|
} else if (qp->ibqp.qp_type == IB_QPT_RC) {
|
||||||
struct hfi1_ib_header *hdr;
|
struct hfi1_ib_header *hdr;
|
||||||
|
|
||||||
hdr = &tx->phdr.hdr;
|
hdr = &tx->phdr.hdr;
|
||||||
|
Loading…
x
Reference in New Issue
Block a user