From e528556577a04a5a2021d08e1096eb41f78b8ea9 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 4 Mar 2021 11:52:06 +0800 Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic. SDMA 4_x asics share the same MGCG/MGLS setting. Signed-off-by: Feifei Xu Reviewed-by: Alex Deucher Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 00d37739f0f1..fdc0c813c33f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2222,21 +2222,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle, if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->asic_type) { - case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_RAVEN: - case CHIP_ARCTURUS: - case CHIP_RENOIR: - sdma_v4_0_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE); - sdma_v4_0_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE); - break; - default: - break; - } + sdma_v4_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE); + sdma_v4_0_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE); return 0; }