clk: renesas: r9a09g011: Add PFC clock and reset entries
Add PFC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220518135208.39885-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -126,6 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
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};
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static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
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DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
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DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
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DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
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DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
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@ -137,6 +138,7 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
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};
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static const struct rzg2l_reset r9a09g011_resets[] = {
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DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
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DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
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DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
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};
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