mt76: dma: rely on mt76_queue in mt76_dma_tx_cleanup signature
This is a preliminary patch to move data queues in mt76_phy and properly support dbdc Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
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264b7b1986
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e5655492e3
@ -217,9 +217,8 @@ mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
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}
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}
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static void
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static void
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mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
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mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
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{
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{
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struct mt76_queue *q = dev->q_tx[qid];
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struct mt76_queue_entry entry;
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struct mt76_queue_entry entry;
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bool wake = false;
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bool wake = false;
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int last;
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int last;
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@ -255,7 +254,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
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}
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}
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wake = wake && q->stopped &&
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wake = wake && q->stopped &&
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qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
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q->qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
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if (wake)
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if (wake)
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q->stopped = false;
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q->stopped = false;
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@ -263,7 +262,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
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wake_up(&dev->tx_wait);
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wake_up(&dev->tx_wait);
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if (wake)
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if (wake)
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ieee80211_wake_queue(dev->hw, qid);
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ieee80211_wake_queue(dev->hw, q->qid);
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}
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}
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static void *
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static void *
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@ -664,7 +663,7 @@ void mt76_dma_cleanup(struct mt76_dev *dev)
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mt76_worker_disable(&dev->tx_worker);
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mt76_worker_disable(&dev->tx_worker);
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netif_napi_del(&dev->tx_napi);
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netif_napi_del(&dev->tx_napi);
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for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
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for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
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mt76_dma_tx_cleanup(dev, i, true);
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mt76_dma_tx_cleanup(dev, dev->q_tx[i], true);
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mt76_for_each_q_rx(dev, i) {
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mt76_for_each_q_rx(dev, i) {
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netif_napi_del(&dev->napi[i]);
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netif_napi_del(&dev->napi[i]);
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@ -122,7 +122,8 @@ int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
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len -= cur_len;
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len -= cur_len;
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if (dev->queue_ops->tx_cleanup)
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if (dev->queue_ops->tx_cleanup)
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dev->queue_ops->tx_cleanup(dev, MT_TXQ_FWDL, false);
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dev->queue_ops->tx_cleanup(dev, dev->q_tx[MT_TXQ_FWDL],
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false);
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}
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}
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return 0;
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return 0;
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@ -179,7 +179,7 @@ struct mt76_queue_ops {
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void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
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void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
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void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid,
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void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
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bool flush);
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bool flush);
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void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
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void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
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@ -89,7 +89,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
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/* Flush all previous CAB queue packets */
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/* Flush all previous CAB queue packets */
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mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
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mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
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mt76_queue_tx_cleanup(dev, MT_TXQ_CAB, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_CAB], false);
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mt76_csa_check(&dev->mt76);
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mt76_csa_check(&dev->mt76);
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if (dev->mt76.csa_complete)
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if (dev->mt76.csa_complete)
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@ -135,7 +135,7 @@ void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
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((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
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((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
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out:
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out:
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mt76_queue_tx_cleanup(dev, MT_TXQ_BEACON, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_BEACON], false);
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if (dev->mt76.q_tx[MT_TXQ_BEACON]->queued >
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if (dev->mt76.q_tx[MT_TXQ_BEACON]->queued >
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hweight8(dev->mt76.beacon_mask))
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hweight8(dev->mt76.beacon_mask))
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dev->beacon_check++;
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dev->beacon_check++;
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@ -147,13 +147,13 @@ static int mt7603_poll_tx(struct napi_struct *napi, int budget)
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dev->tx_dma_check = 0;
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dev->tx_dma_check = 0;
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for (i = MT_TXQ_MCU; i >= 0; i--)
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
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if (napi_complete_done(napi, 0))
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if (napi_complete_done(napi, 0))
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mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt7603_irq_enable(dev, MT_INT_TX_DONE_ALL);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
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mt7603_mac_sta_poll(dev);
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mt7603_mac_sta_poll(dev);
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@ -1435,7 +1435,7 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
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mt7603_pse_client_reset(dev);
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mt7603_pse_client_reset(dev);
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for (i = 0; i < __MT_TXQ_MAX; i++)
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_tx_cleanup(dev, i, true);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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mt76_queue_rx_reset(dev, i);
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@ -75,7 +75,7 @@ static int mt7615_poll_tx(struct napi_struct *napi, int budget)
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dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
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dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
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mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU], false);
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if (napi_complete_done(napi, 0))
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if (napi_complete_done(napi, 0))
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mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
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mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
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@ -1435,12 +1435,12 @@ static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
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struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
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struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
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u8 i, count;
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u8 i, count;
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mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_PSD], false);
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if (is_mt7615(&dev->mt76)) {
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if (is_mt7615(&dev->mt76)) {
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mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_BE], false);
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} else {
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} else {
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for (i = 0; i < IEEE80211_NUM_ACS; i++)
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for (i = 0; i < IEEE80211_NUM_ACS; i++)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
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}
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}
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count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
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count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
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@ -2045,7 +2045,7 @@ void mt7615_dma_reset(struct mt7615_dev *dev)
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usleep_range(1000, 2000);
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usleep_range(1000, 2000);
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for (i = 0; i < __MT_TXQ_MAX; i++)
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_tx_cleanup(dev, i, true);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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mt76_queue_rx_reset(dev, i);
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@ -2464,7 +2464,7 @@ int mt7615_mcu_init(struct mt7615_dev *dev)
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if (ret)
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if (ret)
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return ret;
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return ret;
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mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_FWDL], false);
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dev_dbg(dev->mt76.dev, "Firmware init done\n");
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dev_dbg(dev->mt76.dev, "Firmware init done\n");
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set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
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set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
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mt7615_mcu_fw_log_2_host(dev, 0);
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mt7615_mcu_fw_log_2_host(dev, 0);
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@ -164,13 +164,13 @@ static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
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mt76x02_mac_poll_tx_status(dev, false);
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mt76x02_mac_poll_tx_status(dev, false);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
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if (napi_complete_done(napi, 0))
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if (napi_complete_done(napi, 0))
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mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
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for (i = MT_TXQ_MCU; i >= 0; i--)
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for (i = MT_TXQ_MCU; i >= 0; i--)
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mt76_queue_tx_cleanup(dev, i, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], false);
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mt76_worker_schedule(&dev->mt76.tx_worker);
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mt76_worker_schedule(&dev->mt76.tx_worker);
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@ -469,7 +469,7 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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mt76_mcu_restart(dev);
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mt76_mcu_restart(dev);
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for (i = 0; i < __MT_TXQ_MAX; i++)
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_tx_cleanup(dev, i, true);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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mt76_queue_rx_reset(dev, i);
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@ -56,8 +56,8 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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static void
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static void
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mt7915_tx_cleanup(struct mt7915_dev *dev)
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mt7915_tx_cleanup(struct mt7915_dev *dev)
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{
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{
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mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU], false);
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mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_MCU_WA], false);
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}
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}
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static int mt7915_poll_tx(struct napi_struct *napi, int budget)
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static int mt7915_poll_tx(struct napi_struct *napi, int budget)
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@ -1072,8 +1072,8 @@ void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
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u8 i, count;
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u8 i, count;
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/* clean DMA queues and unmap buffers first */
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/* clean DMA queues and unmap buffers first */
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mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
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mt76_queue_tx_cleanup(dev, mdev->q_tx[MT_TXQ_PSD], false);
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mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
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mt76_queue_tx_cleanup(dev, mdev->q_tx[MT_TXQ_BE], false);
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/*
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/*
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* TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
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* TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
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@ -1421,7 +1421,7 @@ mt7915_dma_reset(struct mt7915_dev *dev)
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usleep_range(1000, 2000);
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usleep_range(1000, 2000);
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for (i = 0; i < __MT_TXQ_MAX; i++)
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_tx_cleanup(dev, i, true);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[i], true);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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mt76_queue_rx_reset(dev, i);
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@ -2799,7 +2799,7 @@ static int mt7915_load_firmware(struct mt7915_dev *dev)
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return -EIO;
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return -EIO;
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}
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}
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mt76_queue_tx_cleanup(dev, MT_TXQ_FWDL, false);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_tx[MT_TXQ_FWDL], false);
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dev_dbg(dev->mt76.dev, "Firmware init done\n");
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dev_dbg(dev->mt76.dev, "Firmware init done\n");
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