Merge patch series "ufs: host: mediatek: Provide features and fixes in MediaTek platforms"
Peter Wang <peter.wang@mediatek.com> says: This series fixes some defects and provide features in MediaTek UFS drivers. Link: https://lore.kernel.org/r/20240315083448.7185-1-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Martin K. Petersen
commit
e5abf748fc
94
drivers/ufs/host/ufs-mediatek-sip.h
Normal file
94
drivers/ufs/host/ufs-mediatek-sip.h
Normal file
@ -0,0 +1,94 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_SIP_H
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#define _UFS_MEDIATEK_SIP_H
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/*
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* SiP (Slicon Partner) commands
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*/
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#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
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#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
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#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
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#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
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#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
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#define UFS_MTK_SIP_SRAM_PWR_CTRL BIT(5)
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#define UFS_MTK_SIP_GET_VCC_NUM BIT(6)
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#define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7)
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#define UFS_MTK_SIP_MPHY_CTRL BIT(8)
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#define UFS_MTK_SIP_MTCMOS_CTRL BIT(9)
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/*
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* Multi-VCC by Numbering
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*/
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enum ufs_mtk_vcc_num {
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UFS_VCC_NONE = 0,
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UFS_VCC_1,
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UFS_VCC_2,
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UFS_VCC_MAX
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};
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enum ufs_mtk_mphy_op {
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UFS_MPHY_BACKUP = 0,
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UFS_MPHY_RESTORE
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};
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/*
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* SMC call wrapper function
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*/
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struct ufs_mtk_smc_arg {
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unsigned long cmd;
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struct arm_smccc_res *res;
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unsigned long v1;
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unsigned long v2;
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unsigned long v3;
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unsigned long v4;
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unsigned long v5;
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unsigned long v6;
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unsigned long v7;
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};
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static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
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{
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arm_smccc_smc(MTK_SIP_UFS_CONTROL,
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s.cmd,
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s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
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}
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#define ufs_mtk_smc(...) \
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_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
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/* Sip kernel interface */
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#define ufs_mtk_va09_pwr_ctrl(res, on) \
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ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
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#define ufs_mtk_crypto_ctrl(res, enable) \
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ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
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#define ufs_mtk_ref_clk_notify(on, stage, res) \
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ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
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#define ufs_mtk_device_reset_ctrl(high, res) \
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ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
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#define ufs_mtk_sram_pwr_ctrl(on, res) \
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ufs_mtk_smc(UFS_MTK_SIP_SRAM_PWR_CTRL, &(res), on)
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#define ufs_mtk_get_vcc_num(res) \
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ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
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#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
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ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)
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#define ufs_mtk_mphy_ctrl(op, res) \
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ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
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#define ufs_mtk_mtcmos_ctrl(op, res) \
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ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)
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#endif /* !_UFS_MEDIATEK_SIP_H */
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@ -19,13 +19,14 @@
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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#include <ufs/ufs_quirks.h>
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#include <ufs/unipro.h>
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#include "ufs-mediatek.h"
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#include "ufs-mediatek-sip.h"
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static int ufs_mtk_config_mcq(struct ufs_hba *hba, bool irq);
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@ -118,6 +119,27 @@ static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
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return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
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}
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static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
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}
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static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
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}
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static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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return (host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
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}
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static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
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{
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u32 tmp;
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@ -169,16 +191,23 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
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static void ufs_mtk_host_reset(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct arm_smccc_res res;
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reset_control_assert(host->hci_reset);
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reset_control_assert(host->crypto_reset);
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reset_control_assert(host->unipro_reset);
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reset_control_assert(host->mphy_reset);
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usleep_range(100, 110);
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reset_control_deassert(host->unipro_reset);
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reset_control_deassert(host->crypto_reset);
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reset_control_deassert(host->hci_reset);
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reset_control_deassert(host->mphy_reset);
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/* restore mphy setting aftre mphy reset */
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if (host->mphy_reset)
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ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
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}
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static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
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@ -203,6 +232,8 @@ static void ufs_mtk_init_reset(struct ufs_hba *hba)
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"unipro_rst");
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ufs_mtk_init_reset_control(hba, &host->crypto_reset,
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"crypto_rst");
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ufs_mtk_init_reset_control(hba, &host->mphy_reset,
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"mphy_rst");
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}
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static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
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@ -622,6 +653,15 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
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if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
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host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
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if (of_property_read_bool(np, "mediatek,ufs-tx-skew-fix"))
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host->caps |= UFS_MTK_CAP_TX_SKEW_FIX;
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if (of_property_read_bool(np, "mediatek,ufs-disable-mcq"))
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host->caps |= UFS_MTK_CAP_DISABLE_MCQ;
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if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
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host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
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dev_info(hba->dev, "caps: 0x%x", host->caps);
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}
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@ -885,6 +925,9 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
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host->mcq_nr_intr = UFSHCD_MAX_Q_NR;
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pdev = container_of(hba->dev, struct platform_device, dev);
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if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
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goto failed;
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for (i = 0; i < host->mcq_nr_intr; i++) {
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/* irq index 0 is legacy irq, sq/cq irq start from index 1 */
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irq = platform_get_irq(pdev, i + 1);
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@ -923,6 +966,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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struct ufs_mtk_host *host;
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struct Scsi_Host *shost = hba->host;
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int err = 0;
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struct arm_smccc_res res;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host) {
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@ -951,6 +995,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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ufs_mtk_init_reset(hba);
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/* backup mphy setting if mphy can reset */
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if (host->mphy_reset)
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ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
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/* Enable runtime autosuspend */
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hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
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@ -987,6 +1035,15 @@ static int ufs_mtk_init(struct ufs_hba *hba)
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* Enable phy clocks specifically here.
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*/
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ufs_mtk_mphy_power_on(hba, true);
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if (ufs_mtk_is_rtff_mtcmos(hba)) {
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/* First Restore here, to avoid backup unexpected value */
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ufs_mtk_mtcmos_ctrl(false, res);
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/* Power on to init */
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ufs_mtk_mtcmos_ctrl(true, res);
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}
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ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
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host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
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@ -1303,27 +1360,37 @@ static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm)
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static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
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{
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if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
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return;
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bool skip_vccqx = false;
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/* Skip if VCC is assumed always-on */
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if (!hba->vreg_info.vcc)
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return;
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/* Bypass LPM when device is still active */
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/* Prevent entering LPM when device is still active */
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if (lpm && ufshcd_is_ufs_dev_active(hba))
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return;
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/* Bypass LPM if VCC is enabled */
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if (lpm && hba->vreg_info.vcc->enabled)
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return;
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/* Skip vccqx lpm control and control vsx only */
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if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
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skip_vccqx = true;
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/* VCC is always-on, control vsx only */
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if (!hba->vreg_info.vcc)
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skip_vccqx = true;
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/* Broken vcc keep vcc always on, most case control vsx only */
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if (lpm && hba->vreg_info.vcc && hba->vreg_info.vcc->enabled) {
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/* Some device vccqx/vsx can enter lpm */
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if (ufs_mtk_is_allow_vccqx_lpm(hba))
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skip_vccqx = false;
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else /* control vsx only */
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skip_vccqx = true;
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}
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if (lpm) {
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ufs_mtk_vccqx_set_lpm(hba, lpm);
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if (!skip_vccqx)
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ufs_mtk_vccqx_set_lpm(hba, lpm);
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ufs_mtk_vsx_set_lpm(hba, lpm);
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} else {
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ufs_mtk_vsx_set_lpm(hba, lpm);
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ufs_mtk_vccqx_set_lpm(hba, lpm);
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if (!skip_vccqx)
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ufs_mtk_vccqx_set_lpm(hba, lpm);
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}
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}
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@ -1374,7 +1441,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
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if (ufshcd_is_link_off(hba))
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ufs_mtk_device_reset_ctrl(0, res);
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ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);
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ufs_mtk_sram_pwr_ctrl(false, res);
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return 0;
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fail:
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@ -1395,7 +1462,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
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ufs_mtk_dev_vreg_set_lpm(hba, false);
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ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);
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ufs_mtk_sram_pwr_ctrl(true, res);
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err = ufs_mtk_mphy_power_on(hba, true);
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if (err)
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@ -1438,6 +1505,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
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if (mid == UFS_VENDOR_SAMSUNG) {
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
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} else if (mid == UFS_VENDOR_MICRON) {
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/* Only for the host which have TX skew issue */
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if (ufs_mtk_is_tx_skew_fix(hba) &&
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(STR_PRFX_EQUAL("MT128GBCAV2U31", dev_info->model) ||
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STR_PRFX_EQUAL("MT256GBCAV4U31", dev_info->model) ||
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STR_PRFX_EQUAL("MT512GBCAV8U31", dev_info->model) ||
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STR_PRFX_EQUAL("MT256GBEAX4U40", dev_info->model) ||
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STR_PRFX_EQUAL("MT512GAYAX4U40", dev_info->model) ||
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STR_PRFX_EQUAL("MT001TAYAX8U40", dev_info->model))) {
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8);
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}
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}
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/*
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@ -1579,6 +1657,12 @@ static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
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static int ufs_mtk_get_hba_mac(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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/* MCQ operation not permitted */
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if (host->caps & UFS_MTK_CAP_DISABLE_MCQ)
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return -EPERM;
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return MAX_SUPP_MAC;
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}
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@ -1790,6 +1874,7 @@ static void ufs_mtk_remove(struct platform_device *pdev)
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static int ufs_mtk_system_suspend(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct arm_smccc_res res;
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int ret;
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ret = ufshcd_system_suspend(dev);
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@ -1798,15 +1883,22 @@ static int ufs_mtk_system_suspend(struct device *dev)
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ufs_mtk_dev_vreg_set_lpm(hba, true);
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if (ufs_mtk_is_rtff_mtcmos(hba))
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ufs_mtk_mtcmos_ctrl(false, res);
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|
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return 0;
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}
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static int ufs_mtk_system_resume(struct device *dev)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct arm_smccc_res res;
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ufs_mtk_dev_vreg_set_lpm(hba, false);
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if (ufs_mtk_is_rtff_mtcmos(hba))
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ufs_mtk_mtcmos_ctrl(true, res);
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return ufshcd_system_resume(dev);
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}
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#endif
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@ -1815,6 +1907,7 @@ static int ufs_mtk_system_resume(struct device *dev)
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static int ufs_mtk_runtime_suspend(struct device *dev)
|
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{
|
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struct ufs_hba *hba = dev_get_drvdata(dev);
|
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struct arm_smccc_res res;
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int ret = 0;
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ret = ufshcd_runtime_suspend(dev);
|
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@ -1823,12 +1916,19 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
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|
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ufs_mtk_dev_vreg_set_lpm(hba, true);
|
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|
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if (ufs_mtk_is_rtff_mtcmos(hba))
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ufs_mtk_mtcmos_ctrl(false, res);
|
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|
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return 0;
|
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}
|
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|
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static int ufs_mtk_runtime_resume(struct device *dev)
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{
|
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struct ufs_hba *hba = dev_get_drvdata(dev);
|
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struct arm_smccc_res res;
|
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|
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if (ufs_mtk_is_rtff_mtcmos(hba))
|
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ufs_mtk_mtcmos_ctrl(true, res);
|
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|
||||
ufs_mtk_dev_vreg_set_lpm(hba, false);
|
||||
|
||||
|
||||
@ -7,7 +7,6 @@
|
||||
#define _UFS_MEDIATEK_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/soc/mediatek/mtk_sip_svc.h>
|
||||
|
||||
/*
|
||||
* MCQ define and struct
|
||||
@ -99,18 +98,6 @@ enum {
|
||||
VS_HIB_EXIT = 13,
|
||||
};
|
||||
|
||||
/*
|
||||
* SiP commands
|
||||
*/
|
||||
#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
|
||||
#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
|
||||
#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
|
||||
#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
|
||||
#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
|
||||
#define UFS_MTK_SIP_HOST_PWR_CTRL BIT(5)
|
||||
#define UFS_MTK_SIP_GET_VCC_NUM BIT(6)
|
||||
#define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7)
|
||||
|
||||
/*
|
||||
* VS_DEBUGCLOCKENABLE
|
||||
*/
|
||||
@ -135,7 +122,17 @@ enum ufs_mtk_host_caps {
|
||||
UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
|
||||
UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
|
||||
UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
|
||||
|
||||
/*
|
||||
* Override UFS_MTK_CAP_BROKEN_VCC's behavior to
|
||||
* allow vccqx upstream to enter LPM
|
||||
*/
|
||||
UFS_MTK_CAP_ALLOW_VCCQX_LPM = 1 << 5,
|
||||
UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6,
|
||||
UFS_MTK_CAP_TX_SKEW_FIX = 1 << 7,
|
||||
UFS_MTK_CAP_DISABLE_MCQ = 1 << 8,
|
||||
/* Control MTCMOS with RTFF */
|
||||
UFS_MTK_CAP_RTFF_MTCMOS = 1 << 9,
|
||||
};
|
||||
|
||||
struct ufs_mtk_crypt_cfg {
|
||||
@ -170,6 +167,7 @@ struct ufs_mtk_host {
|
||||
struct reset_control *hci_reset;
|
||||
struct reset_control *unipro_reset;
|
||||
struct reset_control *crypto_reset;
|
||||
struct reset_control *mphy_reset;
|
||||
struct ufs_hba *hba;
|
||||
struct ufs_mtk_crypt_cfg *crypt;
|
||||
struct ufs_mtk_clk mclk;
|
||||
@ -191,70 +189,4 @@ struct ufs_mtk_host {
|
||||
/* MTK delay of autosuspend: 500 ms */
|
||||
#define MTK_RPM_AUTOSUSPEND_DELAY_MS 500
|
||||
|
||||
/*
|
||||
* Multi-VCC by Numbering
|
||||
*/
|
||||
enum ufs_mtk_vcc_num {
|
||||
UFS_VCC_NONE = 0,
|
||||
UFS_VCC_1,
|
||||
UFS_VCC_2,
|
||||
UFS_VCC_MAX
|
||||
};
|
||||
|
||||
/*
|
||||
* Host Power Control options
|
||||
*/
|
||||
enum {
|
||||
HOST_PWR_HCI = 0,
|
||||
HOST_PWR_MPHY
|
||||
};
|
||||
|
||||
/*
|
||||
* SMC call wrapper function
|
||||
*/
|
||||
struct ufs_mtk_smc_arg {
|
||||
unsigned long cmd;
|
||||
struct arm_smccc_res *res;
|
||||
unsigned long v1;
|
||||
unsigned long v2;
|
||||
unsigned long v3;
|
||||
unsigned long v4;
|
||||
unsigned long v5;
|
||||
unsigned long v6;
|
||||
unsigned long v7;
|
||||
};
|
||||
|
||||
static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
|
||||
{
|
||||
arm_smccc_smc(MTK_SIP_UFS_CONTROL,
|
||||
s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
|
||||
}
|
||||
|
||||
#define ufs_mtk_smc(...) \
|
||||
_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
|
||||
|
||||
/*
|
||||
* SMC call interface
|
||||
*/
|
||||
#define ufs_mtk_va09_pwr_ctrl(res, on) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
|
||||
|
||||
#define ufs_mtk_crypto_ctrl(res, enable) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
|
||||
|
||||
#define ufs_mtk_ref_clk_notify(on, stage, res) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
|
||||
|
||||
#define ufs_mtk_device_reset_ctrl(high, res) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
|
||||
|
||||
#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
|
||||
|
||||
#define ufs_mtk_get_vcc_num(res) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
|
||||
|
||||
#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
|
||||
ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
|
||||
|
||||
#endif /* !_UFS_MEDIATEK_H */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user