net: stmmac: add imx93 platform support
Add imx93 platform support for dwmac-imx driver. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -31,6 +31,12 @@
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#define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
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#define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
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#define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
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#define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
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#define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
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#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
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#define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
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struct imx_dwmac_ops {
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struct imx_dwmac_ops {
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u32 addr_width;
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u32 addr_width;
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bool mac_rgmii_txclk_auto_adj;
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bool mac_rgmii_txclk_auto_adj;
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@ -90,6 +96,35 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
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return ret;
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return ret;
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}
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}
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static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
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{
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struct imx_priv_data *dwmac = plat_dat->bsp_priv;
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int val;
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_MII:
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val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
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break;
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default:
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dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
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plat_dat->interface);
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return -EINVAL;
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}
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val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
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return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
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MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
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};
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static int imx_dwmac_clks_config(void *priv, bool enabled)
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static int imx_dwmac_clks_config(void *priv, bool enabled)
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{
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{
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struct imx_priv_data *dwmac = priv;
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struct imx_priv_data *dwmac = priv;
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@ -188,7 +223,9 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
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}
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}
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dwmac->clk_mem = NULL;
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dwmac->clk_mem = NULL;
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if (of_machine_is_compatible("fsl,imx8dxl")) {
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if (of_machine_is_compatible("fsl,imx8dxl") ||
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of_machine_is_compatible("fsl,imx93")) {
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dwmac->clk_mem = devm_clk_get(dev, "mem");
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dwmac->clk_mem = devm_clk_get(dev, "mem");
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if (IS_ERR(dwmac->clk_mem)) {
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if (IS_ERR(dwmac->clk_mem)) {
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dev_err(dev, "failed to get mem clock\n");
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dev_err(dev, "failed to get mem clock\n");
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@ -196,10 +233,11 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
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}
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}
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}
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}
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if (of_machine_is_compatible("fsl,imx8mp")) {
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if (of_machine_is_compatible("fsl,imx8mp") ||
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/* Binding doc describes the property:
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of_machine_is_compatible("fsl,imx93")) {
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is required by i.MX8MP.
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/* Binding doc describes the propety:
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is optional for i.MX8DXL.
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* is required by i.MX8MP, i.MX93.
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* is optinoal for i.MX8DXL.
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*/
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*/
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dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");
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dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");
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if (IS_ERR(dwmac->intf_regmap))
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if (IS_ERR(dwmac->intf_regmap))
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@ -296,9 +334,16 @@ static struct imx_dwmac_ops imx8dxl_dwmac_data = {
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.set_intf_mode = imx8dxl_set_intf_mode,
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.set_intf_mode = imx8dxl_set_intf_mode,
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};
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};
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static struct imx_dwmac_ops imx93_dwmac_data = {
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.addr_width = 32,
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.mac_rgmii_txclk_auto_adj = true,
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.set_intf_mode = imx93_set_intf_mode,
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};
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static const struct of_device_id imx_dwmac_match[] = {
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static const struct of_device_id imx_dwmac_match[] = {
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{ .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
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{ .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
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{ .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
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{ .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
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{ .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },
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{ }
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{ }
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};
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};
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MODULE_DEVICE_TABLE(of, imx_dwmac_match);
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MODULE_DEVICE_TABLE(of, imx_dwmac_match);
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