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PCI: xilinx: Update Zynq binding with Microblaze node

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Update Zynq PCI binding documentation with Microblaze node.

[bhelgaas: fix "microbalze_0_intc" typo]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Bharat Kumar Gogada 2016-02-11 21:58:10 +05:30 committed by Bjorn Helgaas
parent 2c51391d25
commit e5d4b2006c
1 changed files with 29 additions and 3 deletions
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32
Documentation/devicetree/bindings/pci/xilinx-pcie.txt
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@ -17,7 +17,7 @@ Required properties:
Please refer to the standard PCI bus binding document for a more
detailed explanation
Optional properties:
Optional properties for Zynq/Microblaze:
- bus-range: PCI bus numbers covered
Interrupt controller child node
@ -38,13 +38,13 @@ the four INTx interrupts in ISR and route them to this domain.
Example:
++++++++
Zynq:
pci_express: axi-pcie@50000000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "xlnx,axi-pcie-host-1.00.a";
reg = < 0x50000000 0x10000000 >;
reg = < 0x50000000 0x1000000 >;
device_type = "pci";
interrupts = < 0 52 4 >;
interrupt-map-mask = <0 0 0 7>;
@ -60,3 +60,29 @@ Example:
#interrupt-cells = <1>;
};
};
Microblaze:
pci_express: axi-pcie@10000000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "xlnx,axi-pcie-host-1.00.a";
reg = <0x10000000 0x4000000>;
device_type = "pci";
interrupt-parent = <&microblaze_0_intc>;
interrupts = <1 2>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 1>,
<0 0 0 2 &pcie_intc 2>,
<0 0 0 3 &pcie_intc 3>,
<0 0 0 4 &pcie_intc 4>;
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
pcie_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};