Merge branch irq/mchp-eic into irq/irqchip-next
* irq/mchp-eic: : . : New irqchip driver for the Microchip EIC block : . irqchip/mchp-eic: Fix return value check in mchp_eic_init() irqchip/mchp-eic: Add support for the Microchip EIC dt-bindings: microchip,eic: Add bindings for the Microchip EIC Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
commit
e6a767a175
@ -0,0 +1,73 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip External Interrupt Controller
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maintainers:
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- Claudiu Beznea <claudiu.beznea@microchip.com>
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description:
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This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
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support for handling up to 2 external interrupt lines.
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properties:
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compatible:
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enum:
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- microchip,sama7g5-eic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the input IRQ number (between 0 and 1), the second cell
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is the trigger type as defined in interrupt.txt present in this directory.
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interrupts:
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description: |
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Contains the GIC SPI IRQs mapped to the external interrupt lines. They
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should be specified sequentially from output 0 to output 1.
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minItems: 2
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maxItems: 2
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clocks:
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maxItems: 1
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clock-names:
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const: pclk
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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eic: interrupt-controller@e1628000 {
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compatible = "microchip,sama7g5-eic";
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reg = <0xe1628000 0x100>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
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clock-names = "pclk";
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};
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...
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@ -12254,6 +12254,12 @@ L: linux-crypto@vger.kernel.org
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S: Maintained
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F: drivers/crypto/atmel-ecc.*
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MICROCHIP EIC DRIVER
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M: Claudiu Beznea <claudiu.beznea@microchip.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Supported
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F: drivers/irqchip/irq-mchp-eic.c
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MICROCHIP I2C DRIVER
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M: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
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L: linux-i2c@vger.kernel.org
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@ -609,4 +609,12 @@ config APPLE_AIC
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Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
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such as the M1.
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config MCHP_EIC
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bool "Microchip External Interrupt Controller"
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depends on ARCH_AT91 || COMPILE_TEST
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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help
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Support for Microchip External Interrupt Controller.
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endmenu
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@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
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obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o
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obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
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obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
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obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
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280
drivers/irqchip/irq-mchp-eic.c
Normal file
280
drivers/irqchip/irq-mchp-eic.c
Normal file
@ -0,0 +1,280 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Microchip External Interrupt Controller driver
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*
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* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define MCHP_EIC_GFCS (0x0)
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#define MCHP_EIC_SCFG(x) (0x4 + (x) * 0x4)
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#define MCHP_EIC_SCFG_EN BIT(16)
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#define MCHP_EIC_SCFG_LVL BIT(9)
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#define MCHP_EIC_SCFG_POL BIT(8)
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#define MCHP_EIC_NIRQ (2)
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/*
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* struct mchp_eic - EIC private data structure
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* @base: base address
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* @clk: peripheral clock
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* @domain: irq domain
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* @irqs: irqs b/w eic and gic
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* @scfg: backup for scfg registers (necessary for backup and self-refresh mode)
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* @wakeup_source: wakeup source mask
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*/
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struct mchp_eic {
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void __iomem *base;
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struct clk *clk;
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struct irq_domain *domain;
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u32 irqs[MCHP_EIC_NIRQ];
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u32 scfg[MCHP_EIC_NIRQ];
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u32 wakeup_source;
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};
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static struct mchp_eic *eic;
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static void mchp_eic_irq_mask(struct irq_data *d)
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{
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unsigned int tmp;
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tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));
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tmp &= ~MCHP_EIC_SCFG_EN;
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writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
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irq_chip_mask_parent(d);
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}
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static void mchp_eic_irq_unmask(struct irq_data *d)
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{
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unsigned int tmp;
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tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));
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tmp |= MCHP_EIC_SCFG_EN;
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writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
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irq_chip_unmask_parent(d);
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}
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static int mchp_eic_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int parent_irq_type;
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unsigned int tmp;
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tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq));
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tmp &= ~(MCHP_EIC_SCFG_POL | MCHP_EIC_SCFG_LVL);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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tmp |= MCHP_EIC_SCFG_POL | MCHP_EIC_SCFG_LVL;
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parent_irq_type = IRQ_TYPE_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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tmp |= MCHP_EIC_SCFG_LVL;
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parent_irq_type = IRQ_TYPE_LEVEL_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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parent_irq_type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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tmp |= MCHP_EIC_SCFG_POL;
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parent_irq_type = IRQ_TYPE_EDGE_RISING;
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
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return irq_chip_set_type_parent(d, parent_irq_type);
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}
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static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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irq_set_irq_wake(eic->irqs[d->hwirq], on);
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if (on)
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eic->wakeup_source |= BIT(d->hwirq);
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else
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eic->wakeup_source &= ~BIT(d->hwirq);
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return 0;
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}
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static int mchp_eic_irq_suspend(void)
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{
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unsigned int hwirq;
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for (hwirq = 0; hwirq < MCHP_EIC_NIRQ; hwirq++)
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eic->scfg[hwirq] = readl_relaxed(eic->base +
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MCHP_EIC_SCFG(hwirq));
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if (!eic->wakeup_source)
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clk_disable_unprepare(eic->clk);
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return 0;
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}
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static void mchp_eic_irq_resume(void)
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{
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unsigned int hwirq;
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if (!eic->wakeup_source)
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clk_prepare_enable(eic->clk);
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for (hwirq = 0; hwirq < MCHP_EIC_NIRQ; hwirq++)
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writel_relaxed(eic->scfg[hwirq], eic->base +
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MCHP_EIC_SCFG(hwirq));
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}
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static struct syscore_ops mchp_eic_syscore_ops = {
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.suspend = mchp_eic_irq_suspend,
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.resume = mchp_eic_irq_resume,
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};
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static struct irq_chip mchp_eic_chip = {
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.name = "eic",
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED,
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.irq_mask = mchp_eic_irq_mask,
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.irq_unmask = mchp_eic_irq_unmask,
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.irq_set_type = mchp_eic_irq_set_type,
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.irq_ack = irq_chip_ack_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = mchp_eic_irq_set_wake,
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};
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static int mchp_eic_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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if (WARN_ON(nr_irqs != 1))
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return -EINVAL;
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ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
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if (ret || hwirq >= MCHP_EIC_NIRQ)
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return ret;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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break;
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case IRQ_TYPE_EDGE_FALLING:
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type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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type = IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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return -EINVAL;
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}
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &mchp_eic_chip, eic);
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = GIC_SPI;
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parent_fwspec.param[1] = eic->irqs[hwirq];
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
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}
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static const struct irq_domain_ops mchp_eic_domain_ops = {
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.translate = irq_domain_translate_twocell,
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.alloc = mchp_eic_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int mchp_eic_init(struct device_node *node, struct device_node *parent)
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{
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struct irq_domain *parent_domain = NULL;
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int ret, i;
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eic = kzalloc(sizeof(*eic), GFP_KERNEL);
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if (!eic)
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return -ENOMEM;
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eic->base = of_iomap(node, 0);
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if (!eic->base) {
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ret = -ENOMEM;
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goto free;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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ret = -ENODEV;
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goto unmap;
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}
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eic->clk = of_clk_get_by_name(node, "pclk");
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if (IS_ERR(eic->clk)) {
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ret = PTR_ERR(eic->clk);
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goto unmap;
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}
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ret = clk_prepare_enable(eic->clk);
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if (ret)
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goto unmap;
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for (i = 0; i < MCHP_EIC_NIRQ; i++) {
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struct of_phandle_args irq;
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/* Disable it, if any. */
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writel_relaxed(0UL, eic->base + MCHP_EIC_SCFG(i));
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ret = of_irq_parse_one(node, i, &irq);
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if (ret)
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goto clk_unprepare;
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if (WARN_ON(irq.args_count != 3)) {
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ret = -EINVAL;
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goto clk_unprepare;
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}
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eic->irqs[i] = irq.args[1];
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}
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eic->domain = irq_domain_add_hierarchy(parent_domain, 0, MCHP_EIC_NIRQ,
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node, &mchp_eic_domain_ops, eic);
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if (!eic->domain) {
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pr_err("%pOF: Failed to add domain\n", node);
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ret = -ENODEV;
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goto clk_unprepare;
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}
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register_syscore_ops(&mchp_eic_syscore_ops);
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pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ);
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return 0;
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clk_unprepare:
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clk_disable_unprepare(eic->clk);
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unmap:
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iounmap(eic->base);
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free:
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kfree(eic);
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return ret;
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(mchp_eic)
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IRQCHIP_MATCH("microchip,sama7g5-eic", mchp_eic_init)
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IRQCHIP_PLATFORM_DRIVER_END(mchp_eic)
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MODULE_DESCRIPTION("Microchip External Interrupt Controller");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea@microchip.com>");
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