tools headers UAPI: Sync drm/i915_drm.h with the kernel
To pick up the changes from:d1172ab3d4("drm/i915: Introduce struct class_instance for engines across the uAPI")96fd2c6633("drm/i915: Drop new chunks of context creation ABI (for now)")ea593dbba4("drm/i915: Allow contexts to share a single timeline across all engines")b917154172("drm/i915: Extend CONTEXT_CREATE to set parameters upon construction")e0695db729("drm/i915: Create/destroy VM (ppGTT) for use with contexts")9d1305ef80("drm/i915: Introduce the i915_user_extension_method")c8b502422b("drm/i915: Remove last traces of exec-id (GEM_BUSY)")d90c06d570("drm/i915: Fix I915_EXEC_RING_MASK")e886196469("drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+")be03564bd7("drm/i915: Include reminders about leaving no holes in uAPI enums")ba4fda620a("drm/i915: Optionally disable automatic recovery after a GPU reset") We still don't take into account the _IOC_SIZE() to differentiate ioctl cmds, so more work is needed to support the extension mechanism that is being used here so that we can differentiate DRM_IOCTL_I915_GEM_CONTEXT_CREATE from the newly introduced DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT cmd. This silences this perf build warning: Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h' diff -u tools/include/uapi/drm/i915_drm.h include/uapi/drm/i915_drm.h Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Brendan Gregg <brendan.d.gregg@gmail.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Luis Cláudio Gonçalves <lclaudio@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: https://lkml.kernel.org/n/tip-csn0vanmc7pevyka5qcg0xyw@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo
parent
b5b999dca6
commit
e6aff9f8bf
@ -62,6 +62,28 @@ extern "C" {
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/*
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* i915_user_extension: Base class for defining a chain of extensions
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*
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* Many interfaces need to grow over time. In most cases we can simply
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* extend the struct and have userspace pass in more data. Another option,
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* as demonstrated by Vulkan's approach to providing extensions for forward
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* and backward compatibility, is to use a list of optional structs to
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* provide those extra details.
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*
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* The key advantage to using an extension chain is that it allows us to
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* redefine the interface more easily than an ever growing struct of
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* increasing complexity, and for large parts of that interface to be
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* entirely optional. The downside is more pointer chasing; chasing across
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* the __user boundary with pointers encapsulated inside u64.
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*/
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struct i915_user_extension {
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__u64 next_extension;
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__u32 name;
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__u32 flags; /* All undefined bits must be zero. */
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__u32 rsvd[4]; /* Reserved for future use; must be zero. */
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};
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/*
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* MOCS indexes used for GPU surfaces, defining the cacheability of the
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* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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@ -99,9 +121,23 @@ enum drm_i915_gem_engine_class {
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I915_ENGINE_CLASS_VIDEO = 2,
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I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
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/* should be kept compact */
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I915_ENGINE_CLASS_INVALID = -1
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};
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/*
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* There may be more than one engine fulfilling any role within the system.
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* Each engine of a class is given a unique instance number and therefore
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* any engine can be specified by its class:instance tuplet. APIs that allow
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* access to any engine in the system will use struct i915_engine_class_instance
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* for this identification.
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*/
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struct i915_engine_class_instance {
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__u16 engine_class; /* see enum drm_i915_gem_engine_class */
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__u16 engine_instance;
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};
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/**
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* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
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*
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@ -319,6 +355,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_PERF_ADD_CONFIG 0x37
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#define DRM_I915_PERF_REMOVE_CONFIG 0x38
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#define DRM_I915_QUERY 0x39
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/* Must be kept compact -- no holes */
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@ -367,6 +404,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
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@ -476,6 +514,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
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#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
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#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
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#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
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#define I915_PARAM_HUC_STATUS 42
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@ -559,6 +598,8 @@ typedef struct drm_i915_irq_wait {
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*/
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#define I915_PARAM_MMAP_GTT_COHERENT 52
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/* Must be kept compact -- no holes and well documented */
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typedef struct drm_i915_getparam {
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__s32 param;
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/*
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@ -574,6 +615,7 @@ typedef struct drm_i915_getparam {
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#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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#define I915_SETPARAM_NUM_USED_FENCES 4
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/* Must be kept compact -- no holes */
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typedef struct drm_i915_setparam {
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int param;
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@ -972,7 +1014,7 @@ struct drm_i915_gem_execbuffer2 {
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* struct drm_i915_gem_exec_fence *fences.
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*/
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__u64 cliprects_ptr;
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#define I915_EXEC_RING_MASK (7<<0)
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#define I915_EXEC_RING_MASK (0x3f)
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#define I915_EXEC_DEFAULT (0<<0)
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#define I915_EXEC_RENDER (1<<0)
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#define I915_EXEC_BSD (2<<0)
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@ -1120,32 +1162,34 @@ struct drm_i915_gem_busy {
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* as busy may become idle before the ioctl is completed.
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*
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* Furthermore, if the object is busy, which engine is busy is only
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* provided as a guide. There are race conditions which prevent the
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* report of which engines are busy from being always accurate.
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* However, the converse is not true. If the object is idle, the
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* result of the ioctl, that all engines are idle, is accurate.
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* provided as a guide and only indirectly by reporting its class
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* (there may be more than one engine in each class). There are race
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* conditions which prevent the report of which engines are busy from
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* being always accurate. However, the converse is not true. If the
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* object is idle, the result of the ioctl, that all engines are idle,
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* is accurate.
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*
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* The returned dword is split into two fields to indicate both
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* the engines on which the object is being read, and the
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* engine on which it is currently being written (if any).
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* the engine classess on which the object is being read, and the
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* engine class on which it is currently being written (if any).
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*
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* The low word (bits 0:15) indicate if the object is being written
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* to by any engine (there can only be one, as the GEM implicit
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* synchronisation rules force writes to be serialised). Only the
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* engine for the last write is reported.
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* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
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* 1 not 0 etc) for the last write is reported.
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*
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* The high word (bits 16:31) are a bitmask of which engines are
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* currently reading from the object. Multiple engines may be
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* The high word (bits 16:31) are a bitmask of which engines classes
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* are currently reading from the object. Multiple engines may be
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* reading from the object simultaneously.
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*
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* The value of each engine is the same as specified in the
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* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
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* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
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* the I915_EXEC_RENDER engine for execution, and so it is never
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* The value of each engine class is the same as specified in the
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* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
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* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
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* reported as active itself. Some hardware may have parallel
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* execution engines, e.g. multiple media engines, which are
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* mapped to the same identifier in the EXECBUFFER2 ioctl and
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* so are not separately reported for busyness.
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* mapped to the same class identifier and so are not separately
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* reported for busyness.
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*
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* Caveat emptor:
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* Only the boolean result of this query is reliable; that is whether
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@ -1412,16 +1456,158 @@ struct drm_i915_gem_wait {
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};
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struct drm_i915_gem_context_create {
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/* output: id of new context*/
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__u32 ctx_id;
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__u32 ctx_id; /* output: id of new context*/
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__u32 pad;
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};
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struct drm_i915_gem_context_create_ext {
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__u32 ctx_id; /* output: id of new context*/
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__u32 flags;
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#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
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#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
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(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
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__u64 extensions;
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};
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struct drm_i915_gem_context_param {
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__u32 ctx_id;
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__u32 size;
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__u64 param;
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#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
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#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
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#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
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#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
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#define I915_CONTEXT_PARAM_BANNABLE 0x5
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#define I915_CONTEXT_PARAM_PRIORITY 0x6
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#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
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#define I915_CONTEXT_DEFAULT_PRIORITY 0
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#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
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/*
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* When using the following param, value should be a pointer to
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* drm_i915_gem_context_param_sseu.
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*/
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#define I915_CONTEXT_PARAM_SSEU 0x7
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/*
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* Not all clients may want to attempt automatic recover of a context after
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* a hang (for example, some clients may only submit very small incremental
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* batches relying on known logical state of previous batches which will never
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* recover correctly and each attempt will hang), and so would prefer that
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* the context is forever banned instead.
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*
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* If set to false (0), after a reset, subsequent (and in flight) rendering
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* from this context is discarded, and the client will need to create a new
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* context to use instead.
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*
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* If set to true (1), the kernel will automatically attempt to recover the
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* context by skipping the hanging batch and executing the next batch starting
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* from the default context state (discarding the incomplete logical context
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* state lost due to the reset).
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*
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* On creation, all new contexts are marked as recoverable.
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*/
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#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
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/* Must be kept compact -- no holes and well documented */
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__u64 value;
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};
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/**
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* Context SSEU programming
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*
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* It may be necessary for either functional or performance reason to configure
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* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
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* Sub-slice/EU).
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*
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* This is done by configuring SSEU configuration using the below
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* @struct drm_i915_gem_context_param_sseu for every supported engine which
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* userspace intends to use.
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*
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* Not all GPUs or engines support this functionality in which case an error
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* code -ENODEV will be returned.
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*
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* Also, flexibility of possible SSEU configuration permutations varies between
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* GPU generations and software imposed limitations. Requesting such a
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* combination will return an error code of -EINVAL.
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*
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* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
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* favour of a single global setting.
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*/
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struct drm_i915_gem_context_param_sseu {
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/*
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* Engine class & instance to be configured or queried.
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*/
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struct i915_engine_class_instance engine;
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/*
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* Unused for now. Must be cleared to zero.
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*/
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__u32 flags;
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/*
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* Mask of slices to enable for the context. Valid values are a subset
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* of the bitmask value returned for I915_PARAM_SLICE_MASK.
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*/
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__u64 slice_mask;
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/*
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* Mask of subslices to enable for the context. Valid values are a
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* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
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*/
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__u64 subslice_mask;
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/*
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* Minimum/Maximum number of EUs to enable per subslice for the
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* context. min_eus_per_subslice must be inferior or equal to
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* max_eus_per_subslice.
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*/
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__u16 min_eus_per_subslice;
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__u16 max_eus_per_subslice;
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/*
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* Unused for now. Must be cleared to zero.
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*/
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__u32 rsvd;
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};
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struct drm_i915_gem_context_create_ext_setparam {
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#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
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struct i915_user_extension base;
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struct drm_i915_gem_context_param param;
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};
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struct drm_i915_gem_context_destroy {
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__u32 ctx_id;
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__u32 pad;
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};
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/*
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* DRM_I915_GEM_VM_CREATE -
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*
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* Create a new virtual memory address space (ppGTT) for use within a context
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* on the same file. Extensions can be provided to configure exactly how the
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* address space is setup upon creation.
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*
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* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
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* returned in the outparam @id.
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*
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* No flags are defined, with all bits reserved and must be zero.
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*
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* An extension chain maybe provided, starting with @extensions, and terminated
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* by the @next_extension being 0. Currently, no extensions are defined.
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*
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* DRM_I915_GEM_VM_DESTROY -
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*
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* Destroys a previously created VM id, specified in @id.
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*
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* No extensions or flags are allowed currently, and so must be zero.
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*/
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struct drm_i915_gem_vm_control {
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__u64 extensions;
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__u32 flags;
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__u32 vm_id;
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};
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struct drm_i915_reg_read {
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/*
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* Register offset.
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@ -1434,6 +1620,7 @@ struct drm_i915_reg_read {
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__u64 val; /* Return value */
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};
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/* Known registers:
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*
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* Render engine timestamp - 0x2358 + 64bit - gen7+
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@ -1473,86 +1660,6 @@ struct drm_i915_gem_userptr {
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__u32 handle;
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};
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struct drm_i915_gem_context_param {
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__u32 ctx_id;
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__u32 size;
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__u64 param;
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#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
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#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
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#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
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#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
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#define I915_CONTEXT_PARAM_BANNABLE 0x5
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#define I915_CONTEXT_PARAM_PRIORITY 0x6
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#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
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#define I915_CONTEXT_DEFAULT_PRIORITY 0
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#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
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/*
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* When using the following param, value should be a pointer to
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* drm_i915_gem_context_param_sseu.
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*/
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#define I915_CONTEXT_PARAM_SSEU 0x7
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__u64 value;
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};
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/**
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* Context SSEU programming
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*
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* It may be necessary for either functional or performance reason to configure
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* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
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* Sub-slice/EU).
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*
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* This is done by configuring SSEU configuration using the below
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* @struct drm_i915_gem_context_param_sseu for every supported engine which
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* userspace intends to use.
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*
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* Not all GPUs or engines support this functionality in which case an error
|
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* code -ENODEV will be returned.
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*
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* Also, flexibility of possible SSEU configuration permutations varies between
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* GPU generations and software imposed limitations. Requesting such a
|
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* combination will return an error code of -EINVAL.
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*
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* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
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* favour of a single global setting.
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*/
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struct drm_i915_gem_context_param_sseu {
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/*
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* Engine class & instance to be configured or queried.
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*/
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__u16 engine_class;
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__u16 engine_instance;
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/*
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* Unused for now. Must be cleared to zero.
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*/
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__u32 flags;
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/*
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* Mask of slices to enable for the context. Valid values are a subset
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* of the bitmask value returned for I915_PARAM_SLICE_MASK.
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*/
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__u64 slice_mask;
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/*
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* Mask of subslices to enable for the context. Valid values are a
|
||||
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
|
||||
*/
|
||||
__u64 subslice_mask;
|
||||
|
||||
/*
|
||||
* Minimum/Maximum number of EUs to enable per subslice for the
|
||||
* context. min_eus_per_subslice must be inferior or equal to
|
||||
* max_eus_per_subslice.
|
||||
*/
|
||||
__u16 min_eus_per_subslice;
|
||||
__u16 max_eus_per_subslice;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 rsvd;
|
||||
};
|
||||
|
||||
enum drm_i915_oa_format {
|
||||
I915_OA_FORMAT_A13 = 1, /* HSW only */
|
||||
I915_OA_FORMAT_A29, /* HSW only */
|
||||
@ -1714,6 +1821,7 @@ struct drm_i915_perf_oa_config {
|
||||
struct drm_i915_query_item {
|
||||
__u64 query_id;
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
/*
|
||||
* When set to zero by userspace, this is filled with the size of the
|
||||
|
||||
Loading…
Reference in New Issue
Block a user