clocksource: timer-keystone: introduce clocksource driver for Keystone
Add broadcast clock-event device for the Keystone arch. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other. Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Santosh shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Ivan Khoronzhuk
Daniel Lezcano
parent
926b65e20d
commit
e6b7f580ba
@ -38,3 +38,4 @@ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
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obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
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obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
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244
drivers/clocksource/timer-keystone.c
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244
drivers/clocksource/timer-keystone.c
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@ -0,0 +1,244 @@
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/*
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* Keystone broadcast clock-event
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*
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* Copyright 2013 Texas Instruments, Inc.
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*
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* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_NAME "timer-keystone"
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/* Timer register offsets */
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#define TIM12 0x10
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#define TIM34 0x14
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#define PRD12 0x18
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#define PRD34 0x1c
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#define TCR 0x20
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#define TGCR 0x24
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#define INTCTLSTAT 0x44
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/* Timer register bitfields */
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#define TCR_ENAMODE_MASK 0xC0
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#define TCR_ENAMODE_ONESHOT_MASK 0x40
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#define TCR_ENAMODE_PERIODIC_MASK 0x80
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#define TGCR_TIM_UNRESET_MASK 0x03
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#define INTCTLSTAT_ENINT_MASK 0x01
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/**
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* struct keystone_timer: holds timer's data
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* @base: timer memory base address
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* @hz_period: cycles per HZ period
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* @event_dev: event device based on timer
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*/
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static struct keystone_timer {
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void __iomem *base;
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unsigned long hz_period;
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struct clock_event_device event_dev;
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} timer;
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static inline u32 keystone_timer_readl(unsigned long rg)
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{
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return readl_relaxed(timer.base + rg);
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}
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static inline void keystone_timer_writel(u32 val, unsigned long rg)
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{
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writel_relaxed(val, timer.base + rg);
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}
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/**
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* keystone_timer_barrier: write memory barrier
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* use explicit barrier to avoid using readl/writel non relaxed function
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* variants, because in our case non relaxed variants hide the true places
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* where barrier is needed.
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*/
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static inline void keystone_timer_barrier(void)
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{
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__iowmb();
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}
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/**
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* keystone_timer_config: configures timer to work in oneshot/periodic modes.
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* @ mode: mode to configure
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* @ period: cycles number to configure for
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*/
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static int keystone_timer_config(u64 period, enum clock_event_mode mode)
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{
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u32 tcr;
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u32 off;
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tcr = keystone_timer_readl(TCR);
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off = tcr & ~(TCR_ENAMODE_MASK);
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/* set enable mode */
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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tcr |= TCR_ENAMODE_ONESHOT_MASK;
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break;
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case CLOCK_EVT_MODE_PERIODIC:
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tcr |= TCR_ENAMODE_PERIODIC_MASK;
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break;
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default:
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return -1;
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}
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/* disable timer */
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keystone_timer_writel(off, TCR);
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/* here we have to be sure the timer has been disabled */
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keystone_timer_barrier();
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/* reset counter to zero, set new period */
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keystone_timer_writel(0, TIM12);
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keystone_timer_writel(0, TIM34);
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keystone_timer_writel(period & 0xffffffff, PRD12);
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keystone_timer_writel(period >> 32, PRD34);
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/*
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* enable timer
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* here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
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* have been written.
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*/
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keystone_timer_barrier();
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keystone_timer_writel(tcr, TCR);
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return 0;
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}
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static void keystone_timer_disable(void)
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{
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u32 tcr;
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tcr = keystone_timer_readl(TCR);
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/* disable timer */
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tcr &= ~(TCR_ENAMODE_MASK);
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keystone_timer_writel(tcr, TCR);
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}
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static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int keystone_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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return keystone_timer_config(cycles, evt->mode);
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}
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static void keystone_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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keystone_timer_config(timer.hz_period, CLOCK_EVT_MODE_PERIODIC);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_ONESHOT:
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keystone_timer_disable();
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break;
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default:
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break;
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}
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}
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static void __init keystone_timer_init(struct device_node *np)
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{
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struct clock_event_device *event_dev = &timer.event_dev;
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unsigned long rate;
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struct clk *clk;
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int irq, error;
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u32 tgcr;
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irq = irq_of_parse_and_map(np, 0);
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if (irq == NO_IRQ) {
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pr_err("%s: failed to map interrupts\n", __func__);
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return;
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}
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timer.base = of_iomap(np, 0);
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if (!timer.base) {
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pr_err("%s: failed to map registers\n", __func__);
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return;
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to get clock\n", __func__);
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iounmap(timer.base);
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return;
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}
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error = clk_prepare_enable(clk);
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if (error) {
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pr_err("%s: failed to enable clock\n", __func__);
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goto err;
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}
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rate = clk_get_rate(clk);
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/* disable, use internal clock source */
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keystone_timer_writel(0, TCR);
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/* here we have to be sure the timer has been disabled */
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keystone_timer_barrier();
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/* reset timer as 64-bit, no pre-scaler, plus features are disabled */
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tgcr = 0;
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keystone_timer_writel(0, TGCR);
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/* unreset timer */
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tgcr |= TGCR_TIM_UNRESET_MASK;
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keystone_timer_writel(tgcr, TGCR);
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/* init counter to zero */
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keystone_timer_writel(0, TIM12);
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keystone_timer_writel(0, TIM34);
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timer.hz_period = DIV_ROUND_UP(rate, HZ);
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/* enable timer interrupts */
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keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
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error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
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TIMER_NAME, event_dev);
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if (error) {
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pr_err("%s: failed to setup irq\n", __func__);
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goto err;
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}
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/* setup clockevent */
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event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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event_dev->set_next_event = keystone_set_next_event;
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event_dev->set_mode = keystone_set_mode;
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event_dev->cpumask = cpu_all_mask;
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event_dev->owner = THIS_MODULE;
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event_dev->name = TIMER_NAME;
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event_dev->irq = irq;
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clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
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pr_info("keystone timer clock @%lu Hz\n", rate);
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return;
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err:
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clk_put(clk);
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iounmap(timer.base);
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}
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CLOCKSOURCE_OF_DECLARE(keystone_timer, "ti,keystone-timer",
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keystone_timer_init);
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