Merge branch 'eliminate-config_nr_cpus-dependency-in-dpaa-eth-and-enable-compile_test-in-fsl_qbman'
Vladimir Oltean says: ==================== Eliminate CONFIG_NR_CPUS dependency in dpaa-eth and enable COMPILE_TEST in fsl_qbman Breno's previous attempt at enabling COMPILE_TEST for the fsl_qbman driver (now included here as patch 5/5) triggered compilation warnings for large CONFIG_NR_CPUS values: https://lore.kernel.org/all/202406261920.l5pzM1rj-lkp@intel.com/ Patch 1/5 switches two NR_CPUS arrays in the dpaa-eth driver to dynamic allocation to avoid that warning. There is more NR_CPUS usage in the fsl-qbman driver, but that looks relatively harmless and I couldn't find a good reason to change it. I noticed, while testing, that the driver doesn't actually work properly with high CONFIG_NR_CPUS values, and patch 2/5 addresses that. During code analysis, I have identified two places which treat conditions that can never happen. Patches 3/5 and 4/5 simplify the probing code - dpaa_fq_setup() - just a little bit. Finally we have at 5/5 the patch that triggered all of this. There is an okay from Herbert to take it via netdev, despite it being on soc/qbman: https://lore.kernel.org/all/Zns%2FeVVBc7pdv0yM@gondor.apana.org.au/ Link to v1: https://lore.kernel.org/netdev/20240710230025.46487-1-vladimir.oltean@nxp.com/ ==================== Link: https://patch.msgid.link/20240713225336.1746343-1-vladimir.oltean@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
e6c29506b2
@ -371,6 +371,7 @@ static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
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void *type_data)
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{
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struct dpaa_priv *priv = netdev_priv(net_dev);
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int num_txqs_per_tc = dpaa_num_txqs_per_tc();
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struct tc_mqprio_qopt *mqprio = type_data;
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u8 num_tc;
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int i;
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@ -398,12 +399,12 @@ static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
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netdev_set_num_tc(net_dev, num_tc);
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for (i = 0; i < num_tc; i++)
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netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
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i * DPAA_TC_TXQ_NUM);
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netdev_set_tc_queue(net_dev, i, num_txqs_per_tc,
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i * num_txqs_per_tc);
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out:
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priv->num_tc = num_tc ? : 1;
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netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
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netif_set_real_num_tx_queues(net_dev, priv->num_tc * num_txqs_per_tc);
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return 0;
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}
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@ -649,7 +650,7 @@ static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
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fq->wq = 6;
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break;
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case FQ_TYPE_TX:
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switch (idx / DPAA_TC_TXQ_NUM) {
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switch (idx / dpaa_num_txqs_per_tc()) {
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case 0:
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/* Low priority (best effort) */
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fq->wq = 6;
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@ -667,8 +668,8 @@ static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
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fq->wq = 0;
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break;
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default:
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WARN(1, "Too many TX FQs: more than %d!\n",
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DPAA_ETH_TXQ_NUM);
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WARN(1, "Too many TX FQs: more than %zu!\n",
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dpaa_max_num_txqs());
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}
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break;
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default:
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@ -740,7 +741,8 @@ static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
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port_fqs->rx_pcdq = &dpaa_fq[0];
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if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
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if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list,
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FQ_TYPE_TX_CONF_MQ))
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goto fq_alloc_failed;
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dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
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@ -755,7 +757,7 @@ static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
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port_fqs->tx_defq = &dpaa_fq[0];
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if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
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if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list, FQ_TYPE_TX))
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goto fq_alloc_failed;
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return 0;
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@ -931,14 +933,18 @@ static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
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}
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}
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static void dpaa_fq_setup(struct dpaa_priv *priv,
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const struct dpaa_fq_cbs *fq_cbs,
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struct fman_port *tx_port)
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static int dpaa_fq_setup(struct dpaa_priv *priv,
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const struct dpaa_fq_cbs *fq_cbs,
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struct fman_port *tx_port)
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{
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int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
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const cpumask_t *affine_cpus = qman_affine_cpus();
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u16 channels[NR_CPUS];
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struct dpaa_fq *fq;
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u16 *channels;
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channels = kcalloc(num_possible_cpus(), sizeof(u16), GFP_KERNEL);
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if (!channels)
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return -ENOMEM;
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for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
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channels[num_portals++] = qman_affine_channel(cpu);
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@ -965,11 +971,7 @@ static void dpaa_fq_setup(struct dpaa_priv *priv,
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case FQ_TYPE_TX:
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dpaa_setup_egress(priv, fq, tx_port,
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&fq_cbs->egress_ern);
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/* If we have more Tx queues than the number of cores,
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* just ignore the extra ones.
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*/
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if (egress_cnt < DPAA_ETH_TXQ_NUM)
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priv->egress_fqs[egress_cnt++] = &fq->fq_base;
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priv->egress_fqs[egress_cnt++] = &fq->fq_base;
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break;
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case FQ_TYPE_TX_CONF_MQ:
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priv->conf_fqs[conf_cnt++] = &fq->fq_base;
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@ -987,16 +989,9 @@ static void dpaa_fq_setup(struct dpaa_priv *priv,
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}
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}
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/* Make sure all CPUs receive a corresponding Tx queue. */
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while (egress_cnt < DPAA_ETH_TXQ_NUM) {
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list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
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if (fq->fq_type != FQ_TYPE_TX)
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continue;
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priv->egress_fqs[egress_cnt++] = &fq->fq_base;
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if (egress_cnt == DPAA_ETH_TXQ_NUM)
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break;
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}
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}
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kfree(channels);
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return 0;
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}
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static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
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@ -1004,7 +999,7 @@ static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
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{
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int i;
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for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
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for (i = 0; i < dpaa_max_num_txqs(); i++)
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if (priv->egress_fqs[i] == tx_fq)
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return i;
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@ -3324,7 +3319,7 @@ static int dpaa_eth_probe(struct platform_device *pdev)
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/* Allocate this early, so we can store relevant information in
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* the private area
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*/
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net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
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net_dev = alloc_etherdev_mq(sizeof(*priv), dpaa_max_num_txqs());
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if (!net_dev) {
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dev_err(dev, "alloc_etherdev_mq() failed\n");
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return -ENOMEM;
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@ -3339,6 +3334,22 @@ static int dpaa_eth_probe(struct platform_device *pdev)
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priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
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priv->egress_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
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sizeof(*priv->egress_fqs),
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GFP_KERNEL);
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if (!priv->egress_fqs) {
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err = -ENOMEM;
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goto free_netdev;
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}
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priv->conf_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
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sizeof(*priv->conf_fqs),
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GFP_KERNEL);
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if (!priv->conf_fqs) {
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err = -ENOMEM;
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goto free_netdev;
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}
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mac_dev = dpaa_mac_dev_get(pdev);
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if (IS_ERR(mac_dev)) {
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netdev_err(net_dev, "dpaa_mac_dev_get() failed\n");
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@ -3416,7 +3427,9 @@ static int dpaa_eth_probe(struct platform_device *pdev)
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*/
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dpaa_eth_add_channel(priv->channel, &pdev->dev);
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dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
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err = dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
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if (err)
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goto free_dpaa_bps;
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/* Create a congestion group for this netdev, with
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* dynamically-allocated CGR ID.
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@ -3462,7 +3475,8 @@ static int dpaa_eth_probe(struct platform_device *pdev)
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}
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priv->num_tc = 1;
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netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
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netif_set_real_num_tx_queues(net_dev,
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priv->num_tc * dpaa_num_txqs_per_tc());
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/* Initialize NAPI */
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err = dpaa_napi_add(net_dev);
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@ -18,10 +18,6 @@
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/* Number of prioritised traffic classes */
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#define DPAA_TC_NUM 4
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/* Number of Tx queues per traffic class */
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#define DPAA_TC_TXQ_NUM NR_CPUS
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/* Total number of Tx queues */
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#define DPAA_ETH_TXQ_NUM (DPAA_TC_NUM * DPAA_TC_TXQ_NUM)
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/* More detailed FQ types - used for fine-grained WQ assignments */
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enum dpaa_fq_type {
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@ -142,8 +138,8 @@ struct dpaa_priv {
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struct mac_device *mac_dev;
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struct device *rx_dma_dev;
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struct device *tx_dma_dev;
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struct qman_fq *egress_fqs[DPAA_ETH_TXQ_NUM];
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struct qman_fq *conf_fqs[DPAA_ETH_TXQ_NUM];
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struct qman_fq **egress_fqs;
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struct qman_fq **conf_fqs;
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u16 channel;
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struct list_head dpaa_fq_list;
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@ -185,4 +181,16 @@ extern const struct ethtool_ops dpaa_ethtool_ops;
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/* from dpaa_eth_sysfs.c */
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void dpaa_eth_sysfs_remove(struct device *dev);
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void dpaa_eth_sysfs_init(struct device *dev);
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static inline size_t dpaa_num_txqs_per_tc(void)
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{
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return num_possible_cpus();
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}
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/* Total number of Tx queues */
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static inline size_t dpaa_max_num_txqs(void)
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{
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return DPAA_TC_NUM * dpaa_num_txqs_per_tc();
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}
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#endif /* __DPAA_H */
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@ -457,12 +457,16 @@ static int dpaa_set_coalesce(struct net_device *dev,
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struct netlink_ext_ack *extack)
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{
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const cpumask_t *cpus = qman_affine_cpus();
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bool needs_revert[NR_CPUS] = {false};
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struct qman_portal *portal;
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u32 period, prev_period;
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u8 thresh, prev_thresh;
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bool *needs_revert;
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int cpu, res;
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needs_revert = kcalloc(num_possible_cpus(), sizeof(bool), GFP_KERNEL);
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if (!needs_revert)
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return -ENOMEM;
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period = c->rx_coalesce_usecs;
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thresh = c->rx_max_coalesced_frames;
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@ -485,6 +489,8 @@ static int dpaa_set_coalesce(struct net_device *dev,
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needs_revert[cpu] = true;
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}
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kfree(needs_revert);
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return 0;
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revert_values:
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@ -498,6 +504,8 @@ revert_values:
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qman_dqrr_set_ithresh(portal, prev_thresh);
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}
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kfree(needs_revert);
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return res;
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}
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menuconfig FSL_DPAA
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bool "QorIQ DPAA1 framework support"
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depends on ((FSL_SOC_BOOKE || ARCH_LAYERSCAPE) && ARCH_DMA_ADDR_T_64BIT)
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depends on ((FSL_SOC_BOOKE || ARCH_LAYERSCAPE || COMPILE_TEST) && ARCH_DMA_ADDR_T_64BIT)
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select GENERIC_ALLOCATOR
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help
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The Freescale Data Path Acceleration Architecture (DPAA) is a set of
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