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Mediatek DRM Next for Linux 5.11-2

Browse Source 
1. Add MT8167 support
 2. Cleanup function
 3. Convert the dpi bindings to yaml
 4. Drop local dma_parms
 5. Fix formatting and provide missing member description
 6. Introduce GEM object functions
 7. Fix aliases name
 8. Move MIPI DSI phy driver to phy folder
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Merge tag 'mediatek-drm-next-5.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next

Mediatek DRM Next for Linux 5.11-2

1. Add MT8167 support
2. Cleanup function
3. Convert the dpi bindings to yaml
4. Drop local dma_parms
5. Fix formatting and provide missing member description
6. Introduce GEM object functions
7. Fix aliases name
8. Move MIPI DSI phy driver to phy folder

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20201130234807.936-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie 2020-12-03 13:13:32 +10:00
commit e6c7c9d01f
18 changed files with 185 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
View File

@ -43,7 +43,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
the supported chips are mt2701, mt7623, mt2712 and mt8173.
the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
@ -59,7 +59,7 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-ovl"
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
the supported chips are mt2701 and mt8173.
the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as

42
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
View File

@ -1,42 +0,0 @@
Mediatek DPI Device
===================
The Mediatek DPI function block is a sink of the display subsystem and
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "pixel", "engine", and "pll"
- port: Output port node with endpoint definitions as described in
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached HDMI or LVDS encoder chip.
Optional properties:
- pinctrl-names: Contain "default" and "sleep".
Example:
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0 0x1401d000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dpi_pin_func>;
pinctrl-1 = <&dpi_pin_idle>;
port {
dpi0_out: endpoint {
remote-endpoint = <&hdmi0_in>;
};
};
};

98
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml Normal file
View File

@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: mediatek DPI Controller Device Tree Bindings
maintainers:
- CK Hu <ck.hu@mediatek.com>
- Jitao shi <jitao.shi@mediatek.com>
description: |
The Mediatek DPI function block is a sink of the display subsystem and
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
output bus.
properties:
compatible:
enum:
- mediatek,mt2701-dpi
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Pixel Clock
- description: Engine Clock
- description: DPI PLL
clock-names:
items:
- const: pixel
- const: engine
- const: pll
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
items:
- const: default
- const: sleep
port:
type: object
description:
Output port node with endpoint definitions as described in
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached HDMI or LVDS encoder chip.
properties:
endpoint:
type: object
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dpi_pin_func>;
pinctrl-1 = <&dpi_pin_idle>;
port {
dpi0_out: endpoint {
remote-endpoint = <&hdmi0_in>;
};
};
};
...

1
MAINTAINERS
View File

@ -5870,6 +5870,7 @@ S: Supported
F: Documentation/devicetree/bindings/display/mediatek/
F: drivers/gpu/drm/mediatek/
F: drivers/phy/mediatek/phy-mtk-hdmi*
F: drivers/phy/mediatek/phy-mtk-mipi*
DRM DRIVERS FOR NVIDIA TEGRA
M: Thierry Reding <thierry.reding@gmail.com>

1
drivers/gpu/drm/mediatek/Kconfig
View File

@ -13,6 +13,7 @@ config DRM_MEDIATEK
select DRM_PANEL
select MEMORY
select MTK_SMI
select PHY_MTK_MIPI_DSI
select VIDEOMODE_HELPERS
help
Choose this option if you have a Mediatek SoCs.

3
drivers/gpu/drm/mediatek/Makefile
View File

@ -10,9 +10,6 @@ mediatek-drm-y := mtk_disp_color.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_mipi_tx.o \
mtk_mt8173_mipi_tx.o \
mtk_mt8183_mipi_tx.o \
mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o

7
drivers/gpu/drm/mediatek/mtk_disp_color.c
View File

@ -16,6 +16,7 @@
#define DISP_COLOR_CFG_MAIN 0x0400
#define DISP_COLOR_START_MT2701 0x0f00
#define DISP_COLOR_START_MT8167 0x0400
#define DISP_COLOR_START_MT8173 0x0c00
#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
@ -149,6 +150,10 @@ static const struct mtk_disp_color_data mt2701_color_driver_data = {
.color_offset = DISP_COLOR_START_MT2701,
};
static const struct mtk_disp_color_data mt8167_color_driver_data = {
.color_offset = DISP_COLOR_START_MT8167,
};
static const struct mtk_disp_color_data mt8173_color_driver_data = {
.color_offset = DISP_COLOR_START_MT8173,
};
@ -156,6 +161,8 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = {
static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-color",
.data = &mt2701_color_driver_data},
{ .compatible = "mediatek,mt8167-disp-color",
.data = &mt8167_color_driver_data},
{ .compatible = "mediatek,mt8173-disp-color",
.data = &mt8173_color_driver_data},
{},

47
drivers/gpu/drm/mediatek/mtk_drm_ddp.c
View File

@ -25,6 +25,19 @@
#define INT_MUTEX BIT(1)
#define MT8167_MUTEX_MOD_DISP_PWM 1
#define MT8167_MUTEX_MOD_DISP_OVL0 6
#define MT8167_MUTEX_MOD_DISP_OVL1 7
#define MT8167_MUTEX_MOD_DISP_RDMA0 8
#define MT8167_MUTEX_MOD_DISP_RDMA1 9
#define MT8167_MUTEX_MOD_DISP_WDMA0 10
#define MT8167_MUTEX_MOD_DISP_CCORR 11
#define MT8167_MUTEX_MOD_DISP_COLOR 12
#define MT8167_MUTEX_MOD_DISP_AAL 13
#define MT8167_MUTEX_MOD_DISP_GAMMA 14
#define MT8167_MUTEX_MOD_DISP_DITHER 15
#define MT8167_MUTEX_MOD_DISP_UFOE 16
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA0 13
@ -73,6 +86,8 @@
#define MUTEX_SOF_DPI1 4
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
#define MT8167_MUTEX_SOF_DPI0 2
#define MT8167_MUTEX_SOF_DPI1 3
struct mtk_disp_mutex {
@ -135,6 +150,21 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
[DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
[DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
[DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@ -163,6 +193,13 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
[DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
};
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
static const struct mtk_ddp_data mt8167_ddp_driver_data = {
.mutex_mod = mt8167_mutex_mod,
.mutex_sof = mt8167_mutex_sof,
.mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
.no_clk = true,
};
static const struct mtk_ddp_data mt8173_ddp_driver_data = {
.mutex_mod = mt8173_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
.data = &mt2701_ddp_driver_data},
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = &mt2712_ddp_driver_data},
{ .compatible = "mediatek,mt8167-disp-mutex",
.data = &mt8167_ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = &mt8173_ddp_driver_data},
{},

2
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
View File

@ -359,7 +359,7 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl_2l",
[MTK_DISP_OVL_2L] = "ovl-2l",
[MTK_DISP_RDMA] = "rdma",
[MTK_DISP_WDMA] = "wdma",
[MTK_DISP_COLOR] = "color",

28
drivers/gpu/drm/mediatek/mtk_drm_drv.c
View File

@ -241,21 +241,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
if (!dma_dev->dma_parms) {
private->dma_parms_allocated = true;
dma_dev->dma_parms =
devm_kzalloc(drm->dev, sizeof(*dma_dev->dma_parms),
GFP_KERNEL);
}
if (!dma_dev->dma_parms) {
ret = -ENOMEM;
goto put_dma_dev;
}
ret = dma_set_max_seg_size(dma_dev, (unsigned int)DMA_BIT_MASK(32));
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_unset_dma_parms;
goto err_component_unbind;
}
/*
@ -266,18 +255,13 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->irq_enabled = true;
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret < 0)
goto err_unset_dma_parms;
goto err_component_unbind;
drm_kms_helper_poll_init(drm);
drm_mode_config_reset(drm);
return 0;
err_unset_dma_parms:
if (private->dma_parms_allocated)
dma_dev->dma_parms = NULL;
put_dma_dev:
put_device(private->dma_dev);
err_component_unbind:
component_unbind_all(drm->dev, drm);
put_mutex_dev:
@ -287,14 +271,9 @@ put_mutex_dev:
static void mtk_drm_kms_deinit(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
drm_kms_helper_poll_fini(drm);
drm_atomic_helper_shutdown(drm);
if (private->dma_parms_allocated)
private->dma_dev->dma_parms = NULL;
component_unbind_all(drm->dev, drm);
}
@ -631,7 +610,6 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_mipi_tx_driver,
&mtk_dsi_driver,
};

3
drivers/gpu/drm/mediatek/mtk_drm_drv.h
View File

@ -44,8 +44,6 @@ struct mtk_drm_private {
struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
bool dma_parms_allocated;
};
extern struct platform_driver mtk_ddp_driver;
@ -54,6 +52,5 @@ extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
extern struct platform_driver mtk_mipi_tx_driver;
#endif /* MTK_DRM_DRV_H */

27
drivers/gpu/drm/mediatek/mtk_hdmi.c
View File

@ -875,19 +875,8 @@ static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
mtk_hdmi_hw_msic_setting(hdmi, mode);
}
static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
{
mtk_hdmi_hw_send_aud_packet(hdmi, enable);
return 0;
}
static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
{
mtk_hdmi_hw_ncts_enable(hdmi, on);
return 0;
}
static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
{
enum hdmi_aud_channel_type chan_type;
u8 chan_count;
@ -917,8 +906,6 @@ static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
return 0;
}
static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
@ -926,7 +913,7 @@ static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
{
unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
mtk_hdmi_hw_ncts_enable(hdmi, false);
mtk_hdmi_hw_aud_src_disable(hdmi);
mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
@ -964,7 +951,7 @@ static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
struct drm_display_mode *display_mode)
{
mtk_hdmi_hw_aud_mute(hdmi);
mtk_hdmi_aud_enable_packet(hdmi, false);
mtk_hdmi_hw_send_aud_packet(hdmi, false);
mtk_hdmi_aud_set_input(hdmi);
mtk_hdmi_aud_set_src(hdmi, display_mode);
@ -973,8 +960,8 @@ static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
usleep_range(50, 100);
mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
mtk_hdmi_aud_enable_packet(hdmi, true);
mtk_hdmi_hw_ncts_enable(hdmi, true);
mtk_hdmi_hw_send_aud_packet(hdmi, true);
mtk_hdmi_hw_aud_unmute(hdmi);
return 0;
}
@ -1102,13 +1089,13 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
{
mtk_hdmi_aud_enable_packet(hdmi, true);
mtk_hdmi_hw_send_aud_packet(hdmi, true);
hdmi->audio_enable = true;
}
static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
{
mtk_hdmi_aud_enable_packet(hdmi, false);
mtk_hdmi_hw_send_aud_packet(hdmi, false);
hdmi->audio_enable = false;
}

7
drivers/phy/mediatek/Kconfig
View File

@ -42,3 +42,10 @@ config PHY_MTK_HDMI
select GENERIC_PHY
help
Support HDMI PHY for Mediatek SoCs.
config PHY_MTK_MIPI_DSI
tristate "MediaTek MIPI-DSI Driver"
depends on ARCH_MEDIATEK && OF
select GENERIC_PHY
help
Support MIPI DSI for Mediatek SoCs.

5
drivers/phy/mediatek/Makefile
View File

@ -11,3 +11,8 @@ phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o
obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o

2
drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c → drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
View File

@ -4,7 +4,7 @@
* Author: jitao.shi <jitao.shi@mediatek.com>
*/
#include "mtk_mipi_tx.h"
#include "phy-mtk-mipi-dsi.h"
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)

2
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c → drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
View File

@ -4,7 +4,7 @@
* Author: jitao.shi <jitao.shi@mediatek.com>
*/
#include "mtk_mipi_tx.h"
#include "phy-mtk-mipi-dsi.h"
#define MIPITX_LANE_CON 0x000c
#define RG_DSI_CPHY_T1DRV_EN BIT(0)

5
drivers/gpu/drm/mediatek/mtk_mipi_tx.c → drivers/phy/mediatek/phy-mtk-mipi-dsi.c
View File

@ -3,7 +3,7 @@
* Copyright (c) 2015 MediaTek Inc.
*/
#include "mtk_mipi_tx.h"
#include "phy-mtk-mipi-dsi.h"
inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
{
@ -242,4 +242,7 @@ struct platform_driver mtk_mipi_tx_driver = {
.of_match_table = mtk_mipi_tx_match,
},
};
module_platform_driver(mtk_mipi_tx_driver);
MODULE_DESCRIPTION("MediaTek MIPI TX Driver");
MODULE_LICENSE("GPL v2");

0
drivers/gpu/drm/mediatek/mtk_mipi_tx.h → drivers/phy/mediatek/phy-mtk-mipi-dsi.h
View File