drm/i915: Pass crtc_state down to cnl dpll funcs
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-7-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
@ -2233,11 +2233,11 @@ int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
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static bool
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static bool
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cnl_ddi_calculate_wrpll(int clock,
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cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
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struct drm_i915_private *dev_priv,
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struct skl_wrpll_params *wrpll_params)
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struct skl_wrpll_params *wrpll_params)
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{
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{
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u32 afe_clock = clock * 5;
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struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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u32 afe_clock = crtc_state->port_clock * 5;
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u32 ref_clock;
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u32 ref_clock;
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u32 dco_min = 7998000;
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u32 dco_min = 7998000;
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u32 dco_max = 10000000;
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u32 dco_max = 10000000;
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@ -2273,23 +2273,20 @@ cnl_ddi_calculate_wrpll(int clock,
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ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
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ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
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cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
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cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
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kdiv);
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pdiv, qdiv, kdiv);
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return true;
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return true;
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}
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}
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static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
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static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
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struct intel_crtc_state *crtc_state,
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int clock)
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{
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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u32 cfgcr0, cfgcr1;
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u32 cfgcr0, cfgcr1;
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struct skl_wrpll_params wrpll_params = { 0, };
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struct skl_wrpll_params wrpll_params = { 0, };
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cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
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cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
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if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
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if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
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return false;
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return false;
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cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
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cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
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@ -2310,14 +2307,14 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
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}
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}
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static bool
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static bool
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cnl_ddi_dp_set_dpll_hw_state(int clock,
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cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
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struct intel_dpll_hw_state *dpll_hw_state)
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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{
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u32 cfgcr0;
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u32 cfgcr0;
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cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
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cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
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switch (clock / 2) {
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switch (crtc_state->port_clock / 2) {
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case 81000:
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case 81000:
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cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
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cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
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break;
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break;
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@ -2355,22 +2352,20 @@ static struct intel_shared_dpll *
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cnl_get_dpll(struct intel_crtc_state *crtc_state,
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cnl_get_dpll(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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struct intel_encoder *encoder)
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{
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_shared_dpll *pll;
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struct intel_shared_dpll *pll;
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int clock = crtc_state->port_clock;
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bool bret;
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bool bret;
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struct intel_dpll_hw_state dpll_hw_state;
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struct intel_dpll_hw_state dpll_hw_state;
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memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
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memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
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bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
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if (!bret) {
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if (!bret) {
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DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
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DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
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return NULL;
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return NULL;
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}
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}
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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} else if (intel_crtc_has_dp_encoder(crtc_state)) {
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bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
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bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state, &dpll_hw_state);
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if (!bret) {
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if (!bret) {
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DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
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DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
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return NULL;
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return NULL;
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@ -2539,7 +2534,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
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ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
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ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
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else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
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else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
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ret = cnl_ddi_calculate_wrpll(crtc_state, &pll_params);
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else
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else
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ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
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ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
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