wifi: rtw89: add counters of register-based H2C/C2H
The register-based H2C/C2H are used to exchange information between driver and firmware, but only apply to narrow area because its data size is smaller than regular packet-based H2C/C2H. This kind of H2C/C2H must be paired. To identify if any H2C/C2H is missing, update counters to help diagnose this kind of problems. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20230316063956.71687-1-pkshih@realtek.com
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@ -3140,8 +3140,10 @@ struct rtw89_chip_info {
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u32 txwd_body_size;
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u32 h2c_ctrl_reg;
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const u32 *h2c_regs;
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struct rtw89_reg_def h2c_counter_reg;
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u32 c2h_ctrl_reg;
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const u32 *c2h_regs;
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struct rtw89_reg_def c2h_counter_reg;
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const struct rtw89_page_regs *page_regs;
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bool cfo_src_fd;
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const struct rtw89_reg_def *dcfo_comp;
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@ -3268,6 +3270,8 @@ struct rtw89_fw_info {
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struct completion completion;
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u8 h2c_seq;
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u8 rec_seq;
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u8 h2c_counter;
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u8 c2h_counter;
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struct rtw89_fw_suit normal;
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struct rtw89_fw_suit wowlan;
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bool fw_log_enable;
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@ -615,6 +615,8 @@ int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type)
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fw_info->h2c_seq = 0;
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fw_info->rec_seq = 0;
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fw_info->h2c_counter = 0;
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fw_info->c2h_counter = 0;
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rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX;
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rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX;
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@ -2724,6 +2726,7 @@ static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
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struct rtw89_mac_h2c_info *info)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_fw_info *fw_info = &rtwdev->fw;
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const u32 *h2c_reg = chip->h2c_regs;
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u8 i, val, len;
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int ret;
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@ -2743,6 +2746,9 @@ static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
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for (i = 0; i < RTW89_H2CREG_MAX; i++)
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rtw89_write32(rtwdev, h2c_reg[i], info->h2creg[i]);
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fw_info->h2c_counter++;
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rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
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chip->h2c_counter_reg.mask, fw_info->h2c_counter);
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rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);
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return 0;
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@ -2752,6 +2758,7 @@ static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
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struct rtw89_mac_c2h_info *info)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_fw_info *fw_info = &rtwdev->fw;
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const u32 *c2h_reg = chip->c2h_regs;
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u32 ret;
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u8 i, val;
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@ -2775,6 +2782,10 @@ static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
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info->content_len = (RTW89_GET_C2H_HDR_LEN(*info->c2hreg) << 2) -
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RTW89_C2HREG_HDR_LEN;
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fw_info->c2h_counter++;
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rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
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chip->c2h_counter_reg.mask, fw_info->c2h_counter);
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return 0;
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}
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@ -3398,6 +3398,8 @@ int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
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if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
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return -EFAULT;
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rtw89_write32(rtwdev, R_AX_UDM1, 0);
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rtw89_write32(rtwdev, R_AX_UDM2, 0);
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rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
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rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
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rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
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@ -207,6 +207,11 @@
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#define R_AX_UDM0 0x01F0
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#define R_AX_UDM1 0x01F4
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#define B_AX_UDM1_MASK GENMASK(31, 16)
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#define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
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#define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
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#define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
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#define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
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#define R_AX_UDM2 0x01F8
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#define R_AX_UDM3 0x01FC
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@ -2136,9 +2136,11 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.h2c_desc_size = sizeof(struct rtw89_txwd_body),
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.txwd_body_size = sizeof(struct rtw89_txwd_body),
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.h2c_ctrl_reg = R_AX_H2CREG_CTRL,
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.h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
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.h2c_regs = rtw8852a_h2c_regs,
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.c2h_ctrl_reg = R_AX_C2HREG_CTRL,
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.c2h_regs = rtw8852a_c2h_regs,
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.page_regs = &rtw8852a_page_regs,
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.cfo_src_fd = false,
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.dcfo_comp = &rtw8852a_dcfo_comp,
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@ -2557,8 +2557,10 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.h2c_desc_size = sizeof(struct rtw89_txwd_body),
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.txwd_body_size = sizeof(struct rtw89_txwd_body),
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.h2c_ctrl_reg = R_AX_H2CREG_CTRL,
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.h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
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.h2c_regs = rtw8852b_h2c_regs,
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.c2h_ctrl_reg = R_AX_C2HREG_CTRL,
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8852b_c2h_regs,
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.page_regs = &rtw8852b_page_regs,
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.cfo_src_fd = true,
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@ -2872,8 +2872,10 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.h2c_desc_size = sizeof(struct rtw89_rxdesc_short),
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.txwd_body_size = sizeof(struct rtw89_txwd_body_v1),
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.h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1,
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.h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
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.h2c_regs = rtw8852c_h2c_regs,
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.c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
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.c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
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.c2h_regs = rtw8852c_c2h_regs,
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.page_regs = &rtw8852c_page_regs,
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.cfo_src_fd = false,
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